From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D416C4332F for ; Wed, 2 Feb 2022 18:15:37 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 830E9838F9; Wed, 2 Feb 2022 19:15:34 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="QXliQPfe"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4AB4883900; Wed, 2 Feb 2022 19:15:33 +0100 (CET) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EB8C0838D5 for ; Wed, 2 Feb 2022 19:15:29 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=hnagalla@ti.com Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 212IFSYs098135 for ; Wed, 2 Feb 2022 12:15:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1643825728; bh=IbgNaikRMZgtyPwtV8jHGMGdk/qN8tevWcl8mCveD64=; h=From:To:CC:Subject:Date:References:In-Reply-To; b=QXliQPfeT7KVacS9OpAq2TBcFrA0fi5kb1J+az3tCshiDgKjz693qVcbJA8mI0jJQ ALLH3syBEVc1QX+d3KiM9TuxzulIqW6I08ipMYc4lUJEWLstb+EyiS7w6nwEzeUx+T X5+y4pUfzK+yvwhQyxaRrTnFA6uB/JtWFLyrr/wc= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 212IFS3E108827 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Wed, 2 Feb 2022 12:15:28 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Wed, 2 Feb 2022 12:15:28 -0600 Received: from DFLE100.ent.ti.com ([fe80::f19c:5926:3526:1b30]) by DFLE100.ent.ti.com ([fe80::f19c:5926:3526:1b30%17]) with mapi id 15.01.2308.014; Wed, 2 Feb 2022 12:15:28 -0600 From: "Nagalla, Hari" To: "u-boot@lists.denx.de" CC: "Menon, Nishanth" Subject: RE: [PATCH 0/5] Add ESM driver support for AM64x R5 Thread-Topic: [PATCH 0/5] Add ESM driver support for AM64x R5 Thread-Index: AQHYGF1guN077TMYQkmIMjLd4PyPoKyAkM4w Date: Wed, 2 Feb 2022 18:15:27 +0000 Message-ID: <5cd5a24545cf4c2f9f81cee224097ed2@ti.com> References: <20220202171023.6687-1-hnagalla@ti.com> In-Reply-To: <20220202171023.6687-1-hnagalla@ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.249.43.35] x-exclaimer-md-config: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Sorry.. The patches are being re-submitted after rebasing. Thanks -----Original Message----- From: U-Boot On Behalf Of Nagalla, Hari Sent: Wednesday, February 2, 2022 11:10 AM To: u-boot@lists.denx.de Cc: Menon, Nishanth Subject: [PATCH 0/5] Add ESM driver support for AM64x R5 AM64x devices have a main ESM and a MCU ESM. The ESM driver enables routing= of the error events from various sources to different processors or to res= et hardware logic. Only the MCU ESM's high output can trigger reset logic. = The main RTI0 WWDT output can be routed to the MCU highoutput to trigger re= set through the main ESM. For this reset to occur CTRLMMR_MCU_RST_CTRL:MCU_= ESM_ERROR_RESET_EN_Z is set to '0'. AM64x Technical Reference Manual - https://www.ti.com/lit/pdf/spruim2 Hari Nagalla (5): misc: k3_esm: Add functionality to set and route error events within K3SoC arm: dts: k3-am64: Add support for ESM device nodes arch: arm: mach-k3: am642_init: Probe ESM nodes configs: am64x_evm_r5_defconfig: Add support for ESM driver configs: am64x_hs_evm_r5_defconfig: Add support for ESM driver arch/arm/dts/k3-am64.dtsi | 1 + arch/arm/dts/k3-am642-r5-evm.dts | 19 +++++++++++ arch/arm/dts/k3-am642-r5-sk.dts | 19 +++++++++++ arch/arm/mach-k3/am642_init.c | 37 +++++++++++++++++++++ configs/am64x_evm_r5_defconfig | 1 + configs/am64x_hs_evm_r5_defconfig | 1 + drivers/misc/k3_esm.c | 53 +++++++++++++++++++++++++++++-- 7 files changed, 128 insertions(+), 3 deletions(-) -- 2.17.1