[U-Boot] [PATCH 2/2] mips: xilfpga: Add device tree files

[Daniel Schwierzeck <daniel.schwierzeck@gmail.com>]

Am 27.07.2016 um 12:51 schrieb Zubair Lutfullah Kakakhel:
> Mostly the same as the Kernel upstream device tree file except for
> 
> - alias for the serial console node
> - ethernet node as the ethernet stuff isn't upstream on kernel.org yet
> - uart clock-frequency passed directly in the node
> 
> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
> Reviewed-by: Paul Burton <paul.burton@imgtec.com>

actually this should be the first patch in this series because you can't
build the xilfpga board without these device tree files which would
break bisectability.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

> ---
>  arch/mips/dts/Makefile        |  1 +
>  arch/mips/dts/microAptiv.dtsi | 21 +++++++++++++++
>  arch/mips/dts/nexys4ddr.dts   | 62 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 84 insertions(+)
>  create mode 100644 arch/mips/dts/microAptiv.dtsi
>  create mode 100644 arch/mips/dts/nexys4ddr.dts
> 
> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> index 2f04d73..5f311d4 100644
> --- a/arch/mips/dts/Makefile
> +++ b/arch/mips/dts/Makefile
> @@ -6,6 +6,7 @@ dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
>  dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
>  dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
>  dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
> +dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb
>  dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
>  
>  targets += $(dtb-y)
> diff --git a/arch/mips/dts/microAptiv.dtsi b/arch/mips/dts/microAptiv.dtsi
> new file mode 100644
> index 0000000..81d518e
> --- /dev/null
> +++ b/arch/mips/dts/microAptiv.dtsi
> @@ -0,0 +1,21 @@
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	compatible = "img,xilfpga";
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "mips,m14Kc";
> +			clocks	= <&ext>;
> +			reg = <0>;
> +		};
> +	};
> +
> +	ext: ext {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +	};
> +};
> diff --git a/arch/mips/dts/nexys4ddr.dts b/arch/mips/dts/nexys4ddr.dts
> new file mode 100644
> index 0000000..e254ab1
> --- /dev/null
> +++ b/arch/mips/dts/nexys4ddr.dts
> @@ -0,0 +1,62 @@
> +/dts-v1/;
> +
> +#include "microAptiv.dtsi"
> +
> +/ {
> +	compatible = "digilent,nexys4ddr";
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x0 0x08000000>;
> +	};
> +
> +	cpuintc: interrupt-controller at 0 {
> +		#address-cells = <0>;
> +		#interrupt-cells = <1>;
> +		interrupt-controller;
> +		compatible = "mti,cpu-interrupt-controller";
> +	};
> +
> +	aliases {
> +		console = &axi_uart16550;
> +	};
> +
> +	axi_ethernetlite: ethernet at 10e00000 {
> +		compatible = "xlnx,xps-ethernetlite-1.00.a";
> +		device_type = "network";
> +		local-mac-address = [08 86 4C 0D F7 09];
> +		phy-handle = <&phy0>;
> +		reg = <0x10e00000 0x10000>;
> +		xlnx,duplex = <0x1>;
> +		xlnx,include-global-buffers = <0x1>;
> +		xlnx,include-internal-loopback = <0x0>;
> +		xlnx,include-mdio = <0x1>;
> +		xlnx,instance = "axi_ethernetlite_inst";
> +		xlnx,rx-ping-pong = <0x1>;
> +		xlnx,s-axi-id-width = <0x1>;
> +		xlnx,tx-ping-pong = <0x1>;
> +		xlnx,use-internal = <0x0>;
> +		mdio {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			phy0: phy at 1 {
> +				compatible = <0x0007c0f0 0xfffffff0>;
> +				device_type = "ethernet-phy";
> +				reg = <1>;
> +			} ;
> +		} ;
> +        } ;
> +
> +
> +	axi_uart16550: serial at 10400000 {
> +		compatible = "ns16550a";
> +		reg = <0x10400000 0x10000>;
> +
> +		reg-shift = <2>;
> +		reg-offset = <0x1000>;
> +
> +		clock-frequency = <50000000>;
> +
> +	};
> +};
> +
> 

-- 
- Daniel

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