[U-Boot] [PATCH 57/93] arm: Remove kp_imx6q_tpc board

Simon Glass
2018-11-19T15:53:37Z

This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

arch/arm/mach-imx/mx6/Kconfig | 1 -
board/k+p/kp_imx6q_tpc/Kconfig | 12 -
board/k+p/kp_imx6q_tpc/MAINTAINERS | 6 -
board/k+p/kp_imx6q_tpc/Makefile | 9 -
board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c | 301 -------------------
board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c | 337 ----------------------
configs/kp_imx6q_tpc_defconfig | 44 ---
include/configs/kp_imx6q_tpc.h | 134 ---------
8 files changed, 844 deletions(-)
delete mode 100644 board/k+p/kp_imx6q_tpc/Kconfig
delete mode 100644 board/k+p/kp_imx6q_tpc/MAINTAINERS
delete mode 100644 board/k+p/kp_imx6q_tpc/Makefile
delete mode 100644 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
delete mode 100644 board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
delete mode 100644 configs/kp_imx6q_tpc_defconfig
delete mode 100644 include/configs/kp_imx6q_tpc.h

diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index ca7e60ee1cb..71e57690d6e 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -550,7 +550,6 @@ source "board/solidrun/mx6cuboxi/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/toradex/colibri-imx6ull/Kconfig"
-source "board/k+p/kp_imx6q_tpc/Kconfig"
source "board/udoo/Kconfig"
source "board/warp/Kconfig"

diff --git a/board/k+p/kp_imx6q_tpc/Kconfig b/board/k+p/kp_imx6q_tpc/Kconfig
deleted file mode 100644
index 62e34978ecd..00000000000
--- a/board/k+p/kp_imx6q_tpc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_KP_IMX6Q_TPC
-
-config SYS_BOARD
- default "kp_imx6q_tpc"
-
-config SYS_VENDOR
- default "k+p"
-
-config SYS_CONFIG_NAME
- default "kp_imx6q_tpc"
-
-endif
diff --git a/board/k+p/kp_imx6q_tpc/MAINTAINERS b/board/k+p/kp_imx6q_tpc/MAINTAINERS
deleted file mode 100644
index 6c4c8dd28e3..00000000000
--- a/board/k+p/kp_imx6q_tpc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KP_IMX6Q_TPC BOARD
-M: Lukasz Majewski <lukma@denx.de>
-S: Maintained
-F: board/k+p/kp_imx6q_tpc/
-F: include/configs/kp_imx6q_tpc.h
-F: configs/kp_imx6q_tpc_defconfig
diff --git a/board/k+p/kp_imx6q_tpc/Makefile b/board/k+p/kp_imx6q_tpc/Makefile
deleted file mode 100644
index 6551b2bfa2d..00000000000
--- a/board/k+p/kp_imx6q_tpc/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
-
-ifdef CONFIG_SPL_BUILD
-obj-y := kp_imx6q_tpc_spl.o
-else
-obj-y := kp_imx6q_tpc.o
-endif
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
deleted file mode 100644
index ace986fa050..00000000000
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
+++ /dev/null
@@ -1,301 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * K+P iMX6Q KP_IMX6Q_TPC board configuration
- *
- * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <errno.h>
-#include <fsl_esdhc.h>
-#include <fuse.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define ENET_PAD_CTRL \
- (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL \
- (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC,
- .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
- .gp = IMX_GPIO_NR(5, 27)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC,
- .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
- .gp = IMX_GPIO_NR(5, 26)
- }
-};
-
-static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
- return 0;
-}
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
- return 1;
-}
-
-#ifdef CONFIG_FEC_MXC
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- /* AR8031 PHY Reset */
- IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void eth_phy_reset(void)
-{
- /* Reset AR8031 PHY */
- gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
- mdelay(10);
- gpio_set_value(IMX_GPIO_NR(1, 25), 1);
- udelay(100);
-}
-
-static int setup_fec_clock(void)
-{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- /* set gpr1[21] to select anatop clock */
- clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
-
- return enable_fec_anatop_clock(0, ENET_50MHZ);
-}
-
-int board_eth_init(bd_t *bis)
-{
- SETUP_IOMUX_PADS(enet_pads);
- setup_fec_clock();
- eth_phy_reset();
-
- return cpu_eth_init(bis);
-}
-
-static int ar8031_phy_fixup(struct phy_device *phydev)
-{
- unsigned short val;
-
- /* To enable AR8031 output a 125MHz clk from CLK_25M */
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
- phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
- val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
- val |= 0x0100;
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- ar8031_phy_fixup(phydev);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_FSL_ESDHC
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-static struct fsl_esdhc_cfg usdhc_cfg[] = {
- { USDHC2_BASE_ADDR },
- { USDHC4_BASE_ADDR },
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- return !gpio_get_value(USDHC2_CD_GPIO);
- case USDHC4_BASE_ADDR:
- return 1; /* eMMC/uSDHC4 is always present */
- }
-
- return 0;
-}
-
-int board_mmc_init(bd_t *bis)
-{
- int i, ret;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 micro SD
- * mmc2 eMMC
- */
- gpio_direction_input(USDHC2_CD_GPIO);
-
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_EHCI_MX6
-static void setup_usb(void)
-{
- /*
- * Set daisy chain for otg_pin_id on MX6Q.
- * For MX6DL, this bit is reserved.
- */
- imx_iomux_set_gpr_register(1, 13, 1, 0);
-}
-
-int board_usb_phy_mode(int port)
-{
- if (port == 1)
- return USB_INIT_HOST;
- else
- return USB_INIT_DEVICE;
-}
-
-int board_ehci_power(int port, int on)
-{
- switch (port) {
- case 0:
- break;
- case 1:
- gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
- break;
- default:
- printf("MXC USB port %d not yet supported\n", port);
- return -EINVAL;
- }
-
- return 0;
-}
-#endif
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_USB_EHCI_MX6
- setup_usb();
-#endif
-
- return 0;
-}
-
-int board_init(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- /* Enable eim_slow clocks */
- setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
-
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1);
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
- /* 4 bit bus width */
- {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
- /* 8 bit bus width */
- {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
- {NULL, 0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
- add_board_boot_modes(board_boot_modes);
-#endif
-
- env_set("boardname", "kp-tpc");
- env_set("boardsoc", "imx6q");
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
- return 0;
-}
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
deleted file mode 100644
index d89e1120a57..00000000000
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
+++ /dev/null
@@ -1,337 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * K+P iMX6Q KP_IMX6Q_TPC board configuration
- *
- * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-ddr.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/io.h>
-#include <errno.h>
-#include <fuse.h>
-#include <fsl_esdhc.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <spl.h>
-
-#define UART_PAD_CTRL \
- (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL \
- (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0x0F0000C3, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-/* onboard microSD */
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-/* eMMC */
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
-/* SD */
-static void setup_iomux_sd(void)
-{
- SETUP_IOMUX_PADS(usdhc2_pads);
- SETUP_IOMUX_PADS(usdhc4_pads);
-}
-
-/* UART */
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static void setup_iomux_uart(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
-}
-
-/* USB */
-static iomux_v3_cfg_t const usb_pads[] = {
- IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static void setup_iomux_usb(void)
-{
- SETUP_IOMUX_PADS(usb_pads);
-}
-
-/* DDR3 */
-static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_sdclk_0 = 0x00000030,
- .dram_sdclk_1 = 0x00000030,
- .dram_cas = 0x00000030,
- .dram_ras = 0x00000030,
- .dram_reset = 0x00000030,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00000030,
- .dram_sdodt1 = 0x00000030,
-
- .dram_sdqs0 = 0x00000018,
- .dram_sdqs1 = 0x00000018,
- .dram_sdqs2 = 0x00000018,
- .dram_sdqs3 = 0x00000018,
- .dram_sdqs4 = 0x00000018,
- .dram_sdqs5 = 0x00000018,
- .dram_sdqs6 = 0x00000018,
- .dram_sdqs7 = 0x00000018,
-
- .dram_dqm0 = 0x00000018,
- .dram_dqm1 = 0x00000018,
- .dram_dqm2 = 0x00000018,
- .dram_dqm3 = 0x00000018,
- .dram_dqm4 = 0x00000018,
- .dram_dqm5 = 0x00000018,
- .dram_dqm6 = 0x00000018,
- .dram_dqm7 = 0x00000018,
-};
-
-static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000018,
- .grp_b1ds = 0x00000018,
- .grp_b2ds = 0x00000018,
- .grp_b3ds = 0x00000018,
- .grp_b4ds = 0x00000018,
- .grp_b5ds = 0x00000018,
- .grp_b6ds = 0x00000018,
- .grp_b7ds = 0x00000018,
-};
-
-static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
- .p0_mpwldectrl0 = 0x001F001F,
- .p0_mpwldectrl1 = 0x001F001F,
- .p1_mpwldectrl0 = 0x001F001F,
- .p1_mpwldectrl1 = 0x001F001F,
- .p0_mpdgctrl0 = 0x43270338,
- .p0_mpdgctrl1 = 0x03200314,
- .p1_mpdgctrl0 = 0x431A032F,
- .p1_mpdgctrl1 = 0x03200263,
- .p0_mprddlctl = 0x4B434748,
- .p1_mprddlctl = 0x4445404C,
- .p0_mpwrdlctl = 0x38444542,
- .p1_mpwrdlctl = 0x4935493A,
-};
-
-/* MT41K256M16 (4Gb density) */
-static const struct mx6_ddr3_cfg mt41k256m16 = {
- .mem_speed = 1600,
- .density = 4,
- .width = 16,
- .banks = 8,
- .rowaddr = 15,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
-
-#ifdef CONFIG_MX6_DDRCAL
-static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
-{
- struct mx6_mmdc_calibration calibration = {0};
-
- mmdc_read_calibration(sysinfo, &calibration);
-
- debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
- debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
- debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
- debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
- debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
- debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
- debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
- debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
- debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
- debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
- debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
- debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
-}
-
-static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
-{
- int ret;
-
- /* Perform DDR DRAM calibration */
- udelay(100);
- ret = mmdc_do_write_level_calibration(sysinfo);
- if (ret) {
- printf("DDR: Write level calibration error [%d]\n", ret);
- return;
- }
-
- ret = mmdc_do_dqs_calibration(sysinfo);
- if (ret) {
- printf("DDR: DQS calibration error [%d]\n", ret);
- return;
- }
-
- spl_dram_print_cal(sysinfo);
-}
-#endif /* CONFIG_MX6_DDRCAL */
-
-static void spl_dram_init(void)
-{
- struct mx6_ddr_sysinfo sysinfo = {
- /* width of data bus:0=16,1=32,2=64 */
- .dsize = 2,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 32Gb per CS */
- /* single chip select */
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
- .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- .pd_fast_exit = 1, /* enable precharge power-down fast exit */
- .ddr_type = DDR_TYPE_DDR3,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
- };
-
- mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k256m16);
-
-#ifdef CONFIG_MX6_DDRCAL
- spl_dram_perform_cal(&sysinfo);
-#endif
-}
-
-struct fsl_esdhc_cfg usdhc_cfg[] = {
- {USDHC2_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC4_BASE_ADDR:
- ret = 1; /* eMMC/uSDHC4 is always present */
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bd)
-{
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned int reg = readl(&psrc->sbmr1) >> 11;
- /*
- * Upon reading BOOT_CFG register the following map is done:
- * Bit 11 and 12 of BOOT_CFG register can determine the current
- * mmc port
- * 0x1 SD1
- * 0x3 SD4
- */
-
- switch (reg & 0x3) {
- case 0x1:
- SETUP_IOMUX_PADS(usdhc2_pads);
- usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- case 0x3:
- SETUP_IOMUX_PADS(usdhc4_pads);
- usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- }
-
- return fsl_esdhc_initialize(bd, &usdhc_cfg[0]);
-}
-
-void board_init_f(ulong dummy)
-{
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- ccgr_init();
- gpr_init();
-
- /* setup GP timer */
- timer_init();
-
- setup_iomux_sd();
- setup_iomux_uart();
- setup_iomux_usb();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
deleted file mode 100644
index 5ebbe1dc7c6..00000000000
--- a/configs/kp_imx6q_tpc_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_MX6_DDRCAL=y
-CONFIG_TARGET_KP_IMX6Q_TPC=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=3
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SPL_RAW_IMAGE_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_STOP_STR="."
-# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT4_WRITE=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_IMX_THERMAL=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_IMX_WATCHDOG=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
deleted file mode 100644
index b6b27ee1d5e..00000000000
--- a/include/configs/kp_imx6q_tpc.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * K+P iMX6Q KP_IMX6Q_TPC board configuration
- *
- * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
- */
-
-#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_
-#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_
-
-#include <asm/arch/imx-regs.h>
-
-#include "mx6_common.h"
-
-/* SPL */
-#include "imx6_spl.h" /* common IMX6 SPL configuration */
-
-/* Miscellaneous configurable options */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
-
-/* FEC ethernet */
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* Fuses */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-#endif
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
-
-/* UART */
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* USB Configs */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
-#endif
-
-/* Watchdog */
-#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=ttymxc0,115200\0" \
- "fdt_addr=0x18000000\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "kernel_addr_r=0x10008000\0" \
- "fdt_addr_r=0x13000000\0" \
- "ramdisk_addr_r=0x18000000\0" \
- "scriptaddr=0x14000000\0" \
- "kernel_file=fitImage\0"\
- "rdinit=/sbin/init\0" \
- "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
- "fit_config=mx6q_tpc70_conf\0" \
- "upd_image=st.4k\0" \
- "updargs=setenv bootargs console=${console} ${smp}"\
- "rdinit=${rdinit} ${debug} ${displayargs}\0" \
- "loadusb=usb start; " \
- "fatload usb 0 ${loadaddr} ${upd_image}\0" \
- "usbupd=echo Booting update from usb ...; " \
- "setenv bootargs; " \
- "run updargs; " \
- "run loadusb; " \
- "bootm ${loadaddr}#${fit_config}\0" \
- BOOTENV
-
-#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd"
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1) \
- func(USB, usb, 0) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-#endif
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Environment */
-#define CONFIG_ENV_SIZE (SZ_8K)
-#define CONFIG_ENV_OFFSET 0x100000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-
-#endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */
--
2.19.1.1215.g8438c0b245-goog