[U-Boot] [PATCH 90/93] arm: Remove dra7xx_evm and dra7xx_hs_evm boards

Simon Glass
2018-11-19T15:54:10Z

These board have not been converted to CONFIG_DM_BLK by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

arch/arm/mach-omap2/omap5/Kconfig | 1 -
board/ti/dra7xx/Kconfig | 14 -
board/ti/dra7xx/MAINTAINERS | 7 -
board/ti/dra7xx/Makefile | 6 -
board/ti/dra7xx/README | 26 -
board/ti/dra7xx/evm.c | 1202 -----------------------------
board/ti/dra7xx/mux_data.h | 1121 ---------------------------
configs/dra7xx_evm_defconfig | 102 ---
configs/dra7xx_hs_evm_defconfig | 101 ---
include/configs/dra7xx_evm.h | 165 ----
10 files changed, 2745 deletions(-)
delete mode 100644 board/ti/dra7xx/Kconfig
delete mode 100644 board/ti/dra7xx/MAINTAINERS
delete mode 100644 board/ti/dra7xx/Makefile
delete mode 100644 board/ti/dra7xx/README
delete mode 100644 board/ti/dra7xx/evm.c
delete mode 100644 board/ti/dra7xx/mux_data.h
delete mode 100644 configs/dra7xx_evm_defconfig
delete mode 100644 configs/dra7xx_hs_evm_defconfig
delete mode 100644 include/configs/dra7xx_evm.h

diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
index f083a4a385c..fba25e8b180 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -163,7 +163,6 @@ endif
source "board/compulab/cl-som-am57x/Kconfig"
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
-source "board/ti/dra7xx/Kconfig"
source "board/ti/am57xx/Kconfig"

endif
diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig
deleted file mode 100644
index f6a8e07c5b2..00000000000
--- a/board/ti/dra7xx/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-if TARGET_DRA7XX_EVM
-
-config SYS_BOARD
- default "dra7xx"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "dra7xx_evm"
-
-source "board/ti/common/Kconfig"
-
-endif
diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS
deleted file mode 100644
index 46b6e82b36e..00000000000
--- a/board/ti/dra7xx/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-DRA7XX BOARD
-M: Lokesh Vutla <lokeshvutla@ti.com>
-S: Maintained
-F: board/ti/dra7xx/
-F: include/configs/dra7xx_evm.h
-F: configs/dra7xx_evm_defconfig
-F: configs/dra7xx_hs_evm_defconfig
diff --git a/board/ti/dra7xx/Makefile b/board/ti/dra7xx/Makefile
deleted file mode 100644
index 8d0ca56aded..00000000000
--- a/board/ti/dra7xx/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2013
-# Texas Instruments, <www.ti.com>
-
-obj-y := evm.o
diff --git a/board/ti/dra7xx/README b/board/ti/dra7xx/README
deleted file mode 100644
index 533da01a347..00000000000
--- a/board/ti/dra7xx/README
+++ /dev/null
@@ -1,26 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'dra7xx_evm' build and some
-related uses.
-
-eMMC boot partition use
-=======================
-
-It is possible, depending on SYSBOOT configuration to boot from the eMMC
-boot partitions using (name depending on documentation referenced)
-Alternative Boot operation mode or Boot Sequence Option 1/2. In this
-example we load MLO and u-boot.img from the build into DDR and then use
-'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
-set boot0 as the boot device.
-U-Boot # setenv autoload no
-U-Boot # usb start
-U-Boot # dhcp
-U-Boot # mmc dev 1 1
-U-Boot # tftp ${loadaddr} dra7xx/MLO
-U-Boot # mmc write ${loadaddr} 0 100
-U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
-U-Boot # mmc write ${loadaddr} 300 400
-U-Boot # mmc bootbus 1 2 0 2
-U-Boot # mmc partconf 1 1 1 0
-U-Boot # mmc rst-function 1 1
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
deleted file mode 100644
index bbe54450aee..00000000000
--- a/board/ti/dra7xx/evm.c
+++ /dev/null
@@ -1,1202 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Lokesh Vutla <lokeshvutla@ti.com>
- *
- * Based on previous work by:
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- */
-#include <common.h>
-#include <palmas.h>
-#include <sata.h>
-#include <linux/string.h>
-#include <asm/gpio.h>
-#include <usb.h>
-#include <linux/usb/gadget.h>
-#include <asm/omap_common.h>
-#include <asm/omap_sec_common.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/dra7xx_iodelay.h>
-#include <asm/emif.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sata.h>
-#include <environment.h>
-#include <dwc3-uboot.h>
-#include <dwc3-omap-uboot.h>
-#include <ti-usb-phy-uboot.h>
-#include <miiphy.h>
-
-#include "mux_data.h"
-#include "../common/board_detect.h"
-
-#define board_is_dra76x_evm() board_ti_is("DRA76/7x")
-#define board_is_dra74x_evm() board_ti_is("5777xCPU")
-#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
-#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
-#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
- (strncmp("H", board_ti_get_rev(), 1) <= 0))
-#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
- (strncmp("C", board_ti_get_rev(), 1) <= 0))
-#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
- board_ti_get_emif2_size()
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-#include <cpsw.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GPIO 7_11 */
-#define GPIO_DDR_VTT_EN 203
-
-#define SYSINFO_BOARD_NAME_MAX_LEN 37
-
-const struct omap_sysinfo sysinfo = {
- "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
-};
-
-static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
- .sdram_config_init = 0x61851ab2,
- .sdram_config = 0x61851ab2,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x427F88A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400B,
- .emif_ddr_phy_ctlr_1 = 0x0E24400B,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
- .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
- .sdram_config_init = 0x61851B32,
- .sdram_config = 0x61851B32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x427F88A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400B,
- .emif_ddr_phy_ctlr_1 = 0x0E24400B,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
- .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
- .sdram_config_init = 0x61862B32,
- .sdram_config = 0x61862B32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x0000514C,
- .ref_ctrl_final = 0x0000144A,
- .sdram_tim1 = 0xD113781C,
- .sdram_tim2 = 0x30717FE3,
- .sdram_tim3 = 0x409F86A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400D,
- .emif_ddr_phy_ctlr_1 = 0x0E24400D,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
- .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
- .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
- .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
- .sdram_config_init = 0x61862BB2,
- .sdram_config = 0x61862BB2,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x0000514D,
- .ref_ctrl_final = 0x0000144A,
- .sdram_tim1 = 0xD1137824,
- .sdram_tim2 = 0x30B37FE3,
- .sdram_tim3 = 0x409F8AD8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0824400E,
- .emif_ddr_phy_ctlr_1 = 0x0E24400E,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
- .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
- .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
- .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
- .sdram_config_init = 0x61851ab2,
- .sdram_config = 0x61851ab2,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x30BF7FDA,
- .sdram_tim3 = 0x427F8BA8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400B,
- .emif_ddr_phy_ctlr_1 = 0x0E24400B,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
- .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
- .sdram_config_init = 0x61851B32,
- .sdram_config = 0x61851B32,
- .sdram_config2 = 0x08000000,
- .ref_ctrl = 0x000040F1,
- .ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x427F88A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400B,
- .emif_ddr_phy_ctlr_1 = 0x0E24400B,
- .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
- .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
- .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
- .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
- .sdram_config_init = 0x61862B32,
- .sdram_config = 0x61862B32,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x0000514C,
- .ref_ctrl_final = 0x0000144A,
- .sdram_tim1 = 0xD113783C,
- .sdram_tim2 = 0x30B47FE3,
- .sdram_tim3 = 0x409F8AD8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0824400D,
- .emif_ddr_phy_ctlr_1 = 0x0E24400D,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
- .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
- .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
- .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
- .sdram_config_init = 0x61862B32,
- .sdram_config = 0x61862B32,
- .sdram_config2 = 0x00000000,
- .ref_ctrl = 0x0000514C,
- .ref_ctrl_final = 0x0000144A,
- .sdram_tim1 = 0xD113781C,
- .sdram_tim2 = 0x30B47FE3,
- .sdram_tim3 = 0x409F8AD8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x5007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0824400D,
- .emif_ddr_phy_ctlr_1 = 0x0E24400D,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
- .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
- .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
- .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
-};
-
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
-{
- u64 ram_size;
-
- ram_size = board_ti_get_emif_size();
-
- switch (omap_revision()) {
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- case DRA752_ES2_0:
- switch (emif_nr) {
- case 1:
- if (ram_size > CONFIG_MAX_MEM_MAPPED)
- *regs = &emif1_ddr3_532_mhz_1cs_2G;
- else
- *regs = &emif1_ddr3_532_mhz_1cs;
- break;
- case 2:
- if (ram_size > CONFIG_MAX_MEM_MAPPED)
- *regs = &emif2_ddr3_532_mhz_1cs_2G;
- else
- *regs = &emif2_ddr3_532_mhz_1cs;
- break;
- }
- break;
- case DRA762_ABZ_ES1_0:
- case DRA762_ACD_ES1_0:
- case DRA762_ES1_0:
- if (emif_nr == 1)
- *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
- else
- *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
- break;
- case DRA722_ES1_0:
- case DRA722_ES2_0:
- case DRA722_ES2_1:
- if (ram_size < CONFIG_MAX_MEM_MAPPED)
- *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
- else
- *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
- break;
- default:
- *regs = &emif1_ddr3_532_mhz_1cs;
- }
-}
-
-static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x80640300,
- .dmm_lisa_map_2 = 0xC0500220,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x80600100,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x80740300,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-/*
- * DRA722 EVM EMIF1 2GB CONFIGURATION
- * EMIF1 4 devices of 512Mb x 8 Micron
- */
-const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
- .dmm_lisa_map_0 = 0x0,
- .dmm_lisa_map_1 = 0x0,
- .dmm_lisa_map_2 = 0x80700100,
- .dmm_lisa_map_3 = 0xFF020100,
- .is_ma_present = 0x1
-};
-
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
-{
- u64 ram_size;
-
- ram_size = board_ti_get_emif_size();
-
- switch (omap_revision()) {
- case DRA762_ABZ_ES1_0:
- case DRA762_ACD_ES1_0:
- case DRA762_ES1_0:
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- case DRA752_ES2_0:
- if (ram_size > CONFIG_MAX_MEM_MAPPED)
- *dmm_lisa_regs = &lisa_map_dra7_2GB;
- else
- *dmm_lisa_regs = &lisa_map_dra7_1536MB;
- break;
- case DRA722_ES1_0:
- case DRA722_ES2_0:
- case DRA722_ES2_1:
- default:
- if (ram_size < CONFIG_MAX_MEM_MAPPED)
- *dmm_lisa_regs = &lisa_map_2G_x_2;
- else
- *dmm_lisa_regs = &lisa_map_2G_x_4;
- break;
- }
-}
-
-struct vcores_data dra752_volts = {
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS659038_REG_ADDR_SMPS12,
- .mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS659038_REG_ADDR_SMPS45,
- .eve.pmic = &tps659038,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
- .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
- .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS659038_REG_ADDR_SMPS6,
- .gpu.pmic = &tps659038,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS659038_REG_ADDR_SMPS7,
- .core.pmic = &tps659038,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS659038_REG_ADDR_SMPS8,
- .iva.pmic = &tps659038,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra76x_volts = {
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = LP87565_REG_ADDR_BUCK01,
- .mpu.pmic = &lp87565,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS65917_REG_ADDR_SMPS1,
- .eve.pmic = &tps659038,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
- .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
- .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = LP87565_REG_ADDR_BUCK23,
- .gpu.pmic = &lp87565,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS65917_REG_ADDR_SMPS3,
- .core.pmic = &tps659038,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS65917_REG_ADDR_SMPS4,
- .iva.pmic = &tps659038,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra722_volts = {
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = TPS65917_REG_ADDR_SMPS1,
- .mpu.pmic = &tps659038,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = TPS65917_REG_ADDR_SMPS2,
- .core.pmic = &tps659038,
-
- /*
- * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
- * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
- */
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
- .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
- .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = TPS65917_REG_ADDR_SMPS3,
- .gpu.pmic = &tps659038,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = TPS65917_REG_ADDR_SMPS3,
- .eve.pmic = &tps659038,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = TPS65917_REG_ADDR_SMPS3,
- .iva.pmic = &tps659038,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-struct vcores_data dra718_volts = {
- /*
- * In the case of dra71x GPU MPU and CORE
- * are all powered up by BUCK0 of LP873X PMIC
- */
- .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
- .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
- .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .mpu.addr = LP873X_REG_ADDR_BUCK0,
- .mpu.pmic = &lp8733,
- .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
-
- .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
- .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
- .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .core.addr = LP873X_REG_ADDR_BUCK0,
- .core.pmic = &lp8733,
-
- .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
- .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
- .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .gpu.addr = LP873X_REG_ADDR_BUCK0,
- .gpu.pmic = &lp8733,
- .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
-
- /*
- * The DSPEVE and IVA rails are grouped on DRA71x-evm
- * and are powered by BUCK1 of LP873X PMIC
- */
- .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
- .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
- .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
- .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
- .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .eve.addr = LP873X_REG_ADDR_BUCK1,
- .eve.pmic = &lp8733,
- .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
-
- .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
- .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
- .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
- .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
- .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
- .iva.addr = LP873X_REG_ADDR_BUCK1,
- .iva.pmic = &lp8733,
- .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
-};
-
-int get_voltrail_opp(int rail_offset)
-{
- int opp;
-
- switch (rail_offset) {
- case VOLT_MPU:
- opp = DRA7_MPU_OPP;
- /* DRA71x supports only OPP_NOM for MPU */
- if (board_is_dra71x_evm())
- opp = OPP_NOM;
- break;
- case VOLT_CORE:
- opp = DRA7_CORE_OPP;
- /* DRA71x supports only OPP_NOM for CORE */
- if (board_is_dra71x_evm())
- opp = OPP_NOM;
- break;
- case VOLT_GPU:
- opp = DRA7_GPU_OPP;
- /* DRA71x supports only OPP_NOM for GPU */
- if (board_is_dra71x_evm())
- opp = OPP_NOM;
- break;
- case VOLT_EVE:
- opp = DRA7_DSPEVE_OPP;
- /*
- * DRA71x does not support OPP_OD for EVE.
- * If OPP_OD is selected by menuconfig, fallback
- * to OPP_NOM.
- */
- if (board_is_dra71x_evm() && opp == OPP_OD)
- opp = OPP_NOM;
- break;
- case VOLT_IVA:
- opp = DRA7_IVA_OPP;
- /*
- * DRA71x does not support OPP_OD for IVA.
- * If OPP_OD is selected by menuconfig, fallback
- * to OPP_NOM.
- */
- if (board_is_dra71x_evm() && opp == OPP_OD)
- opp = OPP_NOM;
- break;
- default:
- opp = OPP_NOM;
- }
-
- return opp;
-}
-
-/**
- * @brief board_init
- *
- * @return 0
- */
-int board_init(void)
-{
- gpmc_init();
- gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- u64 ram_size;
-
- ram_size = board_ti_get_emif_size();
-
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = get_effective_memsize();
- if (ram_size > CONFIG_MAX_MEM_MAPPED) {
- gd->bd->bi_dram[1].start = 0x200000000;
- gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
- }
-
- return 0;
-}
-
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- char *name = "unknown";
-
- if (is_dra72x()) {
- if (board_is_dra72x_revc_or_later())
- name = "dra72x-revc";
- else if (board_is_dra71x_evm())
- name = "dra71x";
- else
- name = "dra72x";
- } else if (is_dra76x_abz()) {
- name = "dra76x_abz";
- } else if (is_dra76x_acd()) {
- name = "dra76x_acd";
- } else {
- name = "dra7xx";
- }
-
- set_board_info_env(name);
-
- /*
- * Default FIT boot on HS devices. Non FIT images are not allowed
- * on HS devices.
- */
- if (get_device_type() == HS_DEVICE)
- env_set("boot_fit", "1");
-
- omap_die_id_serial();
- omap_set_fastboot_vars();
-
- /*
- * Hook the LDO1 regulator to EN pin. This applies only to LP8733
- * Rest all regulators are hooked to EN Pin at reset.
- */
- if (board_is_dra71x_evm())
- palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-void do_board_detect(void)
-{
- int rc;
-
- rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
- CONFIG_EEPROM_CHIP_ADDRESS);
- if (rc)
- printf("ti_i2c_eeprom_init failed %d\n", rc);
-}
-
-#else
-
-void do_board_detect(void)
-{
- char *bname = NULL;
- int rc;
-
- rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
- CONFIG_EEPROM_CHIP_ADDRESS);
- if (rc)
- printf("ti_i2c_eeprom_init failed %d\n", rc);
-
- if (board_is_dra74x_evm()) {
- bname = "DRA74x EVM";
- } else if (board_is_dra72x_evm()) {
- bname = "DRA72x EVM";
- } else if (board_is_dra71x_evm()) {
- bname = "DRA71x EVM";
- } else if (board_is_dra76x_evm()) {
- bname = "DRA76x EVM";
- } else {
- /* If EEPROM is not populated */
- if (is_dra72x())
- bname = "DRA72x EVM";
- else
- bname = "DRA74x EVM";
- }
-
- if (bname)
- snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
- "Board: %s REV %s\n", bname, board_ti_get_rev());
-}
-#endif /* CONFIG_SPL_BUILD */
-
-void vcores_init(void)
-{
- if (board_is_dra74x_evm()) {
- *omap_vcores = &dra752_volts;
- } else if (board_is_dra72x_evm()) {
- *omap_vcores = &dra722_volts;
- } else if (board_is_dra71x_evm()) {
- *omap_vcores = &dra718_volts;
- } else if (board_is_dra76x_evm()) {
- *omap_vcores = &dra76x_volts;
- } else {
- /* If EEPROM is not populated */
- if (is_dra72x())
- *omap_vcores = &dra722_volts;
- else
- *omap_vcores = &dra752_volts;
- }
-}
-
-void set_muxconf_regs(void)
-{
- do_set_mux32((*ctrl)->control_padconf_core_base,
- early_padconf, ARRAY_SIZE(early_padconf));
-}
-
-#ifdef CONFIG_IODELAY_RECALIBRATION
-void recalibrate_iodelay(void)
-{
- struct pad_conf_entry const *pads, *delta_pads = NULL;
- struct iodelay_cfg_entry const *iodelay;
- int npads, niodelays, delta_npads = 0;
- int ret;
-
- switch (omap_revision()) {
- case DRA722_ES1_0:
- case DRA722_ES2_0:
- case DRA722_ES2_1:
- pads = dra72x_core_padconf_array_common;
- npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
- if (board_is_dra71x_evm()) {
- pads = dra71x_core_padconf_array;
- npads = ARRAY_SIZE(dra71x_core_padconf_array);
- iodelay = dra71_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
- } else if (board_is_dra72x_revc_or_later()) {
- delta_pads = dra72x_rgmii_padconf_array_revc;
- delta_npads =
- ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
- iodelay = dra72_iodelay_cfg_array_revc;
- niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
- } else {
- delta_pads = dra72x_rgmii_padconf_array_revb;
- delta_npads =
- ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
- iodelay = dra72_iodelay_cfg_array_revb;
- niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
- }
- break;
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- pads = dra74x_core_padconf_array;
- npads = ARRAY_SIZE(dra74x_core_padconf_array);
- iodelay = dra742_es1_1_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
- break;
- case DRA762_ACD_ES1_0:
- case DRA762_ES1_0:
- pads = dra76x_core_padconf_array;
- npads = ARRAY_SIZE(dra76x_core_padconf_array);
- iodelay = dra76x_es1_0_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
- break;
- default:
- case DRA752_ES2_0:
- case DRA762_ABZ_ES1_0:
- pads = dra74x_core_padconf_array;
- npads = ARRAY_SIZE(dra74x_core_padconf_array);
- iodelay = dra742_es2_0_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
- /* Setup port1 and port2 for rgmii with 'no-id' mode */
- clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
- RGMII1_ID_MODE_N_MASK);
- break;
- }
- /* Setup I/O isolation */
- ret = __recalibrate_iodelay_start();
- if (ret)
- goto err;
-
- /* Do the muxing here */
- do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
-
- /* Now do the weird minor deltas that should be safe */
- if (delta_npads)
- do_set_mux32((*ctrl)->control_padconf_core_base,
- delta_pads, delta_npads);
-
- if (is_dra76x())
- /* Set mux for MCAN instead of DCAN1 */
- clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
- MCAN_SEL_ALT_MASK, MCAN_SEL);
-
- /* Setup IOdelay configuration */
- ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
-err:
- /* Closeup.. remove isolation */
- __recalibrate_iodelay_end(ret);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- return 0;
-}
-
-void board_mmc_poweron_ldo(uint voltage)
-{
- if (board_is_dra71x_evm()) {
- if (voltage == LDO_VOLT_3V0)
- voltage = 0x19;
- else if (voltage == LDO_VOLT_1V8)
- voltage = 0xa;
- lp873x_mmc1_poweron_ldo(voltage);
- } else if (board_is_dra76x_evm()) {
- palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
- } else {
- palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
- }
-}
-
-static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
- .hw_rev = "rev11",
- .unsupported_caps = MMC_CAP(MMC_HS_200) |
- MMC_CAP(UHS_SDR104),
- .max_freq = 96000000,
-};
-
-static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
- .hw_rev = "rev11",
- .unsupported_caps = MMC_CAP(MMC_HS_200) |
- MMC_CAP(UHS_SDR104) |
- MMC_CAP(UHS_SDR50),
- .max_freq = 48000000,
-};
-
-const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
-{
- switch (omap_revision()) {
- case DRA752_ES1_0:
- case DRA752_ES1_1:
- if (addr == OMAP_HSMMC1_BASE)
- return &dra7x_es1_1_mmc1_fixups;
- else
- return &dra7x_es1_1_mmc23_fixups;
- default:
- return NULL;
- }
-}
-#endif
-
-#ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss1 = {
- .maximum_speed = USB_SPEED_SUPER,
- .base = DRA7_USB_OTG_SS1_BASE,
- .tx_fifo_resize = false,
- .index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss1_glue = {
- .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
- .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
- .index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy1_device = {
- .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
- .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
- .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
- .index = 0,
-};
-
-static struct dwc3_device usb_otg_ss2 = {
- .maximum_speed = USB_SPEED_SUPER,
- .base = DRA7_USB_OTG_SS2_BASE,
- .tx_fifo_resize = false,
- .index = 1,
-};
-
-static struct dwc3_omap_device usb_otg_ss2_glue = {
- .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
- .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
- .index = 1,
-};
-
-static struct ti_usb_phy_device usb_phy2_device = {
- .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
- .index = 1,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- enable_usb_clocks(index);
- switch (index) {
- case 0:
- if (init == USB_INIT_DEVICE) {
- usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
- }
-
- ti_usb_phy_uboot_init(&usb_phy1_device);
- dwc3_omap_uboot_init(&usb_otg_ss1_glue);
- dwc3_uboot_init(&usb_otg_ss1);
- break;
- case 1:
- if (init == USB_INIT_DEVICE) {
- usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
- usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
- }
-
- ti_usb_phy_uboot_init(&usb_phy2_device);
- dwc3_omap_uboot_init(&usb_otg_ss2_glue);
- dwc3_uboot_init(&usb_otg_ss2);
- break;
- default:
- printf("Invalid Controller Index\n");
- }
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- switch (index) {
- case 0:
- case 1:
- ti_usb_phy_uboot_exit(index);
- dwc3_uboot_exit(index);
- dwc3_omap_uboot_exit(index);
- break;
- default:
- printf("Invalid Controller Index\n");
- }
- disable_usb_clocks(index);
- return 0;
-}
-
-int usb_gadget_handle_interrupts(int index)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(index);
- if (status)
- dwc3_uboot_handle_interrupt(index);
-
- return 0;
-}
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
-#ifdef CONFIG_SPL_ENV_SUPPORT
- env_init();
- env_load();
- if (env_get_yesno("boot_os") != 1)
- return 1;
-#endif
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-extern u32 *const omap_si_rev;
-
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
-
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 2,
- },
- {
- .slave_reg_ofs = 0x308,
- .sliver_reg_ofs = 0xdc0,
- .phy_addr = 3,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 2,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- int ret;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
- uint32_t ctrl_val;
-
- /* try reading mac address from efuse */
- mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
- mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
- mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = mac_hi & 0xFF;
- mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
- mac_addr[4] = (mac_lo & 0xFF00) >> 8;
- mac_addr[5] = mac_lo & 0xFF;
-
- if (!env_get("ethaddr")) {
- printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- }
-
- mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
- mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
- mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = mac_hi & 0xFF;
- mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
- mac_addr[4] = (mac_lo & 0xFF00) >> 8;
- mac_addr[5] = mac_lo & 0xFF;
-
- if (!env_get("eth1addr")) {
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("eth1addr", mac_addr);
- }
-
- ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
- ctrl_val |= 0x22;
- writel(ctrl_val, (*ctrl)->control_core_control_io1);
-
- if (*omap_si_rev == DRA722_ES1_0)
- cpsw_data.active_slave = 1;
-
- if (board_is_dra72x_revc_or_later()) {
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
- cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
- }
-
- ret = cpsw_register(&cpsw_data);
- if (ret < 0)
- printf("Error %d registering CPSW switch\n", ret);
-
- return ret;
-}
-#endif
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-/* VTT regulator enable */
-static inline void vtt_regulator_enable(void)
-{
- if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
- return;
-
- /* Do not enable VTT for DRA722 or DRA76x */
- if (is_dra72x() || is_dra76x())
- return;
-
- /*
- * EVM Rev G and later use gpio7_11 for DDR3 termination.
- * This is safe enough to do on older revs.
- */
- gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
- gpio_direction_output(GPIO_DDR_VTT_EN, 1);
-}
-
-int board_early_init_f(void)
-{
- vtt_regulator_enable();
- return 0;
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
- if (is_dra72x()) {
- if (board_is_dra71x_evm()) {
- if (!strcmp(name, "dra71-evm"))
- return 0;
- }else if(board_is_dra72x_revc_or_later()) {
- if (!strcmp(name, "dra72-evm-revc"))
- return 0;
- } else if (!strcmp(name, "dra72-evm")) {
- return 0;
- }
- } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
- return 0;
- } else if (!is_dra72x() && !is_dra76x_acd() &&
- !strcmp(name, "dra7-evm")) {
- return 0;
- }
-
- return -1;
-}
-#endif
-
-#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
-{
- secure_boot_verify_image(p_image, p_size);
-}
-
-void board_tee_image_process(ulong tee_image, size_t tee_size)
-{
- secure_tee_install((u32)tee_image);
-}
-
-#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
-int fastboot_set_reboot_flag(void)
-{
- printf("Setting reboot to fastboot flag ...\n");
- env_set("dofastboot", "1");
- env_save();
- return 0;
-}
-#endif
-
-U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
-#endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
deleted file mode 100644
index f1f6bd53167..00000000000
--- a/board/ti/dra7xx/mux_data.h
+++ /dev/null
@@ -1,1121 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- * Nishant Kamat <nskamat@ti.com>
- */
-#ifndef _MUX_DATA_DRA7XX_H_
-#define _MUX_DATA_DRA7XX_H_
-
-#include <asm/arch/mux_dra7xx.h>
-
-const struct pad_conf_entry dra72x_core_padconf_array_common[] = {
- {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
- {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
- {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
- {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
- {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
- {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
- {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
- {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
- {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
- {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
- {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
- {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
- {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
- {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
- {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
- {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
- {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
- {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
- {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
- {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
- {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
- {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
- {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
- {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
- {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
- {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
- {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
- {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
- {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
- {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
- {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
- {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
- {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
- {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
- {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
- {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
- {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
- {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
- {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
- {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
- {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
- {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
- {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
- {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
- {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 */
- {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_hsync0.vin2a_hsync0 */
- {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_vsync0.vin2a_vsync0 */
- {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d0.vin2a_d0 */
- {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d1.vin2a_d1 */
- {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d2.vin2a_d2 */
- {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d3.vin2a_d3 */
- {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d4.vin2a_d4 */
- {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d5.vin2a_d5 */
- {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d6.vin2a_d6 */
- {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d7.vin2a_d7 */
- {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d8.vin2a_d8 */
- {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d9.vin2a_d9 */
- {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d10.vin2a_d10 */
- {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d11.vin2a_d11 */
- {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
- {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
- {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
- {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
- {MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr0.i2c5_sda */
- {MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.i2c5_scl */
- {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
- {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
- {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
- {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
- {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
- {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
- {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
- {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
- {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
- {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
- {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
- {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
- {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
- {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
- {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
- {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
- {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
- {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
- {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
- {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
- {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
- {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rxd.mmc4_dat0 */
- {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
- {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
- {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
- {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
- {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
-};
-
-const struct pad_conf_entry dra72x_rgmii_padconf_array_revb[] = {
- {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
- {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */
- {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */
- {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */
-};
-
-const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
- {VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
- {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
-};
-
-const struct pad_conf_entry dra71x_core_padconf_array[] = {
- {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
- {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
- {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
- {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
- {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
- {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
- {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
- {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
- {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
- {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
- {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
- {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
- {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
- {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
- {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
- {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
- {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
- {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
- {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
- {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
- {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
- {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
- {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
- {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
- {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
- {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
- {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
- {GPMC_A11, (M14 | PIN_INPUT)}, /* gpmc_a11.gpio2_1 */
- {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
- {GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
- {GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
- {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
- {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
- {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
- {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
- {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
- {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
- {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
- {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
- {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
- {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
- {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
- {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
- {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
- {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_clk0.vin2a_clk0 */
- {VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */
- {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_hsync0.vin2a_hsync0 */
- {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* vin2a_vsync0.vin2a_vsync0 */
- {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d0.vin2a_d0 */
- {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d1.vin2a_d1 */
- {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* vin2a_d2.vin2a_d2 */
- {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d3.vin2a_d3 */
- {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d4.vin2a_d4 */
- {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)}, /* vin2a_d5.vin2a_d5 */
- {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d6.vin2a_d6 */
- {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)}, /* vin2a_d7.vin2a_d7 */
- {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d8.vin2a_d8 */
- {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)}, /* vin2a_d9.vin2a_d9 */
- {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d10.vin2a_d10 */
- {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)}, /* vin2a_d11.vin2a_d11 */
- {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
- {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
- {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* N/A.N/A */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
- {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
- {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
- {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
- {MCASP1_ACLKX, (M14 | PIN_INPUT)}, /* mcasp1_aclkx.gpio7_31 */
- {MCASP1_FSX, (M14 | 0x000d0000)}, /* mcasp1_fsx.gpio7_30 */
- {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
- {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
- {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
- {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
- {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
- {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
- {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
- {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
- {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
- {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
- {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
- {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
- {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
- {SPI1_CS1, (M14 | PIN_INPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
- {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
- {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
- {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
- {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
- {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
- {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
- {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
- {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
- {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rxd.mmc4_dat0 */
- {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
- {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
- {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
- {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
- {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
-};
-
-const struct pad_conf_entry early_padconf[] = {
- {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
- {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */
- {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */
- {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */
- {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */
- {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */
-};
-
-#ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = {
- {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */
- {0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */
- {0x708, 80, 1391}, /* RGMMI0_RXD0_IN */
- {0x714, 196, 1522}, /* RGMMI0_RXD1_IN */
- {0x720, 40, 1860}, /* RGMMI0_RXD2_IN */
- {0x72C, 0, 1956}, /* RGMMI0_RXD3_IN */
- {0x740, 0, 220}, /* RGMMI0_TXC_OUT */
- {0x74C, 1820, 180}, /* RGMMI0_TXCTL_OUT */
- {0x758, 1740, 440}, /* RGMMI0_TXD0_OUT */
- {0x764, 1740, 240}, /* RGMMI0_TXD1_OUT */
- {0x770, 1680, 380}, /* RGMMI0_TXD2_OUT */
- {0x77C, 1740, 440}, /* RGMMI0_TXD3_OUT */
- /* These values are for using RGMII1 configuration on VIN2a_x pins. */
- {0xAB0, 596, 0}, /* CFG_VIN2A_D18_IN */
- {0xABC, 314, 980}, /* CFG_VIN2A_D19_IN */
- {0xAD4, 241, 1536}, /* CFG_VIN2A_D20_IN */
- {0xAE0, 103, 1689}, /* CFG_VIN2A_D21_IN */
- {0xAEC, 161, 1563}, /* CFG_VIN2A_D22_IN */
- {0xAF8, 0, 1613}, /* CFG_VIN2A_D23_IN */
- {0xA70, 0, 200}, /* CFG_VIN2A_D12_OUT */
- {0xA7C, 1560, 140}, /* CFG_VIN2A_D13_OUT */
- {0xA88, 1700, 0}, /* CFG_VIN2A_D14_OUT */
- {0xA94, 1260, 0}, /* CFG_VIN2A_D15_OUT */
- {0xAA0, 1400, 0}, /* CFG_VIN2A_D16_OUT */
- {0xAAC, 1290, 0}, /* CFG_VIN2A_D17_OUT */
- {0x144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x150, 2062, 2277}, /* CFG_GPMC_A14_IN */
- {0x15C, 1960, 2289}, /* CFG_GPMC_A15_IN */
- {0x168, 2058, 2386}, /* CFG_GPMC_A16_IN */
- {0x170, 0, 0 }, /* CFG_GPMC_A16_OUT */
- {0x174, 2062, 2350}, /* CFG_GPMC_A17_IN */
- {0x188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */
-};
-
-const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revc[] = {
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
- {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
- {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
- {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
- {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 121, 0}, /* CFG_GPMC_CS2_OUT */
- {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
- {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
- {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
- {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
-};
-
-const struct iodelay_cfg_entry dra71_iodelay_cfg_array[] = {
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
- {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
- {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
- {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
- {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
- {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
- {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
- {0x0A44, 1936, 0}, /* CFG_VIN2A_D0_IN */
- {0x0A50, 2031, 0}, /* CFG_VIN2A_D10_IN */
- {0x0A5C, 1702, 0}, /* CFG_VIN2A_D11_IN */
- {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
- {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
- {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
- {0x0B04, 1736, 0}, /* CFG_VIN2A_D2_IN */
- {0x0B10, 1943, 0}, /* CFG_VIN2A_D3_IN */
- {0x0B1C, 1601, 0}, /* CFG_VIN2A_D4_IN */
- {0x0B28, 2052, 0}, /* CFG_VIN2A_D5_IN */
- {0x0B34, 1571, 0}, /* CFG_VIN2A_D6_IN */
- {0x0B40, 1855, 0}, /* CFG_VIN2A_D7_IN */
- {0x0B4C, 1224, 618}, /* CFG_VIN2A_D8_IN */
- {0x0B58, 1373, 509}, /* CFG_VIN2A_D9_IN */
- {0x0B7C, 1943, 0}, /* CFG_VIN2A_HSYNC0_IN */
- {0x0B88, 1612, 0}, /* CFG_VIN2A_VSYNC0_IN */
-};
-#endif
-
-const struct pad_conf_entry dra74x_core_padconf_array[] = {
- {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
- {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
- {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
- {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
- {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
- {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
- {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
- {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
- {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
- {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
- {GPMC_AD10, (M3 | PIN_INPUT)}, /* gpmc_ad10.vout3_d10 */
- {GPMC_AD11, (M3 | PIN_INPUT)}, /* gpmc_ad11.vout3_d11 */
- {GPMC_AD12, (M3 | PIN_INPUT)}, /* gpmc_ad12.vout3_d12 */
- {GPMC_AD13, (M3 | PIN_INPUT)}, /* gpmc_ad13.vout3_d13 */
- {GPMC_AD14, (M3 | PIN_INPUT)}, /* gpmc_ad14.vout3_d14 */
- {GPMC_AD15, (M3 | PIN_INPUT)}, /* gpmc_ad15.vout3_d15 */
- {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a0.vout3_d16 */
- {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a1.vout3_d17 */
- {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a2.vout3_d18 */
- {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a3.vout3_d19 */
- {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a4.vout3_d20 */
- {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a5.vout3_d21 */
- {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a6.vout3_d22 */
- {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a7.vout3_d23 */
- {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a8.vout3_hsync */
- {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a9.vout3_vsync */
- {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)}, /* gpmc_a10.vout3_de */
- {GPMC_A11, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a11.gpio2_1 */
- {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
- {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
- {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
- {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
- {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
- {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
- {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
- {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
- {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
- {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
- {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
- {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
- {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
- {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
- {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
- {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {GPMC_CS3, (M3 | PIN_INPUT_PULLUP)}, /* gpmc_cs3.vout3_clk */
- {VIN1A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_clk0.vin1a_clk0 */
- {VIN1A_DE0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_de0.vin1a_de0 */
- {VIN1A_FLD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_fld0.vin1a_fld0 */
- {VIN1A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_hsync0.vin1a_hsync0 */
- {VIN1A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_vsync0.vin1a_vsync0 */
- {VIN1A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d0.vin1a_d0 */
- {VIN1A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d1.vin1a_d1 */
- {VIN1A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d2.vin1a_d2 */
- {VIN1A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d3.vin1a_d3 */
- {VIN1A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d4.vin1a_d4 */
- {VIN1A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d5.vin1a_d5 */
- {VIN1A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d6.vin1a_d6 */
- {VIN1A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d7.vin1a_d7 */
- {VIN1A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d8.vin1a_d8 */
- {VIN1A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d9.vin1a_d9 */
- {VIN1A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d10.vin1a_d10 */
- {VIN1A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d11.vin1a_d11 */
- {VIN1A_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d12.vin1a_d12 */
- {VIN1A_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d13.vin1a_d13 */
- {VIN1A_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d14.vin1a_d14 */
- {VIN1A_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d15.vin1a_d15 */
- {VIN1A_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d16.vin1a_d16 */
- {VIN1A_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d17.vin1a_d17 */
- {VIN1A_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d18.vin1a_d18 */
- {VIN1A_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d19.vin1a_d19 */
- {VIN1A_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d20.vin1a_d20 */
- {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d21.vin1a_d21 */
- {VIN1A_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d22.vin1a_d22 */
- {VIN1A_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin1a_d23.vin1a_d23 */
- {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
- {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
- {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
- {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
- {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
- {MCASP1_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.mcasp1_aclkx */
- {MCASP1_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.mcasp1_fsx */
- {MCASP1_AXR0, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE15)}, /* mcasp1_axr0.mcasp1_axr0 */
- {MCASP1_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.mcasp1_axr1 */
- {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
- {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
- {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
- {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
- {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
- {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
- {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
- {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
- {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
- {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
- {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
- {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
- {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
- {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
- {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
- {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
- {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
- {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
- {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */
- {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
- {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
- {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
- {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
- {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
- {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
- {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
- {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */
- {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */
- {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
- {WAKEUP2, (M14)}, /* Wakeup2.gpio1_2 */
-};
-
-const struct pad_conf_entry dra76x_core_padconf_array[] = {
- {GPMC_AD0, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vout3_d0 */
- {GPMC_AD1, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vout3_d1 */
- {GPMC_AD2, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vout3_d2 */
- {GPMC_AD3, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vout3_d3 */
- {GPMC_AD4, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vout3_d4 */
- {GPMC_AD5, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vout3_d5 */
- {GPMC_AD6, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vout3_d6 */
- {GPMC_AD7, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vout3_d7 */
- {GPMC_AD8, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vout3_d8 */
- {GPMC_AD9, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vout3_d9 */
- {GPMC_AD10, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad10.vout3_d10 */
- {GPMC_AD11, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad11.vout3_d11 */
- {GPMC_AD12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad12.vout3_d12 */
- {GPMC_AD13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad13.vout3_d13 */
- {GPMC_AD14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad14.vout3_d14 */
- {GPMC_AD15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad15.vout3_d15 */
- {GPMC_A0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vout3_d16 */
- {GPMC_A1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vout3_d17 */
- {GPMC_A2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vout3_d18 */
- {GPMC_A3, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vout3_d19 */
- {GPMC_A4, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vout3_d20 */
- {GPMC_A5, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vout3_d21 */
- {GPMC_A6, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vout3_d22 */
- {GPMC_A7, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vout3_d23 */
- {GPMC_A8, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vout3_hsync */
- {GPMC_A9, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vout3_vsync */
- {GPMC_A10, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vout3_de */
- {GPMC_A11, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a11.gpio2_1 */
- {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */
- {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
- {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
- {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
- {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
- {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
- {GPMC_A19, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a19.mmc2_dat4 */
- {GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a20.mmc2_dat5 */
- {GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a21.mmc2_dat6 */
- {GPMC_A22, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a22.mmc2_dat7 */
- {GPMC_A23, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a23.mmc2_clk */
- {GPMC_A24, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a24.mmc2_dat0 */
- {GPMC_A25, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a25.mmc2_dat1 */
- {GPMC_A26, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a26.mmc2_dat2 */
- {GPMC_A27, (M1 | PIN_INPUT_PULLDOWN)}, /* gpmc_a27.mmc2_dat3 */
- {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
- {GPMC_CS0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_cs0.gpmc_cs0 */
- {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {GPMC_CS3, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs3.vout3_clk */
- {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpmc_advn_ale */
- {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpmc_oen_ren */
- {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpmc_wen */
- {GPMC_BEN0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_ben0.gpmc_ben0 */
- {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpmc_wait0 */
- {VIN1A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin1a_fld0.gpio3_1 */
- {VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_clk0.vin2a_clk0 */
- {VIN2A_DE0, (M15 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_de0.Driveroff */
- {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
- {VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_hsync0.vin2a_hsync0 */
- {VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_vsync0.vin2a_vsync0 */
- {VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d0.vin2a_d0 */
- {VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d1.vin2a_d1 */
- {VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d2.vin2a_d2 */
- {VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d3.vin2a_d3 */
- {VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d4.vin2a_d4 */
- {VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.vin2a_d5 */
- {VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d6.vin2a_d6 */
- {VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d7.vin2a_d7 */
- {VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d8.vin2a_d8 */
- {VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d9.vin2a_d9 */
- {VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d10.vin2a_d10 */
- {VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d11.vin2a_d11 */
- {VIN2A_D12, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
- {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
- {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
- {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
- {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
- {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_de.vout1_de */
- {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */
- {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {RGMII0_TXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
- {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */
- {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */
- {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
- {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
- {MCASP1_ACLKX, (M14 | 0x00070000)}, /* mcasp1_aclkx.gpio7_31 */
- {MCASP1_FSX, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.gpio7_30 */
- {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
- {MCASP1_AXR1, (M10 | 0x000f0000)}, /* mcasp1_axr1.i2c5_scl */
- {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
- {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
- {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLUP)}, /* mcasp2_aclkr.Driveroff */
- {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
- {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
- {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
- {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)}, /* mcasp3_axr1.mcasp3_axr1 */
- {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.mmc1_sdcd */
- {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */
- {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */
- {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */
- {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */
- {SPI1_CS0, (M0 | PIN_INPUT_PULLUP)}, /* spi1_cs0.spi1_cs0 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.uart3_rxd */
- {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */
- {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */
- {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */
- {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
- {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
- {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
- {UART1_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_ctsn.mmc4_clk */
- {UART1_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart1_rtsn.mmc4_cmd */
- {UART2_RXD, (M3 | PIN_INPUT_PULLUP)}, /* N/A.mmc4_dat0 */
- {UART2_TXD, (M3 | PIN_INPUT_PULLUP)}, /* uart2_txd.mmc4_dat1 */
- {UART2_CTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.mmc4_dat2 */
- {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */
- {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_0 */
- {WAKEUP1, (M14 | PIN_OUTPUT)}, /* N/A.gpio1_1 */
- {WAKEUP2, (M14 | PIN_INPUT)}, /* N/A.gpio1_2 */
- {WAKEUP3, (M1 | PIN_OUTPUT)}, /* N/A.sys_nirq1 */
-};
-
-#ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
- {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 0, 0}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 1560, 120}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 1570, 120}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 1500, 120}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 1775, 120}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 1875, 120}, /* CFG_RGMII0_TXD3_OUT */
- {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
- {0x08DC, 2600, 0}, /* CFG_VIN1A_D0_IN */
- {0x08E8, 2652, 46}, /* CFG_VIN1A_D10_IN */
- {0x08F4, 2541, 0}, /* CFG_VIN1A_D11_IN */
- {0x0900, 2603, 574}, /* CFG_VIN1A_D12_IN */
- {0x090C, 2548, 443}, /* CFG_VIN1A_D13_IN */
- {0x0918, 2624, 598}, /* CFG_VIN1A_D14_IN */
- {0x0924, 2535, 1027}, /* CFG_VIN1A_D15_IN */
- {0x0930, 2526, 818}, /* CFG_VIN1A_D16_IN */
- {0x093C, 2623, 797}, /* CFG_VIN1A_D17_IN */
- {0x0948, 2578, 888}, /* CFG_VIN1A_D18_IN */
- {0x0954, 2574, 1008}, /* CFG_VIN1A_D19_IN */
- {0x0960, 2527, 123}, /* CFG_VIN1A_D1_IN */
- {0x096C, 2577, 737}, /* CFG_VIN1A_D20_IN */
- {0x0978, 2627, 616}, /* CFG_VIN1A_D21_IN */
- {0x0984, 2573, 777}, /* CFG_VIN1A_D22_IN */
- {0x0990, 2730, 67}, /* CFG_VIN1A_D23_IN */
- {0x099C, 2509, 303}, /* CFG_VIN1A_D2_IN */
- {0x09A8, 2494, 267}, /* CFG_VIN1A_D3_IN */
- {0x09B4, 2474, 0}, /* CFG_VIN1A_D4_IN */
- {0x09C0, 2556, 181}, /* CFG_VIN1A_D5_IN */
- {0x09CC, 2516, 195}, /* CFG_VIN1A_D6_IN */
- {0x09D8, 2589, 210}, /* CFG_VIN1A_D7_IN */
- {0x09E4, 2624, 75}, /* CFG_VIN1A_D8_IN */
- {0x09F0, 2704, 14}, /* CFG_VIN1A_D9_IN */
- {0x09FC, 2469, 55}, /* CFG_VIN1A_DE0_IN */
- {0x0A08, 2557, 264}, /* CFG_VIN1A_FLD0_IN */
- {0x0A14, 2465, 269}, /* CFG_VIN1A_HSYNC0_IN */
- {0x0A20, 2411, 348}, /* CFG_VIN1A_VSYNC0_IN */
- {0x0A70, 150, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 1500, 0}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 1600, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 900, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 680, 0}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 500, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
- {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 1976, 1389}, /* CFG_GPMC_A14_IN */
- {0x015C, 1872, 1408}, /* CFG_GPMC_A15_IN */
- {0x0168, 1914, 1506}, /* CFG_GPMC_A16_IN */
- {0x0170, 57, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */
- {0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
-};
-
-const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
- {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 70, 70}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 35, 70}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 100, 130}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 0, 70}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 100, 130}, /* CFG_RGMII0_TXD3_OUT */
- {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
- {0x08DC, 2105, 619}, /* CFG_VIN1A_D0_IN */
- {0x08E8, 2107, 739}, /* CFG_VIN1A_D10_IN */
- {0x08F4, 2005, 788}, /* CFG_VIN1A_D11_IN */
- {0x0900, 2059, 1297}, /* CFG_VIN1A_D12_IN */
- {0x090C, 2027, 1141}, /* CFG_VIN1A_D13_IN */
- {0x0918, 2071, 1332}, /* CFG_VIN1A_D14_IN */
- {0x0924, 1995, 1764}, /* CFG_VIN1A_D15_IN */
- {0x0930, 1999, 1542}, /* CFG_VIN1A_D16_IN */
- {0x093C, 2072, 1540}, /* CFG_VIN1A_D17_IN */
- {0x0948, 2034, 1629}, /* CFG_VIN1A_D18_IN */
- {0x0954, 2026, 1761}, /* CFG_VIN1A_D19_IN */
- {0x0960, 2017, 757}, /* CFG_VIN1A_D1_IN */
- {0x096C, 2037, 1469}, /* CFG_VIN1A_D20_IN */
- {0x0978, 2077, 1349}, /* CFG_VIN1A_D21_IN */
- {0x0984, 2022, 1545}, /* CFG_VIN1A_D22_IN */
- {0x0990, 2168, 784}, /* CFG_VIN1A_D23_IN */
- {0x099C, 1996, 962}, /* CFG_VIN1A_D2_IN */
- {0x09A8, 1993, 901}, /* CFG_VIN1A_D3_IN */
- {0x09B4, 2098, 499}, /* CFG_VIN1A_D4_IN */
- {0x09C0, 2038, 844}, /* CFG_VIN1A_D5_IN */
- {0x09CC, 2002, 863}, /* CFG_VIN1A_D6_IN */
- {0x09D8, 2063, 873}, /* CFG_VIN1A_D7_IN */
- {0x09E4, 2088, 759}, /* CFG_VIN1A_D8_IN */
- {0x09F0, 2152, 701}, /* CFG_VIN1A_D9_IN */
- {0x09FC, 1926, 728}, /* CFG_VIN1A_DE0_IN */
- {0x0A08, 2043, 937}, /* CFG_VIN1A_FLD0_IN */
- {0x0A14, 1978, 909}, /* CFG_VIN1A_HSYNC0_IN */
- {0x0A20, 1926, 987}, /* CFG_VIN1A_VSYNC0_IN */
- {0x0A70, 140, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 90, 70}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 0, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 0, 70}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
- {0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 2575, 966}, /* CFG_GPMC_A14_IN */
- {0x015C, 2503, 889}, /* CFG_GPMC_A15_IN */
- {0x0168, 2528, 1007}, /* CFG_GPMC_A16_IN */
- {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */
- {0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
-};
-
-const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = {
- {0x011C, 787, 0}, /* CFG_GPMC_A0_OUT */
- {0x0128, 1181, 0}, /* CFG_GPMC_A10_OUT */
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */
- {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */
- {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */
- {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */
- {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x01A0, 592, 0}, /* CFG_GPMC_A1_OUT */
- {0x020C, 641, 0}, /* CFG_GPMC_A2_OUT */
- {0x0218, 1481, 0}, /* CFG_GPMC_A3_OUT */
- {0x0224, 1775, 0}, /* CFG_GPMC_A4_OUT */
- {0x0230, 785, 0}, /* CFG_GPMC_A5_OUT */
- {0x023C, 848, 0}, /* CFG_GPMC_A6_OUT */
- {0x0248, 851, 0}, /* CFG_GPMC_A7_OUT */
- {0x0254, 1783, 0}, /* CFG_GPMC_A8_OUT */
- {0x0260, 951, 0}, /* CFG_GPMC_A9_OUT */
- {0x026C, 1091, 0}, /* CFG_GPMC_AD0_OUT */
- {0x0278, 1027, 0}, /* CFG_GPMC_AD10_OUT */
- {0x0284, 824, 0}, /* CFG_GPMC_AD11_OUT */
- {0x0290, 1196, 0}, /* CFG_GPMC_AD12_OUT */
- {0x029C, 754, 0}, /* CFG_GPMC_AD13_OUT */
- {0x02A8, 665, 0}, /* CFG_GPMC_AD14_OUT */
- {0x02B4, 1027, 0}, /* CFG_GPMC_AD15_OUT */
- {0x02C0, 937, 0}, /* CFG_GPMC_AD1_OUT */
- {0x02CC, 1168, 0}, /* CFG_GPMC_AD2_OUT */
- {0x02D8, 872, 0}, /* CFG_GPMC_AD3_OUT */
- {0x02E4, 1092, 0}, /* CFG_GPMC_AD4_OUT */
- {0x02F0, 576, 0}, /* CFG_GPMC_AD5_OUT */
- {0x02FC, 1113, 0}, /* CFG_GPMC_AD6_OUT */
- {0x0308, 943, 0}, /* CFG_GPMC_AD7_OUT */
- {0x0314, 0, 0}, /* CFG_GPMC_AD8_OUT */
- {0x0320, 0, 0}, /* CFG_GPMC_AD9_OUT */
- {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
- {0x0380, 1801, 948}, /* CFG_GPMC_CS3_OUT */
- {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */
- {0x0A38, 0, 0}, /* CFG_VIN2A_CLK0_IN */
- {0x0A44, 2180, 0}, /* CFG_VIN2A_D0_IN */
- {0x0A50, 2297, 110}, /* CFG_VIN2A_D10_IN */
- {0x0A5C, 1938, 0}, /* CFG_VIN2A_D11_IN */
- {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */
- {0x0AC8, 2326, 309}, /* CFG_VIN2A_D1_IN */
- {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */
- {0x0B04, 2057, 0}, /* CFG_VIN2A_D2_IN */
- {0x0B10, 2440, 257}, /* CFG_VIN2A_D3_IN */
- {0x0B1C, 2142, 0}, /* CFG_VIN2A_D4_IN */
- {0x0B28, 2455, 252}, /* CFG_VIN2A_D5_IN */
- {0x0B34, 1883, 0}, /* CFG_VIN2A_D6_IN */
- {0x0B40, 2229, 0}, /* CFG_VIN2A_D7_IN */
- {0x0B4C, 2250, 151}, /* CFG_VIN2A_D8_IN */
- {0x0B58, 2279, 27}, /* CFG_VIN2A_D9_IN */
- {0x0B7C, 2233, 0}, /* CFG_VIN2A_HSYNC0_IN */
- {0x0B88, 1936, 0}, /* CFG_VIN2A_VSYNC0_IN */
- {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */
- {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */
- {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */
- {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */
- {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */
- {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */
- {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */
- {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */
- {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */
- {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */
- {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */
- {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */
- {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */
- {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */
- {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */
- {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */
- {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */
- {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */
- {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */
- {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */
- {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */
- {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */
- {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */
- {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */
- {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */
- {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
- {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
- {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */
-};
-#endif
-
-#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
deleted file mode 100644
index 27f6b5d981f..00000000000
--- a/configs/dra7xx_evm_defconfig
+++ /dev/null
@@ -1,102 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ARMV7_LPAE=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_CMD_SPL=y
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
-CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_DWC_AHCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=1
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_GPIO=y
-CONFIG_PCF8575_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_SPL_MMC_HS200_SUPPORT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_ETH=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_SPL_PHY=y
-CONFIG_PIPE3_PHY=y
-CONFIG_PMIC_PALMAS=y
-CONFIG_PMIC_LP873X=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_PALMAS=y
-CONFIG_DM_REGULATOR_LP873X=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DRA7XX_INDEX=1
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
deleted file mode 100644
index 651fc4fb427..00000000000
--- a/configs/dra7xx_hs_evm_defconfig
+++ /dev/null
@@ -1,101 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TI_SECURE_DEVICE=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_OMAP54XX=y
-CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
-CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
-CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_SPL=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_ARMV7_LPAE=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_IMAGE_POST_PROCESS=y
-CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_DMA_SUPPORT=y
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_SPI_LOAD=y
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
-CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SPL_SYSCON=y
-CONFIG_DWC_AHCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_DFU_SF=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
-CONFIG_FASTBOOT_BUF_ADDR=0x82000000
-CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=1
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_GPIO=y
-CONFIG_PCF8575_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_DM_ETH=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY_GIGE=y
-CONFIG_MII=y
-CONFIG_SPL_PHY=y
-CONFIG_PIPE3_PHY=y
-CONFIG_PMIC_PALMAS=y
-CONFIG_PMIC_LP873X=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_PALMAS=y
-CONFIG_DM_REGULATOR_LP873X=y
-CONFIG_DM_SCSI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_XHCI_DRA7XX_INDEX=1
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_OMAP_USB_PHY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
deleted file mode 100644
index 2d8758db754..00000000000
--- a/include/configs/dra7xx_evm.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated.
- * Lokesh Vutla <lokeshvutla@ti.com>
- *
- * Configuration settings for the TI DRA7XX board.
- * See ti_omap5_common.h for omap5 common settings.
- */
-
-#ifndef __CONFIG_DRA7XX_EVM_H
-#define __CONFIG_DRA7XX_EVM_H
-
-#include <environment/ti/dfu.h>
-
-#define CONFIG_IODELAY_RECALIBRATION
-
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED 0x80000000
-
-#ifndef CONFIG_QSPI_BOOT
-/* MMC ENV related defines */
-#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_ENV_OFFSET 0x260000
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#endif
-
-#if (CONFIG_CONS_INDEX == 1)
-#define CONSOLEDEV "ttyO0"
-#elif (CONFIG_CONS_INDEX == 3)
-#define CONSOLEDEV "ttyO2"
-#endif
-#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
-
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-#define CONFIG_SYS_OMAP_ABE_SYSCK
-
-#ifndef CONFIG_SPL_BUILD
-#define DFUARGS \
- "dfu_bufsiz=0x10000\0" \
- DFU_ALT_INFO_MMC \
- DFU_ALT_INFO_EMMC \
- DFU_ALT_INFO_RAM \
- DFU_ALT_INFO_QSPI
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_CMD_BOOTD
-#ifdef CONFIG_SPL_DFU_SUPPORT
-#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
-#define DFUARGS \
- "dfu_bufsiz=0x10000\0" \
- DFU_ALT_INFO_RAM
-#endif
-#endif
-
-#include <configs/ti_omap5_common.h>
-
-/* Enhance our eMMC support / experience. */
-#define CONFIG_HSMMC2_8BIT
-
-/* CPSW Ethernet */
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_TI
-
-/* SPI */
-#define CONFIG_TI_SPI_MMAP
-#define CONFIG_SF_DEFAULT_SPEED 76800000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_QSPI_QUAD_SUPPORT
-
-/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
- * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
- * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
- * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
- * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
- * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
- * 0x9E0000 - 0x2000000 : USERLAND
- */
-#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
-#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
-#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_ENV_SIZE (64 << 10)
-#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
-#define CONFIG_ENV_OFFSET 0x1C0000
-#define CONFIG_ENV_OFFSET_REDUND 0x1D0000
-#endif
-
-/* SPI SPL */
-#define CONFIG_TI_EDMA3
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
-
-#define CONFIG_SUPPORT_EMMC_BOOT
-
-/* USB xHCI HOST */
-#define CONFIG_USB_XHCI_OMAP
-
-#define CONFIG_OMAP_USB2PHY2_HOST
-
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
-/* NAND support */
-#ifdef CONFIG_NAND
-/* NAND: device related configs */
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-/* NAND: driver related configs */
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
- 10, 11, 12, 13, 14, 15, 16, 17, \
- 18, 19, 20, 21, 22, 23, 24, 25, \
- 26, 27, 28, 29, 30, 31, 32, 33, \
- 34, 35, 36, 37, 38, 39, 40, 41, \
- 42, 43, 44, 45, 46, 47, 48, 49, \
- 50, 51, 52, 53, 54, 55, 56, 57, }
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 14
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
-/* NAND: SPL related configs */
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
-#endif
-#endif /* !CONFIG_NAND */
-
-/* Parallel NOR Support */
-#if defined(CONFIG_NOR)
-/* NOR: device related configs */
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
-/* #define CONFIG_INIT_IGNORE_ERROR */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BASE (0x08000000)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-/* Reduce SPL size by removing unlikey targets */
-#ifdef CONFIG_NOR_BOOT
-#define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */
-#define CONFIG_ENV_OFFSET 0x001c0000
-#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
-#endif
-#endif /* NOR support */
-
-#endif /* __CONFIG_DRA7XX_EVM_H */
--
2.19.1.1215.g8438c0b245-goog