[U-Boot] [PATCH 05/93] arm: Remove ls1043ardb_sdcard_SECURE_BOOT board

Simon Glass
2018-11-19T15:52:45Z

This board has not been converted to CONFIG_DM_BLK by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

arch/arm/Kconfig | 1 -
board/freescale/ls1043ardb/Kconfig | 41 ---
board/freescale/ls1043ardb/MAINTAINERS | 16 -
board/freescale/ls1043ardb/Makefile | 10 -
board/freescale/ls1043ardb/README | 54 ----
board/freescale/ls1043ardb/cpld.c | 173 -----------
board/freescale/ls1043ardb/cpld.h | 45 ---
board/freescale/ls1043ardb/ddr.c | 238 ---------------
board/freescale/ls1043ardb/ddr.h | 116 -------
board/freescale/ls1043ardb/eth.c | 76 -----
board/freescale/ls1043ardb/ls1043ardb.c | 221 --------------
board/freescale/ls1043ardb/ls1043ardb_pbi.cfg | 14 -
.../ls1043ardb/ls1043ardb_rcw_nand.cfg | 7 -
.../ls1043ardb/ls1043ardb_rcw_sd.cfg | 7 -
configs/ls1043ardb_SECURE_BOOT_defconfig | 51 ----
configs/ls1043ardb_defconfig | 49 ---
configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 68 -----
configs/ls1043ardb_nand_defconfig | 66 ----
.../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 66 ----
configs/ls1043ardb_sdcard_defconfig | 64 ----
include/configs/ls1043ardb.h | 285 ------------------
21 files changed, 1668 deletions(-)
delete mode 100644 board/freescale/ls1043ardb/Kconfig
delete mode 100644 board/freescale/ls1043ardb/MAINTAINERS
delete mode 100644 board/freescale/ls1043ardb/Makefile
delete mode 100644 board/freescale/ls1043ardb/README
delete mode 100644 board/freescale/ls1043ardb/cpld.c
delete mode 100644 board/freescale/ls1043ardb/cpld.h
delete mode 100644 board/freescale/ls1043ardb/ddr.c
delete mode 100644 board/freescale/ls1043ardb/ddr.h
delete mode 100644 board/freescale/ls1043ardb/eth.c
delete mode 100644 board/freescale/ls1043ardb/ls1043ardb.c
delete mode 100644 board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
delete mode 100644 board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
delete mode 100644 board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
delete mode 100644 configs/ls1043ardb_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1043ardb_defconfig
delete mode 100644 configs/ls1043ardb_nand_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1043ardb_nand_defconfig
delete mode 100644 configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
delete mode 100644 configs/ls1043ardb_sdcard_defconfig
delete mode 100644 include/configs/ls1043ardb.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 11f2e0f826d..08d6db1cadf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1513,7 +1513,6 @@ source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1021aiot/Kconfig"
source "board/freescale/ls1046aqds/Kconfig"
-source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/ls1046ardb/Kconfig"
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
deleted file mode 100644
index 3d9e295c4e7..00000000000
--- a/board/freescale/ls1043ardb/Kconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-
-if TARGET_LS1043ARDB
-
-config SYS_BOARD
- default "ls1043ardb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "fsl-layerscape"
-
-config SYS_CONFIG_NAME
- default "ls1043ardb"
-
-config SYS_HAS_ARMV8_SECURE_BASE
- bool "Enable secure address for PSCI image"
- depends on ARMV8_PSCI
- default n
- help
- PSCI image can be re-located to secure RAM.
- If enabled, please also define the value for ARMV8_SECURE_BASE,
- for LS1043ARDB, it could be some address in OCRAM.
-
-if FSL_LS_PPA
-config SYS_LS_PPA_FW_ADDR
- hex "PPA Firmware Addr"
- default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
- default 0x400000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-
-if CHAIN_OF_TRUST
-config SYS_LS_PPA_ESBC_ADDR
- hex "PPA Firmware HDR Addr"
- default 0x60680000 if SYS_LS_PPA_FW_IN_XIP
- default 0x680000 if SYS_LS_PPA_FW_IN_MMC || SYS_LS_PPA_FW_IN_NAND
-endif
-endif
-
-source "board/freescale/common/Kconfig"
-
-endif
diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS
deleted file mode 100644
index 88fe42e1e8a..00000000000
--- a/board/freescale/ls1043ardb/MAINTAINERS
+++ /dev/null
@@ -1,16 +0,0 @@
-LS1043A BOARD
-M: Mingkai Hu <mingkai.hu@nxp.com>
-S: Maintained
-F: board/freescale/ls1043ardb/
-F: board/freescale/ls1043ardb/ls1043ardb.c
-F: include/configs/ls1043ardb.h
-F: configs/ls1043ardb_defconfig
-F: configs/ls1043ardb_nand_defconfig
-F: configs/ls1043ardb_sdcard_defconfig
-
-LS1043A_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/ls1043ardb_SECURE_BOOT_defconfig
-F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
-F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile
deleted file mode 100644
index 5309576c688..00000000000
--- a/board/freescale/ls1043ardb/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2015 Freescale Semiconductor
-
-obj-y += ddr.o
-obj-y += ls1043ardb.o
-ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_NET) += eth.o
-obj-y += cpld.o
-endif
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
deleted file mode 100644
index 709ddbbef31..00000000000
--- a/board/freescale/ls1043ardb/README
+++ /dev/null
@@ -1,54 +0,0 @@
-Overview
---------
-The LS1043A Reference Design Board (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS1043A
-LayerScape Architecture processor. The LS1043ARDB provides SW development
-platform for the Freescale LS1043A processor series, with a complete
-debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
-
-LS1043A SoC Overview
---------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
-SoC overview.
-
- LS1043ARDB board Overview
- -----------------------
- - SERDES Connections, 4 lanes supporting:
- - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
- standard PCIe card
- - QSGMII with x4 RJ45 connector
- - XFI with x1 RJ45 connector
- - DDR Controller
- - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
- -IFC/Local Bus
- - One 128MB NOR flash 16-bit data bus
- - One 512 MB NAND flash with ECC support
- - CPLD connection
- - USB 3.0
- - Two super speed USB 3.0 Type A ports
- - SDHC: connects directly to a full SD/MMC slot
- - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
- - 4 I2C controllers
- - UART
- - Two 4-pin serial ports at up to 115.2 Kbit/s
- - Two DB9 D-Type connectors supporting one Serial port each
- - ARM JTAG support
-
-Memory map from core's view
-----------------------------
-Start Address End Address Description Size
-0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
-0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
-0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
-0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
-0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
-0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
-0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
-
-Booting Options
----------------
-a) NOR boot
-b) NAND boot
-c) SD boot
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
deleted file mode 100644
index 00c70b1e49d..00000000000
--- a/board/freescale/ls1043ardb/cpld.c
+++ /dev/null
@@ -1,173 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor
- *
- * Freescale LS1043ARDB board-specific CPLD controlling supports.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include "cpld.h"
-
-u8 cpld_read(unsigned int reg)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- return in_8(p + reg);
-}
-
-void cpld_write(unsigned int reg, u8 value)
-{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
-
- out_8(p + reg, value);
-}
-
-/* Set the boot bank to the alternate bank */
-void cpld_set_altbank(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_NOR;
- u8 reg4 = CPLD_READ(soft_mux_on);
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
- u8 reg7 = CPLD_READ(vbank);
-
- cpld_rev_bit(&reg5);
-
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
- CPLD_WRITE(vbank, reg7);
-
- CPLD_WRITE(system_rst, 1);
-}
-
-/* Set the boot bank to the default bank */
-void cpld_set_defbank(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_NOR;
- u8 reg4 = CPLD_READ(soft_mux_on);
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
-
- cpld_rev_bit(&reg5);
-
- CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- CPLD_WRITE(vbank, 0);
-
- CPLD_WRITE(system_rst, 1);
-}
-
-void cpld_set_nand(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_NAND;
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
-
- cpld_rev_bit(&reg5);
-
- CPLD_WRITE(soft_mux_on, 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- CPLD_WRITE(system_rst, 1);
-}
-
-void cpld_set_sd(void)
-{
- u16 reg = CPLD_CFG_RCW_SRC_SD;
- u8 reg5 = (u8)(reg >> 1);
- u8 reg6 = (u8)(reg & 1);
-
- cpld_rev_bit(&reg5);
-
- CPLD_WRITE(soft_mux_on, 1);
-
- CPLD_WRITE(cfg_rcw_src1, reg5);
- CPLD_WRITE(cfg_rcw_src2, reg6);
-
- CPLD_WRITE(system_rst, 1);
-}
-#ifdef DEBUG
-static void cpld_dump_regs(void)
-{
- printf("cpld_ver = %x\n", CPLD_READ(cpld_ver));
- printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub));
- printf("pcba_ver = %x\n", CPLD_READ(pcba_ver));
- printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on));
- printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1));
- printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2));
- printf("vbank = %x\n", CPLD_READ(vbank));
- printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel));
- printf("uart_sel = %x\n", CPLD_READ(uart_sel));
- printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel));
- printf("tdmclk_mux_sel = %x\n", CPLD_READ(tdmclk_mux_sel));
- printf("sdhc_spics_sel = %x\n", CPLD_READ(sdhc_spics_sel));
- printf("status_led = %x\n", CPLD_READ(status_led));
- putc('\n');
-}
-#endif
-
-void cpld_rev_bit(unsigned char *value)
-{
- u8 rev_val, val;
- int i;
-
- val = *value;
- rev_val = val & 1;
- for (i = 1; i <= 7; i++) {
- val >>= 1;
- rev_val <<= 1;
- rev_val |= val & 1;
- }
-
- *value = rev_val;
-}
-
-int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int rc = 0;
-
- if (argc <= 1)
- return cmd_usage(cmdtp);
-
- if (strcmp(argv[1], "reset") == 0) {
- if (strcmp(argv[2], "altbank") == 0)
- cpld_set_altbank();
- else if (strcmp(argv[2], "nand") == 0)
- cpld_set_nand();
- else if (strcmp(argv[2], "sd") == 0)
- cpld_set_sd();
- else
- cpld_set_defbank();
-#ifdef DEBUG
- } else if (strcmp(argv[1], "dump") == 0) {
- cpld_dump_regs();
-#endif
- } else {
- rc = cmd_usage(cmdtp);
- }
-
- return rc;
-}
-
-U_BOOT_CMD(
- cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
- "Reset the board or alternate bank",
- "reset: reset to default bank\n"
- "cpld reset altbank: reset to alternate bank\n"
- "cpld reset nand: reset to boot from NAND flash\n"
- "cpld reset sd: reset to boot from SD card\n"
-#ifdef DEBUG
- "cpld dump - display the CPLD registers\n"
-#endif
-);
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
deleted file mode 100644
index 2e757b557f4..00000000000
--- a/board/freescale/ls1043ardb/cpld.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor
- */
-
-#ifndef __CPLD_H__
-#define __CPLD_H__
-
-/*
- * CPLD register set of LS1043ARDB board-specific.
- */
-struct cpld_data {
- u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
- u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
- u8 pcba_ver; /* 0x2 - PCBA Revision Register */
- u8 system_rst; /* 0x3 - system reset register */
- u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */
- u8 cfg_rcw_src1; /* 0x5 - Reset config word 1 */
- u8 cfg_rcw_src2; /* 0x6 - Reset config word 1 */
- u8 vbank; /* 0x7 - Flash bank selection Control */
- u8 sysclk_sel; /* 0x8 - */
- u8 uart_sel; /* 0x9 - */
- u8 sd1refclk_sel; /* 0xA - */
- u8 tdmclk_mux_sel; /* 0xB - */
- u8 sdhc_spics_sel; /* 0xC - */
- u8 status_led; /* 0xD - */
- u8 global_rst; /* 0xE - */
-};
-
-u8 cpld_read(unsigned int reg);
-void cpld_write(unsigned int reg, u8 value);
-void cpld_rev_bit(unsigned char *value);
-
-#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
-#define CPLD_WRITE(reg, value) \
- cpld_write(offsetof(struct cpld_data, reg), value)
-
-/* CPLD on IFC */
-#define CPLD_SW_MUX_BANK_SEL 0x40
-#define CPLD_BANK_SEL_MASK 0x07
-#define CPLD_BANK_SEL_ALTBANK 0x04
-#define CPLD_CFG_RCW_SRC_NOR 0x025
-#define CPLD_CFG_RCW_SRC_NAND 0x106
-#define CPLD_CFG_RCW_SRC_SD 0x040
-#endif
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
deleted file mode 100644
index 7bc0f568ffb..00000000000
--- a/board/freescale/ls1043ardb/ddr.c
+++ /dev/null
@@ -1,238 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include "ddr.h"
-#ifdef CONFIG_FSL_DEEP_SLEEP
-#include <fsl_sleep.h>
-#endif
-#include <asm/arch/clock.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
-
- if (ctrl_num > 1) {
- printf("Not supported controller number %d\n", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- pbsp = udimms[0];
-
- /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->wrlvl_start = pbsp->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- popts->cpo_override = pbsp->cpo_override;
- popts->write_data_delay =
- pbsp->write_data_delay;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found for %lu MT/s\n",
- ddr_freq);
- printf("Trying to use the highest speed (%u) parameters\n",
- pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->wrlvl_start = pbsp_highest->wrlvl_start;
- popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
- popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
- } else {
- panic("DIMM is not supported by this board");
- }
-found:
- debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
- pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
-
- /* force DDR bus width to 32 bits */
- popts->data_bus_width = 1;
- popts->otf_burst_chop_en = 0;
- popts->burst_length = DDR_BL8;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 1;
- /*
- * Write leveling override
- */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xf;
-
- /*
- * Rtt and Rtt_WR override
- */
- popts->rtt_override = 0;
-
- /* Enable ZQ calibration */
- popts->zq_en = 1;
-
- /* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x46;
-
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
- DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
-}
-
-/* DDR model number: MT40A512M8HX-093E */
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 1,
- .rank_density = 2147483648u,
- .capacity = 2147483648u,
- .primary_sdram_width = 32,
- .ec_sdram_width = 0,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .bank_addr_bits = 0,
- .bank_group_bits = 2,
- .edc_config = 0,
- .burst_lengths_bitmask = 0x0c,
-
- .tckmin_x_ps = 938,
- .tckmax_ps = 1500,
- .caslat_x = 0x000DFA00,
- .taa_ps = 13500,
- .trcd_ps = 13500,
- .trp_ps = 13500,
- .tras_ps = 33000,
- .trc_ps = 46500,
- .trfc1_ps = 260000,
- .trfc2_ps = 160000,
- .trfc4_ps = 110000,
- .tfaw_ps = 21000,
- .trrds_ps = 3700,
- .trrdl_ps = 5300,
- .tccdl_ps = 5355,
- .refresh_rate_ps = 7800000,
- .dq_mapping[0] = 0x0,
- .dq_mapping[1] = 0x0,
- .dq_mapping[2] = 0x0,
- .dq_mapping[3] = 0x0,
- .dq_mapping[4] = 0x0,
- .dq_mapping[5] = 0x0,
- .dq_mapping[6] = 0x0,
- .dq_mapping[7] = 0x0,
- .dq_mapping[8] = 0x0,
- .dq_mapping[9] = 0x0,
- .dq_mapping[10] = 0x0,
- .dq_mapping[11] = 0x0,
- .dq_mapping[12] = 0x0,
- .dq_mapping[13] = 0x0,
- .dq_mapping[14] = 0x0,
- .dq_mapping[15] = 0x0,
- .dq_mapping[16] = 0x0,
- .dq_mapping[17] = 0x0,
- .dq_mapping_ors = 0,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
- unsigned int controller_number,
- unsigned int dimm_number)
-{
- static const char dimm_model[] = "Fixed DDR on board";
-
- if (((controller_number == 0) && (dimm_number == 0)) ||
- ((controller_number == 1) && (dimm_number == 0))) {
- memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
- memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
- memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
- }
-
- return 0;
-}
-#else
-
-phys_size_t fixed_sdram(void)
-{
- int i;
- char buf[32];
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- phys_size_t ddr_size;
- ulong ddr_freq, ddr_freq_mhz;
-
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
- if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
- (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
- memcpy(&ddr_cfg_regs,
- fixed_ddr_parm_0[i].ddr_settings,
- sizeof(ddr_cfg_regs));
- break;
- }
- }
-
- if (fixed_ddr_parm_0[i].max_freq == 0)
- panic("Unsupported DDR data rate %s MT/s data rate\n",
- strmhz(buf, ddr_freq));
-
- ddr_size = (phys_size_t)2048 * 1024 * 1024;
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- return ddr_size;
-}
-#endif
-
-int fsl_initdram(void)
-{
- phys_size_t dram_size;
-
-#ifdef CONFIG_SYS_DDR_RAW_TIMING
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
- puts("Initializing DDR....\n");
- dram_size = fsl_ddr_sdram();
-#else
- dram_size = fsl_ddr_sdram_size();
-#endif
-#else
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
- puts("Initialzing DDR using fixed setting\n");
- dram_size = fixed_sdram();
-#else
- gd->ram_size = 0x80000000;
-
- return 0;
-#endif
-#endif
- erratum_a008850_post();
-
-#ifdef CONFIG_FSL_DEEP_SLEEP
- fsl_dp_ddr_restore();
-#endif
-
- gd->ram_size = dram_size;
-
- return 0;
-}
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
deleted file mode 100644
index 85ed920ca6d..00000000000
--- a/board/freescale/ls1043ardb/ddr.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DDR_H__
-#define __DDR_H__
-
-extern void erratum_a008850_post(void);
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 rank_gb;
- u32 clk_adjust;
- u32 wrlvl_start;
- u32 wrlvl_ctl_2;
- u32 wrlvl_ctl_3;
- u32 cpo_override;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-/*
- * These tables contain all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
- /*
- * memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
- */
-#ifdef CONFIG_SYS_FSL_DDR4
- {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
- {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
- {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
-#endif
- {}
-};
-
-static const struct board_specific_parameters *udimms[] = {
- udimm0,
-};
-
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {
- .cs[0].bnds = 0x0000007F,
- .cs[1].bnds = 0,
- .cs[2].bnds = 0,
- .cs[3].bnds = 0,
- .cs[0].config = 0x80040322,
- .cs[0].config_2 = 0,
- .cs[1].config = 0,
- .cs[1].config_2 = 0,
- .cs[2].config = 0,
- .cs[3].config = 0,
- .timing_cfg_3 = 0x010C1000,
- .timing_cfg_0 = 0x91550018,
- .timing_cfg_1 = 0xBBB48C42,
- .timing_cfg_2 = 0x0048C111,
- .ddr_sdram_cfg = 0xC50C0008,
- .ddr_sdram_cfg_2 = 0x00401100,
- .ddr_sdram_cfg_3 = 0,
- .ddr_sdram_mode = 0x03010210,
- .ddr_sdram_mode_2 = 0,
- .ddr_sdram_mode_3 = 0x00010210,
- .ddr_sdram_mode_4 = 0,
- .ddr_sdram_mode_5 = 0x00010210,
- .ddr_sdram_mode_6 = 0,
- .ddr_sdram_mode_7 = 0x00010210,
- .ddr_sdram_mode_8 = 0,
- .ddr_sdram_mode_9 = 0x00000500,
- .ddr_sdram_mode_10 = 0x04000000,
- .ddr_sdram_mode_11 = 0x00000400,
- .ddr_sdram_mode_12 = 0x04000000,
- .ddr_sdram_mode_13 = 0x00000400,
- .ddr_sdram_mode_14 = 0x04000000,
- .ddr_sdram_mode_15 = 0x00000400,
- .ddr_sdram_mode_16 = 0x04000000,
- .ddr_sdram_interval = 0x18600618,
- .ddr_data_init = 0xDEADBEEF,
- .ddr_sdram_clk_cntl = 0x03000000,
- .ddr_init_addr = 0,
- .ddr_init_ext_addr = 0,
- .timing_cfg_4 = 0x00000002,
- .timing_cfg_5 = 0x03401400,
- .timing_cfg_6 = 0,
- .timing_cfg_7 = 0x13300000,
- .timing_cfg_8 = 0x02115600,
- .timing_cfg_9 = 0,
- .ddr_zq_cntl = 0x8A090705,
- .ddr_wrlvl_cntl = 0x8675F607,
- .ddr_wrlvl_cntl_2 = 0x07090800,
- .ddr_wrlvl_cntl_3 = 0,
- .ddr_sr_cntr = 0,
- .ddr_sdram_rcw_1 = 0,
- .ddr_sdram_rcw_2 = 0,
- .ddr_cdr1 = 0x80040000,
- .ddr_cdr2 = 0x0000A181,
- .dq_map_0 = 0,
- .dq_map_1 = 0,
- .dq_map_2 = 0,
- .dq_map_3 = 0,
- .debug[28] = 0x00700046,
-
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
- {1550, 1650, &ddr_cfg_regs_1600},
- {0, 0, NULL}
-};
-
-#endif
-#endif
diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c
deleted file mode 100644
index a8d0c1109b4..00000000000
--- a/board/freescale/ls1043ardb/eth.c
+++ /dev/null
@@ -1,76 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-#include <common.h>
-#include <asm/io.h>
-#include <netdev.h>
-#include <fm_eth.h>
-#include <fsl_dtsec.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-
-#include "../common/fman.h"
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
- int i;
- struct memac_mdio_info dtsec_mdio_info;
- struct memac_mdio_info tgec_mdio_info;
- struct mii_dev *dev;
- u32 srds_s1;
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-
- srds_s1 = in_be32(&gur->rcwsr[4]) &
- FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
- srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
-
- dtsec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
-
- dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
- /* Register the 1G MDIO bus */
- fm_memac_mdio_init(bis, &dtsec_mdio_info);
-
- tgec_mdio_info.regs =
- (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
- tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
-
- /* Register the 10G MDIO bus */
- fm_memac_mdio_init(bis, &tgec_mdio_info);
-
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
-
- /* QSGMII on lane B, MAC 1/2/5/6 */
- fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
-
- switch (srds_s1) {
- case 0x1455:
- break;
- default:
- printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
- srds_s1);
- break;
- }
-
- dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
- fm_info_set_mdio(i, dev);
-
- /* XFI on lane A, MAC 9 */
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
- fm_info_set_mdio(FM1_10GEC1, dev);
-
- cpu_eth_init(bis);
-#endif
-
- return pci_eth_init(bis);
-}
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
deleted file mode 100644
index f31f0ec515d..00000000000
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/fsl_serdes.h>
-#include <asm/arch/soc.h>
-#include <asm/arch-fsl-layerscape/fsl_icid.h>
-#include <fdt_support.h>
-#include <hwconfig.h>
-#include <ahci.h>
-#include <mmc.h>
-#include <scsi.h>
-#include <fm_eth.h>
-#include <fsl_esdhc.h>
-#include <fsl_ifc.h>
-#include <fsl_sec.h>
-#include "cpld.h"
-#ifdef CONFIG_U_QE
-#include <fsl_qe.h>
-#endif
-#include <asm/arch/ppa.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- fsl_lsch2_early_init_f();
-
- return 0;
-}
-
-#ifndef CONFIG_SPL_BUILD
-
-int checkboard(void)
-{
- static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
-#ifndef CONFIG_SD_BOOT
- u8 cfg_rcw_src1, cfg_rcw_src2;
- u16 cfg_rcw_src;
-#endif
- u8 sd1refclk_sel;
-
- printf("Board: LS1043ARDB, boot from ");
-
-#ifdef CONFIG_SD_BOOT
- puts("SD\n");
-#else
- cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
- cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
- cpld_rev_bit(&cfg_rcw_src1);
- cfg_rcw_src = cfg_rcw_src1;
- cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
-
- if (cfg_rcw_src == 0x25)
- printf("vBank %d\n", CPLD_READ(vbank));
- else if (cfg_rcw_src == 0x106)
- puts("NAND\n");
- else
- printf("Invalid setting of SW4\n");
-#endif
-
- printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
- CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
-
- puts("SERDES Reference Clocks:\n");
- sd1refclk_sel = CPLD_READ(sd1refclk_sel);
- printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
-
- return 0;
-}
-
-int board_init(void)
-{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
- erratum_a010315();
-#endif
-
-#ifdef CONFIG_FSL_IFC
- init_final_memctl_regs();
-#endif
-
-#ifdef CONFIG_SECURE_BOOT
- /* In case of Secure Boot, the IBR configures the SMMU
- * to allow only Secure transactions.
- * SMMU must be reset in bypass mode.
- * Set the ClientPD bit and Clear the USFCFG Bit
- */
- u32 val;
- val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
- out_le32(SMMU_SCR0, val);
- val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
- out_le32(SMMU_NSCR0, val);
-#endif
-
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
-#ifdef CONFIG_FSL_LS_PPA
- ppa_init();
-#endif
-
-#ifdef CONFIG_U_QE
- u_qe_init();
-#endif
- /* invert AQR105 IRQ pins polarity */
- out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
-
- return 0;
-}
-
-int config_board_mux(void)
-{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
- u32 usb_pwrfault;
-
- if (hwconfig("qe-hdlc")) {
- out_be32(&scfg->rcwpmuxcr0,
- (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
- printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
- in_be32(&scfg->rcwpmuxcr0));
- } else {
-#ifdef CONFIG_HAS_FSL_XHCI_USB
- out_be32(&scfg->rcwpmuxcr0, 0x3333);
- out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
- usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
- SCFG_USBPWRFAULT_USB3_SHIFT) |
- (SCFG_USBPWRFAULT_DEDICATED <<
- SCFG_USBPWRFAULT_USB2_SHIFT) |
- (SCFG_USBPWRFAULT_SHARED <<
- SCFG_USBPWRFAULT_USB1_SHIFT);
- out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
-#endif
- }
- return 0;
-}
-
-#if defined(CONFIG_MISC_INIT_R)
-int misc_init_r(void)
-{
- config_board_mux();
- return 0;
-}
-#endif
-
-void fdt_del_qe(void *blob)
-{
- int nodeoff = 0;
-
- while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
- "fsl,qe")) >= 0) {
- fdt_del_node(blob, nodeoff);
- }
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
-
- /* fixup DT for the two DDR banks */
- base[0] = gd->bd->bi_dram[0].start;
- size[0] = gd->bd->bi_dram[0].size;
- base[1] = gd->bd->bi_dram[1].start;
- size[1] = gd->bd->bi_dram[1].size;
-
- fdt_fixup_memory_banks(blob, base, size, 2);
- ft_cpu_setup(blob, bd);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
- fdt_fixup_fman_ethernet(blob);
-#endif
-
- fdt_fixup_icid(blob);
-
- /*
- * qe-hdlc and usb multi-use the pins,
- * when set hwconfig to qe-hdlc, delete usb node.
- */
- if (hwconfig("qe-hdlc"))
-#ifdef CONFIG_HAS_FSL_XHCI_USB
- fdt_del_node_and_alias(blob, "usb1");
-#endif
- /*
- * qe just support qe-uart and qe-hdlc,
- * if qe-uart and qe-hdlc are not set in hwconfig,
- * delete qe node.
- */
- if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
- fdt_del_qe(blob);
-
- return 0;
-}
-
-u8 flash_read8(void *addr)
-{
- return __raw_readb(addr + 1);
-}
-
-void flash_write16(u16 val, void *addr)
-{
- u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
-
- __raw_writew(shftval, addr);
-}
-
-u16 flash_read16(void *addr)
-{
- u16 val = __raw_readw(addr);
-
- return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
-}
-
-#endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
deleted file mode 100644
index f072274f474..00000000000
--- a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#Configure Scratch register
-09570600 00000000
-09570604 10000000
-#Alt base register
-09570158 00001000
-#Disable CCI barrier tranaction
-09570178 0000e010
-09180000 00000008
-#USB PHY frequency sel
-09570418 0000009e
-0957041c 0000009e
-09570420 0000009e
-#flush PBI data
-096100c0 000fffff
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
deleted file mode 100644
index d87058b7efe..00000000000
--- a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# serdes protocol
-08100010 0a000000 00000000 00000000
-14550002 80004012 e0106000 c1002000
-00000000 00000000 00000000 00038800
-00000000 00001100 00000096 00000001
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
deleted file mode 100644
index e2ee34b7dfc..00000000000
--- a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# RCW
-08100010 0a000000 00000000 00000000
-14550002 80004012 60040000 c1002000
-00000000 00000000 00000000 00038800
-00000000 00001100 00000096 00000001
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
deleted file mode 100644
index 41df0b9fbfa..00000000000
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_SECURE_BOOT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
deleted file mode 100644
index 7541fad3db4..00000000000
--- a/configs/ls1043ardb_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x60100000
-CONFIG_FSL_LS_PPA=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_MISC_INIT_R=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
deleted file mode 100644
index 2879f45d564..00000000000
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
-CONFIG_NAND_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_CRYPTO_SUPPORT=y
-CONFIG_SPL_HASH_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
deleted file mode 100644
index 5a23e3cfff5..00000000000
--- a/configs/ls1043ardb_nand_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
-CONFIG_NAND_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
deleted file mode 100644
index 3c196944568..00000000000
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SECURE_BOOT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_MISC_INIT_R=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x110
-CONFIG_SPL_CRYPTO_SUPPORT=y
-CONFIG_SPL_HASH_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
deleted file mode 100644
index 144e48b885b..00000000000
--- a/configs/ls1043ardb_sdcard_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_LS1043ARDB=y
-CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
-CONFIG_SD_BOOT=y
-CONFIG_BOOTDELAY=10
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL_BOARD_INIT=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xf0
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_CACHE=y
-CONFIG_MP=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m at 0x100000(nor_bank0_uboot),40m at 0x1100000(nor_bank0_fit),7m(nor_bank0_user),2m at 0x4100000(nor_bank4_uboot),40m at 0x5100000(nor_bank4_fit),-(nor_bank4_user);7e800000.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)"
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_DM=y
-CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_E1000=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
deleted file mode 100644
index 54e6eef417b..00000000000
--- a/include/configs/ls1043ardb.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor
- */
-
-#ifndef __LS1043ARDB_H__
-#define __LS1043ARDB_H__
-
-#include "ls1043a_common.h"
-
-#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 100000000
-
-#define CONFIG_LAYERSCAPE_NS_ACCESS
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-/* Physical Memory Map */
-#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-
-#define CONFIG_SYS_SPD_BUS_NUM 0
-
-#ifndef CONFIG_SPL
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
-#define CONFIG_FSL_DDR_BIST
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
-#endif
-
-#ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
-#endif
-
-#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
-#endif
-
-#ifdef CONFIG_SD_BOOT
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
-#define CONFIG_CMD_SPL
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30
-#endif
-
-/*
- * NOR Flash Definitions
- */
-#define CONFIG_SYS_NOR_CSPR_EXT (0x0)
-#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_CSPR \
- (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
- CSPR_PORT_SIZE_16 | \
- CSPR_MSEL_NOR | \
- CSPR_V)
-
-/* NOR Flash Timing Params */
-#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
- CSOR_NOR_TRHZ_80)
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
- FTIM0_NOR_TEADC(0x1) | \
- FTIM0_NOR_TAVDS(0x0) | \
- FTIM0_NOR_TEAHC(0xc))
-#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
- FTIM1_NOR_TRAD_NOR(0xb) | \
- FTIM1_NOR_TSEQRAD_NOR(0x9))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
- FTIM2_NOR_TCH(0x4) | \
- FTIM2_NOR_TWPH(0x8) | \
- FTIM2_NOR_TWP(0x10))
-#define CONFIG_SYS_NOR_FTIM3 0
-#define CONFIG_SYS_IFC_CCR 0x01000000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
-
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_SYS_WRITE_SWAPPED_DATA
-
-/*
- * NAND Flash Definitions
- */
-#ifndef SPL_NO_IFC
-#define CONFIG_NAND_FSL_IFC
-#endif
-
-#define CONFIG_SYS_NAND_BASE 0x7e800000
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | CSPR_PORT_SIZE_8 \
- | CSPR_MSEL_NAND \
- | CSPR_V)
-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
- | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
- | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
- | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
- | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
- | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
- | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
-
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
- FTIM0_NAND_TWP(0x18) | \
- FTIM0_NAND_TWCHT(0x7) | \
- FTIM0_NAND_TWH(0xa))
-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
- FTIM1_NAND_TWBE(0x39) | \
- FTIM1_NAND_TRR(0xe) | \
- FTIM1_NAND_TRP(0x18))
-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
- FTIM2_NAND_TREH(0xa) | \
- FTIM2_NAND_TWHRE(0x1e))
-#define CONFIG_SYS_NAND_FTIM3 0x0
-
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-
-#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
-#endif
-
-/*
- * CPLD
- */
-#define CONFIG_SYS_CPLD_BASE 0x7fb00000
-#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
-
-#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
-#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
- CSPR_PORT_SIZE_8 | \
- CSPR_MSEL_GPCM | \
- CSPR_V)
-#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
- CSOR_NOR_NOR_MODE_AVD_NOR | \
- CSOR_NOR_TRHZ_80)
-
-/* CPLD Timing parameters for IFC GPCM */
-#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
- FTIM0_GPCM_TEADC(0xf) | \
- FTIM0_GPCM_TEAHC(0xf))
-#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
- FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
- FTIM2_GPCM_TCH(0xf) | \
- FTIM2_GPCM_TWP(0xff))
-#define CONFIG_SYS_CPLD_FTIM3 0x0
-
-/* IFC Timing Params */
-#ifdef CONFIG_NAND_BOOT
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
-
-#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#endif
-
-#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
-#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
-#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
-#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
-#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
-#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
-#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
-#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
-
-/* EEPROM */
-#ifndef SPL_NO_EEPROM
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#endif
-
-/*
- * Environment
- */
-#ifndef SPL_NO_ENV
-#define CONFIG_ENV_OVERWRITE
-#endif
-
-#if defined(CONFIG_NAND_BOOT)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
-#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x20000
-#endif
-
-/* FMan */
-#ifndef SPL_NO_FMAN
-#define AQR105_IRQ_MASK 0x40000000
-
-#ifdef CONFIG_NET
-#define CONFIG_PHY_VITESSE
-#define CONFIG_PHY_REALTEK
-#endif
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
-
-#define RGMII_PHY1_ADDR 0x1
-#define RGMII_PHY2_ADDR 0x2
-
-#define QSGMII_PORT1_PHY_ADDR 0x4
-#define QSGMII_PORT2_PHY_ADDR 0x5
-#define QSGMII_PORT3_PHY_ADDR 0x6
-#define QSGMII_PORT4_PHY_ADDR 0x7
-
-#define FM1_10GEC1_PHY_ADDR 0x1
-
-#define CONFIG_ETHPRIME "FM1@DTSEC3"
-#endif
-#endif
-
-/* SATA */
-#ifndef SPL_NO_SATA
-#ifndef CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT2
-#endif
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
-#define CONFIG_SYS_SCSI_MAX_LUN 2
-#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
- CONFIG_SYS_SCSI_MAX_LUN)
-#define SCSI_VEND_ID 0x1b4b
-#define SCSI_DEV_ID 0x9170
-#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
-#endif
-
-#include <asm/fsl_secure_boot.h>
-
-#endif /* __LS1043ARDB_H__ */
--
2.19.1.1215.g8438c0b245-goog