From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09020C433EF for ; Mon, 20 Sep 2021 05:44:17 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F210960F70 for ; Mon, 20 Sep 2021 05:44:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org F210960F70 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 66BEF81E1C; Mon, 20 Sep 2021 07:44:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1632116653; bh=iWnFp0qyOYTapNqgKbz72bI7GMUoRAxt1qtMu1jeeJI=; h=Subject:To:Cc:References:From:Date:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=c/g5U1eeMHEhmY+14yiDpJGgVBqQXkpDMjxYYEBgxvFa8/VXYLcQZtp4LcpT56286 S0oCVBMJvvj9sTfMtCXcwT7YB1QZ5/lPiB2sa4SOvPLt9GjezSW7/owRPhp9jVFp8v oBSDnvCXEnOPAbBomYEJ5hMZdIjd3n4C0dBnPjE5aCJySZzeRG2U1BJPHx1KFZJAfy 4mw3iKBVeyn0yMzETiaGaUreXW0LMVfK7ArRjrjiRkhMYfns+xU8G62I/mu1vfSCtz 9iEEenpD1iiIvt3+P7VqfOjq8YWSaEO/RKWaQKik2Itcp3ISUdkBek4zXCMDSR/Pyl 8ciC9NJddQ6ow== Received: by phobos.denx.de (Postfix, from userid 109) id 0C5568290A; Mon, 20 Sep 2021 07:44:11 +0200 (CEST) Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [91.198.250.253]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0BE37811F7 for ; Mon, 20 Sep 2021 07:44:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp102.mailbox.org (smtp102.mailbox.org [80.241.60.233]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4HCYQb6hkJzQjx3; Mon, 20 Sep 2021 07:44:07 +0200 (CEST) Subject: Re: [PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges To: =?UTF-8?Q?Pali_Roh=c3=a1r?= , Simon Glass , Phil Sutter Cc: u-boot@lists.denx.de, Bin Meng References: <20210910113335.8283-1-pali@kernel.org> From: Stefan Roese Message-ID: <5ef73d52-cda4-a237-ec25-72035fb3bbfb@denx.de> Date: Mon, 20 Sep 2021 07:44:03 +0200 MIME-Version: 1.0 In-Reply-To: <20210910113335.8283-1-pali@kernel.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: de-DE Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 1A05C26E X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Added Bin to cc. On 10.09.21 13:33, Pali Rohár wrote: > Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved > and should be zero. So do not set them to non-zero value. > > Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers > contain information if 64-bit memory addressing is supported. So preserve > this information when overwriting these registers. > > Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information > if 32-bit io addressing is supported. So preserve this information and do > not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and > PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. > > Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Thanks, Stefan > --- > drivers/pci/pci_auto.c | 39 +++++++++++++++++++++++++++++---------- > 1 file changed, 29 insertions(+), 10 deletions(-) > > diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c > index b128a05dd380..7b6e629cae70 100644 > --- a/drivers/pci/pci_auto.c > +++ b/drivers/pci/pci_auto.c > @@ -165,6 +165,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) > struct pci_region *pci_prefetch; > struct pci_region *pci_io; > u16 cmdstat, prefechable_64; > + u8 io_32; > struct udevice *ctlr = pci_get_controller(dev); > struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); > > @@ -175,6 +176,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) > dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); > dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); > prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; > + dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32); > + io_32 &= PCI_IO_RANGE_TYPE_MASK; > > /* Configure bus number registers */ > dm_pci_write_config8(dev, PCI_PRIMARY_BUS, > @@ -191,7 +194,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) > * I/O space > */ > dm_pci_write_config16(dev, PCI_MEMORY_BASE, > - (pci_mem->bus_lower & 0xfff00000) >> 16); > + ((pci_mem->bus_lower & 0xfff00000) >> 16) & > + PCI_MEMORY_RANGE_MASK); > > cmdstat |= PCI_COMMAND_MEMORY; > } > @@ -205,7 +209,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) > * I/O space > */ > dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, > - (pci_prefetch->bus_lower & 0xfff00000) >> 16); > + (((pci_prefetch->bus_lower & 0xfff00000) >> 16) & > + PCI_PREF_RANGE_MASK) | prefechable_64); > if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) > #ifdef CONFIG_SYS_PCI_64BIT > dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, > @@ -217,8 +222,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) > cmdstat |= PCI_COMMAND_MEMORY; > } else { > /* We don't support prefetchable memory for now, so disable */ > - dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000); > - dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0); > + dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 | > + prefechable_64); > + dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 | > + prefechable_64); > if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { > dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); > dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); > @@ -230,8 +237,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) > pciauto_region_align(pci_io, 0x1000); > > dm_pci_write_config8(dev, PCI_IO_BASE, > - (pci_io->bus_lower & 0x0000f000) >> 8); > - dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, > + (((pci_io->bus_lower & 0x0000f000) >> 8) & > + PCI_IO_RANGE_MASK) | io_32); > + if (io_32 == PCI_IO_RANGE_TYPE_32) > + dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, > (pci_io->bus_lower & 0xffff0000) >> 16); > > cmdstat |= PCI_COMMAND_IO; > @@ -261,7 +270,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) > pciauto_region_align(pci_mem, 0x100000); > > dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, > - (pci_mem->bus_lower - 1) >> 16); > + ((pci_mem->bus_lower - 1) >> 16) & > + PCI_MEMORY_RANGE_MASK); > } > > if (pci_prefetch) { > @@ -275,7 +285,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) > pciauto_region_align(pci_prefetch, 0x100000); > > dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, > - (pci_prefetch->bus_lower - 1) >> 16); > + (((pci_prefetch->bus_lower - 1) >> 16) & > + PCI_PREF_RANGE_MASK) | prefechable_64); > if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) > #ifdef CONFIG_SYS_PCI_64BIT > dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, > @@ -286,12 +297,20 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) > } > > if (pci_io) { > + u8 io_32; > + > + dm_pci_read_config8(dev, PCI_IO_LIMIT, > + &io_32); > + io_32 &= PCI_IO_RANGE_TYPE_MASK; > + > /* Round I/O allocator to 4KB boundary */ > pciauto_region_align(pci_io, 0x1000); > > dm_pci_write_config8(dev, PCI_IO_LIMIT, > - ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); > - dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, > + ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) & > + PCI_IO_RANGE_MASK) | io_32); > + if (io_32 == PCI_IO_RANGE_TYPE_32) > + dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, > ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); > } > } > Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de