[U-Boot] [PATCH 1/2] mx5: Add default pin initializers

["Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>]

Dear Matt Sealey,

> On Tue, Aug 14, 2012 at 10:46 AM, Beno?t Th?baudeau
> <benoit.thebaudeau@advansee.com> wrote:
> > Create default pin initialization functions for the default iomux
> > function
> > assignments of the main peripherals.
> >
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > Cc: Stefano Babic <sbabic@denx.de>
> > ---
> >  .../arch/arm/cpu/armv7/mx5/soc.c                   |  139
> >  ++++++++++++++++++++
> >  .../arch/arm/include/asm/arch-mx5/sys_proto.h      |    5 +
> >  2 files changed, 144 insertions(+)
> >
> > diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c
> > u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
> > index 3f5a4f7..ee19b54 100644
> > --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c
> > +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
> > @@ -25,6 +25,8 @@
> >
> >  #include <common.h>
> >  #include <asm/arch/imx-regs.h>
> > +#include <asm/arch/mx5x_pins.h>
> > +#include <asm/arch/iomux.h>
> >  #include <asm/arch/clock.h>
> >  #include <asm/arch/sys_proto.h>
> >
> > @@ -71,6 +73,143 @@ u32 get_cpu_rev(void)
> >         return system_rev;
> >  }
> >
> > +#ifdef CONFIG_MXC_UART
> > +#if CONFIG_MXC_UART_BASE == UART1_BASE
> > +#ifdef CONFIG_MX51
> > +void mx51_uart1_init_pins(void)
> > +{
> > +       int in_pad, out_pad;
> > +
> > +       /* Set up pins for UART1. */
> > +       mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> > +       mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> > +       mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> > +       mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> > +
> > +
> >       mxc_iomux_set_input(MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
> > +                           INPUT_CTL_PATH0);
> > +       mxc_iomux_set_input(MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
> > +                           INPUT_CTL_PATH0);
> > +
> > +       in_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> > PAD_CTL_PUE_PULL |
> > +               PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
> > +               PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW;
> > +       out_pad = PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE |
> > +               PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
> > +               PAD_CTL_SRE_SLOW;
> 
> If we're nitpicking - none of the UART1_* pads on MX51 have valid ODE
> bits, it's a reserved area.

I know that.

> Even though you're setting it to 0 here,

Indeed.

> including it in the pad settings is bad behavior.

No, it's here to emphasize the pad settings that are used. Moreover, in some
cases, the same pad value is used for several pads that do not all have the same
bits available or not, so that wouldn't make sense to have the same pad setting
written in many different ways only because of that.

This kind of thing will also very likely occur in your new iomux-mx51.h.

Best regards,
Beno?t