[PATCH] rockchip: px30: Change RK809 PMIC interrupt polarity

[PATCH] rockchip: px30: Change RK809 PMIC interrupt polarity

[Miquel Raynal]

PMIC interrupt can be active high or active low depending on BIT(1) of
the GPIO_INT_CFG pin. The default is 0x1, which means active
high. Change the polarity in the device tree to reflect the default
state.

This change does not impact U-Boot directly as there are no interrupts
at this stage but it keeps the device tree synced with Linux.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 arch/arm/dts/px30-evb.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/px30-evb.dts b/arch/arm/dts/px30-evb.dts
index 53ab8bc7db..b1a4f72152 100644
--- a/arch/arm/dts/px30-evb.dts
+++ b/arch/arm/dts/px30-evb.dts
@@ -179,7 +179,7 @@
 		compatible = "rockchip,rk809";
 		reg = <0x20>;
 		interrupt-parent = <&gpio0>;
-		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pmic_int>;
 		rockchip,system-power-controller;
-- 
2.20.1

[PATCH] rockchip: px30: Change RK809 PMIC interrupt polarity

[Heiko Stuebner]

Am Freitag, 6. Dezember 2019, 16:46:29 CET schrieb Miquel Raynal:
> PMIC interrupt can be active high or active low depending on BIT(1) of
> the GPIO_INT_CFG pin. The default is 0x1, which means active
> high. Change the polarity in the device tree to reflect the default
> state.
> 
> This change does not impact U-Boot directly as there are no interrupts
> at this stage but it keeps the device tree synced with Linux.
> 
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

just for reference so this doesn't get applied by accident, in the kernel
we changed the register-programmed interrupt polarity to low,
so that this is in line with all other rk8xx pmics, so don't need to change
the devicetree in the kernel or in uboot.


Heiko