From: "Maniyam, Dinesh via U-Boot" <u-boot@lists.u-boot-project.org>
To: "Chee, Tien Fong" <tien.fong.chee@altera.com>, u-boot@lists.denx.de
Cc: Marek Vasut <marex@denx.de>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Tom Rini <trini@konsulko.com>,
Michal Simek <michal.simek@amd.com>,
Kok Kiang <kok.kiang.hea@altera.com>,
Boon Khai <boon.khai.ng@altera.com>,
Alif <alif.zakuan.yuslaimi@altera.com>,
Tien Fong Chee <tien.fong.chee@intel.com>
Subject: Re: [PATCH] arm: socfpga: Reset MPFE NoC after programming peripheral / combined RBF
Date: Wed, 29 Jul 2026 13:53:22 +0800 [thread overview]
Message-ID: <615f70f8-e41c-4b53-952c-e04effbebf4d@altera.com> (raw)
In-Reply-To: <4d496d68-a6ca-4ff0-a463-aeaca0febf3a@altera.com>
Hi Tien Fong,
On 17/4/2026 4:42 pm, Chee, Tien Fong wrote:
> Hi Dinesh,
>
>
> On 25/3/2026 1:46 pm, dinesh.maniyam@altera.com wrote:
>> From: Dinesh Maniyam <dinesh.maniyam@altera.com>
>>
>> This patch triggers warm reset to recover the MPFE NoC from corruption
>> due to high frequency transient clock output from HPS EMIF IOPLL at
>> VCO startup after peripheral RBF is programmed.
>>
>
> As described in the commit message is not acceptable until the
> warm-reset / NoC recovery logic appears in the
>
> series or the message is narrowed to “add SYSMGR ROM-code offset
> definitions for …”.
>
>
>>
>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
>> ---
>> arch/arm/mach-socfpga/include/mach/system_manager_arria10.h | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
>> index 0afe63e647e..73e953465a4 100644
>> --- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
>> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
>> @@ -37,6 +37,10 @@
>> #define SYSMGR_A10_ISW_HANDOFF_BASE 0x230
>> #define SYSMGR_A10_ISW_HANDOFF_7 0x1c
>>
>> +#define SYSMGR_A10_ROMCODE_CTRL 0x204
>> +#define SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND 0x208
>> +#define SYSMGR_A10_ISW_HANDOFF 0x230
>
>
> Redundant offset / naming: SYSMGR_A10_ISW_HANDOFF is 0x230, the same
> value as SYSMGR_A10_ISW_HANDOFF_BASE
>
>> +
>> #define SYSMGR_SDMMC SYSMGR_A10_SDMMC
>>
>> #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
Confirmed against current master -- SYSMGR_A10_ROMCODE_CTRL and
SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND already exist, and the warm-reset /
MPFE-NoC-recovery sequence this was meant to add is already implemented
in spl_a10.c (the "MPFE hang workaround" block, gated on
is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode(), which already
covers both peripheral and combined RBF). Withdrawing this one --
nothing left to add.
We can drop the patch!
Regards,
Dinesh
prev parent reply other threads:[~2026-07-29 5:53 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-25 5:46 [PATCH] arm: socfpga: Reset MPFE NoC after programming peripheral / combined RBF dinesh.maniyam
2026-04-17 8:42 ` Chee, Tien Fong
2026-07-29 5:53 ` Maniyam, Dinesh via U-Boot [this message]
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