From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ajay Bhargav <ajay.bhargav@einfochips.com>
Date: Mon, 19 Sep 2011 16:16:17 +0530 (IST)
Subject: [U-Boot] [PATCH 1/4] SPI: Add SPI driver support for Marvell
 Armada100
In-Reply-To: <201109191255.47759.marek.vasut@gmail.com>
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----- "Marek Vasut" <marek.vasut@gmail.com> wrote:

> On Monday, September 19, 2011 12:47:07 PM Ajay Bhargav wrote:
> > This patch provides support for SPI emulated over SSP for Marvell
> > Armada100 SOC.
> > 
> > Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
> > ---
> >  arch/arm/include/asm/arch-armada100/spi.h |  111 ++++++++++++++++
> >  drivers/spi/Makefile                      |    1 +
> >  drivers/spi/armada100_spi.c               |  205
> > +++++++++++++++++++++++++++++ 3 files changed, 317 insertions(+), 0
> > deletions(-)
> >  create mode 100644 arch/arm/include/asm/arch-armada100/spi.h
> >  create mode 100644 drivers/spi/armada100_spi.c
> > 
> 
> [...]
> 
> > +
> > +#define SSCR1_TXTRESH(x)	((x - 1) << 6)	/* level [1..16] */
> > +#define SSCR1_RXTRESH(x)	((x - 1) << 10)	/* level [1..16] */
> 
> ((x) - 1), missing parenthesis, please fix globally.
> 
> > +#define SSCR1_TINTE		(1 << 19)	/* Receiver Time-out
> > +						   Interrupt enable */
> > +
> > +#define SSCR0_DSS		0x0f		/* Data Size Select (mask) */
> > +#define SSCR0_DATASIZE(x)	(x - 1)		/* Data Size Select [4..16] */
> > +#define SSCR0_FRF		0x30		/* FRame Format (mask) */
> > +#define SSCR0_MOTO		(0x0 << 4)	/* Motorola's Serial
> > +						   Peripheral Interface */
> > +#define SSCR0_TI		(0x1 << 4)	/* TI's Synchronous
> > +						   Serial Protocol (SSP) */
> > +#define SSCR0_NATIONAL		(0x2 << 4)	/* National Microwire */
> > +#define SSCR0_ECS		(1 << 6)	/* External clock select */
> > +#define SSCR0_SSE		(1 << 7)	/* Synchronous Serial Port
> > +						   Enable */
> > +
> > +#define SSSR_TNF	(1 << 2)	/* Transmit FIFO Not Full */
> > +#define SSSR_RNE	(1 << 3)	/* Receive FIFO Not Empty */
> > +#define SSSR_BSY	(1 << 4)	/* SSP Busy */
> > +#define SSSR_TFS	(1 << 5)	/* Transmit FIFO Service Request */
> > +#define SSSR_RFS	(1 << 6)	/* Receive FIFO Service Request */
> > +#define SSSR_ROR	(1 << 7)	/* Receive FIFO Overrun */
> > +#define SSSR_TINT	(1 << 19)	/* Receiver Time-out Interrupt */
> 
> [...]
> 
> > +
> > +static void null_writer(struct armd_spi_slave *pss)
> > +{
> > +	while (!(readl(&pss->spi_reg->sssr) & SSSR_TNF))
> > +		;
> 
> Please avoid endless loops, please fix globally.
> 
> 
> Cheers
> 
Hi Marek,

I will fix that :) any more comments?

Regards,
Ajay Bhargav