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[173.73.95.180]) by smtp.gmail.com with ESMTPSA id cb15-20020a05622a1f8f00b003ab43dabfb1sm9717824qtb.55.2023.01.21.13.56.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 21 Jan 2023 13:56:55 -0800 (PST) Message-ID: <6363344f-1448-ddf6-9459-94a1b44e27d3@gmail.com> Date: Sat, 21 Jan 2023 16:56:54 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v2 00/17] Basic StarFive JH7110 RISC-V SoC support Content-Language: en-US To: Conor Dooley , Yanhong Wang Cc: u-boot@lists.denx.de, Rick Chen , Leo , Lukasz Majewski , Lee Kuan Lim , Jianlong Huang , Emil Renner Berthing References: <20230118081132.31403-1-yanhong.wang@starfivetech.com> From: Sean Anderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 1/21/23 16:36, Conor Dooley wrote: > On Wed, Jan 18, 2023 at 04:11:15PM +0800, Yanhong Wang wrote: >> This series of patches base on the latest branch/master, and add support >> for the StarFive JH7110 RISC-V SoC and VisionFive V2 board. In order for >> this to be achieved, the respective DT nodes have been added, and the >> required defconfigs have been added to the boards' defconfig. What is more, >> the basic required DM drivers have been added, such as reset, clock, pinctrl, >> uart, ram etc. >> >> Note that the register base address of reset controller is same with the >> clock controller. Therefore, there is no device tree node alone for reset >> driver. It binds device node in the clock driver. >> >> The u-boot-spl and u-boot has been tested on the VisionFive V2 boards which >> equip with JH7110 SoC and works normally. >> >> For more information and support, you can visit RVspace wiki[1]. >> >> [1] https://wiki.rvspace.org/ >> >> Changes in v2: >> - Renamed file 'jh7110-regs.h' to 'regs.h'. >> - Reworded the clear L2 LIM memory code in C. >> - Removed flash init call in 'spl_soc_init' function. >> - Reworded the clock driver. >> - Rename the macro 'SET_DIV' to 'ASSIGNED_CLOCK_PARENTS' in 'spl.c'. >> - Moved the device tree node 'dmc@15700000' from 'jh7110-u-boot.dtsi' to >> 'starfive_visionfive2-u-boot.dtsi'. >> >> Previous versions: >> v1 - https://patchwork.ozlabs.org/project/uboot/cover/20221212025020.23778-1-yanhong.wang@starfivetech.com/ >> >> Jianlong Huang (1): >> dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions >> >> Kuan Lim Lee (1): >> pinctrl: starfive: Add StarFive JH7110 driver >> >> Yanhong Wang (15): >> riscv: cpu: jh7110: Add support for jh7110 SoC >> cache: starfive: Add StarFive JH7110 support >> dt-bindings: reset: Add StarFive JH7110 reset definitions >> reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC >> dt-bindings: clock: Add StarFive JH7110 clock definitions >> clk: starfive: Add StarFive JH7110 clock driver >> ram: starfive: add ddr driver >> board: starfive: add StarFive VisionFive v2 board support >> riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC >> board: starfive: Add Kconfig for StarFive VisionFive v2 Board >> board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig >> riscv: dts: jh7110: Add initial StarFive JH7110 device tree >> riscv: dts: jh7110: Add initial u-boot device tree >> riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device >> tree >> configs: starfive: add starfive_visionfive2_defconfig > > Apologies if I have missed it somewhere - but where is patch 12? > I don't see it on lore.kernel.org nor in my inbox :( > > Thanks, > Conor. > https://lore.kernel.org/all/20230118082907.31629-1-yanhong.wang@starfivetech.com/ Not sure why it isn't with the rest of the series. --Sean