From mboxrd@z Thu Jan  1 00:00:00 1970
From: Kumar Gala <kumar.gala@freescale.com>
Date: Tue, 18 Jan 2005 11:14:27 -0600
Subject: [U-Boot-Users] MPC8540 DataTLBError
In-Reply-To: <20050118161351.98630.qmail@web41407.mail.yahoo.com>
References: <20050118161351.98630.qmail@web41407.mail.yahoo.com>
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To: u-boot@lists.denx.de

It looks like you are actually showing me the 2nd fault.  The address 
that is causing the fault (0xfff81410) is the DataTLBError handler, 
however I dont know how you got into this handler.  That is the root of 
your problem.  If you can send your include/configs/"BOARD.h" for you 
board that would be helpful.

Are you enabling CONFIG_SPD_EEPROM?  If not that might be causing 
issues for you.  You have to make sure that CFG_INIT_RAM_ADDR is both 
16k aligned and is at a physical address that does not contain 
anything.

Anyways, I think the easiest next step is to see how you have your 
"BOARD.h" file setup.  It would also be helpful to understand exactly 
where you think you are having issues in the code path.  Your initial 
email was a bit vague.

- kumar

On Jan 18, 2005, at 10:13 AM, Jeff Stevens wrote:

> I read out the registers you were talking about:
>
> DEAR: 0x000211a8
>  SSR0: 0xfff81410
>  SRR1: 0x00000000
>  ESR : 0x00800000
>  MAS0: 0x00000001
>  MAS1: 0x80000000
>  MAS2: 0x00021000
>  MAS3: 0x00000000
>  MAS4: 0x00000000
>  MAS6: 0x00000000
>
> TLB0 Entries:
>  ? 0 : 00 ff700000?? 4KB V? 0 -> ff700000? 0000 -I-G-
>  ---RWX
>  ?16 : 00 e4010000?? 4KB V? 0 -> e4010000? 0000 -I-G-
>  ---RWX
>  ?17 : 00 e4011000?? 4KB V? 0 -> e4011000? 0000 -I-G-
>  ---RWX
>  ?18 : 00 e4012000?? 4KB V? 0 -> e4012000? 0000 -I-G-
>  ---RWX
>  ?19 : 00 e4013000?? 4KB V? 0 -> e4013000? 0000 -I-G-
>  ---RWX
>
>
>
> TLB1 Entries:
>  ? 0 : 00 fc000000? 64MB V? 0 -> fc000000? 0000 -I-G-
>  ---RWX
>  ? 1 : 00 f8000000? 64MB V? 0 -> f8000000? 0000 -I-G-
>  ---RWX
>  ? 2 : 00 80000000 256MB V? 0 -> 80000000? 0000 -I-G-
>  ---RWX
>  ? 3 : 00 90000000 256MB V? 0 -> 90000000? 0000 -I-G-
>  ---RWX
>  ? 4 : 00 c0000000 256MB V? 0 -> c0000000? 0000 -I-G-
>  ---RWX
>  ? 5 : 00 d0000000 256MB V? 0 -> d0000000? 0000 -I-G-
>  ---RWX
>  ? 6 : 00 e0000000? 64MB V? 0 -> e0000000? 0000 -I-G-
>  ---RWX
>  ? 7 : 00 00000000 256MB -? 0 -> 00000000? 0000 -----
>  ---RWX
>  ? 8 : 00 00000000?? 1KB -? 0 -> 00000000? 0000 --M-E
>  ------
>  ? 9 : f5 bf7ef000?? 4MB -? 1 -> fe7fe000? 1111 WIMGE
>  RWXRWX
>  ?10 : 7b ffff7000?? 4GB -? 1 -> fffff000? 1111 WIMGE
>  RWXR-X
>  ?11 : 7f feffb000 256GB -? 1 -> fefff000? 1111 WIMG-
>  RWXRW-
>  ?12 : fe bdfbf000?? 1TB -? 1 -> fff7f000? 1111 WIMGE
>  RWXRWX
>  ?13 : ff fffff000?? 1TB -? 1 -> f7fee000? 1111 WIMG-
>  RWXRWX
>  ?14 : ff ffe7f000?? 4GB -? 1 -> fdbdd000? 1111 WIMGE
>  RWXRWX
>  ?15 : ff fffff000?? 1TB -? 1 -> fffff000? 1111 WIMGE
>  RWXRWX
>
> I don't understand why I'm getting this TLB Data
>  Error.? Any help would be greatly appreciated, as I am
>  stuck, and don't know what else to try.? I have tried
>  using all TLB1 entries, and have moved
>  CFG_INIT_RAM_ADDR to 0x40000000, but nothing seems to
>  help.? What am I missing?
>
> Thanks,
>  ?? Jeff Stevens
>
>
>
> --- Kumar Gala <kumar.gala@freescale.com> wrote:
>
> > Jeff,
>  >
> > 1. You should never take a DTLBError in u-boot, so
>  > one would think
> > there is an issue in your tlb setup
>  > 2. Can you get the value of DEAR out, this will help
>  > know what address
> > is being accessed that is causing the fault (SRR0,
>  > SRR1, and ESR) are
> > also useful.
>  > 3. I would expect a patch form 6/17 to be in the
>  > mainline, however
> > without a specific reference its very difficult to
>  > know
>  >
> > - kumar
>  >
> > On Jan 14, 2005, at 3:02 PM, Jeff Stevens wrote:
> >
> > > I have a custom board with an MPC8540 processor.
>  > > U-Boot always ends up at 0xfff81400
>  > (DataTLBError).? I
>  > >? traced it through and found that the first time
>  > it
>  > >? enters DataTLBError is at the end of _start (in
>  > >? cpu/mpc85xx/start.S) in the loop (1:) where it is
>  > >? allocating the Initial RAM in data cache.? I
>  > traped
>  > >? the CPU before that loop and then I placed an
>  > infinite
>  > >? loop right after that loop and it never gets
>  > there.? I
>  > >? then traced back into _start right after that
>  > loop and
>  > >? told it to run again, and it went back into
>  > > DataTLBError at a later point in the code.? So is
>  > this
>  > >? a problem with my tlb1_entry table?? I also read
>  > >? online that there was a patch submitted on
>  > 6/17/2004
>  > >? to fix this, do I need this?? I updated my U-Boot
>  > >? development tree today over CVS.? Is that patch
>  > >? already in there?? Any help would be greatly
>  > >? appreciated.? Here is my tbl1_entry.? All I did
>  > was
>  > >? alter the MPC8540ADS init.S file to get mine (I
>  > don't
>  > >? have any BCSRs or SDRAM on the LBC).
>  > >
>  > >
>  > >
>  > >
>  > >
>  > > tlb1_entry:
> > >????????? entry_start
>  > >
>  > >???????? /*
>  > >?????????? * Number of TLB0 and TLB1 entries in the
>  > following
>  > > table
>  > >?????????? */
>  > >????????? .long 12
>  > >
>  > > #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
> > >???????? /*
>  > >?????????? * TLB0??????????? 4K?? Non-cacheable,
>  > guarded
>  > >?????????? * 0xff700000?? 4K????? Initial CCSRBAR
>  > mapping
>  > >?????????? *
>  > >?????????? * This ends up at a TLB0 Index==0 entry,
>  > and must
>  > >? not collide
> > >?????????? * with other TLB0 Entries.
>  > >?????????? */
>  > >????????? .long TLB1_MAS0(0, 0, 0)
>  > >????????? .long TLB1_MAS1(1, 0, 0, 0, 0)
>  > >????????? .long
> > TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT),
> > > 0,0,0,0,1,0,1,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT),
> > > 0,0,0,0,0,1,0,1,0,1)
> > > #else
>  > >? #error("Update the number of table entries in
> > > tlb1_entry")
>  > >? #endif
>  > >
>  > >???????? /*
>  > >?????????? * TLB0???????? 16K???? Cacheable,
>  > non-guarded
> > >?????????? * 0xd001_0000? 16K???? Temporary Global
>  > data for
>  > > initialization
>  > >?????????? *
>  > >?????????? * Use four 4K TLB0 entries.? These
>  > entries must be
>  > >? cacheable
> > >?????????? * as they provide the bootstrap memory
>  > before the
>  > >? memory
>  > >?????????? * controler and real memory have been
>  > configured.
>  > >?????????? *
>  > >?????????? * These entries end up at TLB0 Indicies
>  > 0x10, 0x14,
>  > >? 0x18 and 0x1c,
>  > >?????????? * and must not collide with other TLB0
>  > entries.
>  > >?????????? */
>  > >????????? .long TLB1_MAS0(0, 0, 0)
>  > >????????? .long TLB1_MAS1(1, 0, 0, 0, 0)
>  > >????????? .long
> > TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
> > > 0,0,0,0,0,0,0,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
> > > 0,0,0,0,0,1,0,1,0,1)
> > >
>  > >???????? .long TLB1_MAS0(0, 0, 0)
>  > >????????? .long TLB1_MAS1(1, 0, 0, 0, 0)
>  > >????????? .long
> > TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 *
>  > >? 1024), 0,0,0,0,0,0,0,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 *
>  > >? 1024), 0,0,0,0,0,1,0,1,0,1)
> > >
>  > >???????? .long TLB1_MAS0(0, 0, 0)
>  > >????????? .long TLB1_MAS1(1, 0, 0, 0, 0)
>  > >????????? .long
> > TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 *
>  > >? 1024), 0,0,0,0,0,0,0,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 *
>  > >? 1024), 0,0,0,0,0,1,0,1,0,1)
> > >
>  > >???????? .long TLB1_MAS0(0, 0, 0)
>  > >????????? .long TLB1_MAS1(1, 0, 0, 0, 0)
>  > >????????? .long
> > TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 *
>  > >? 1024), 0,0,0,0,0,0,0,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 *
>  > >? 1024), 0,0,0,0,0,1,0,1,0,1)
> > >
>  > >
>  > >
>  > >???????? /*
>  > >?????????? * TLB 0:????? 64M????? Non-cacheable,
>  > guarded
>  > >?????????? * 0xfc000000?? 64M???? FLASH (First
>  > Half)
>  > >?????????? * Out of reset this entry is only 4K.
>  > >?????????? */
>  > >????????? .long TLB1_MAS0(1, 0, 0)
>  > >????????? .long TLB1_MAS1(1, 1, 0, 0,
>  > BOOKE_PAGESZ_64M)
> > >???????? .long
>  > TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE),
> > > 0,0,0,0,1,0,1,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE),
> > > 0,0,0,0,0,1,0,1,0,1)
> > >
>  > >???????? /*
>  > >?????????? * TLB 1:????? 64M????? Non-cacheable,
>  > guarded
>  > >?????????? * 0xf8000000?? 64M???? FLASH (Second
>  > Half)
>  > >?????????? */
>  > >????????? .long TLB1_MAS0(1, 1, 0)
>  > >????????? .long TLB1_MAS1(1, 1, 0, 0,
>  > BOOKE_PAGESZ_64M)
> > >???????? .long
>  > TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE +
>  > >? 0x04000000), 0,0,0,0,1,0,1,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE +
>  > >? 0x04000000), 0,0,0,0,0,1,0,1,0,1)
> > >
>  > >???????? /*
>  > >?????????? * TLB 2:?????? 256M??? Non-cacheable,
>  > guarded
>  > >?????????? * 0x80000000?? 256M??? PCI1 MEM First
>  > half
>  > >?????????? */
>  > >????????? .long TLB1_MAS0(1, 2, 0)
>  > >????????? .long TLB1_MAS1(1, 1, 0, 0,
>  > BOOKE_PAGESZ_256M)
> > >???????? .long
>  > TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE),
> > > 0,0,0,0,1,0,1,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE),
> > > 0,0,0,0,0,1,0,1,0,1)
> > >
>  > >???????? /*
>  > >?????????? * TLB 3:?????? 256M??? Non-cacheable,
>  > guarded
>  > >?????????? * 0x90000000?? 256M??? PCI1 MEM Second
>  > half
>  > >?????????? */
>  > >????????? .long TLB1_MAS0(1, 3, 0)
>  > >????????? .long TLB1_MAS1(1, 1, 0, 0,
>  > BOOKE_PAGESZ_256M)
> > >???????? .long
>  > TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE +
>  > >? 0x10000000), 0,0,0,0,1,0,1,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE +
>  > >? 0x10000000), 0,0,0,0,0,1,0,1,0,1)
> > >
>  > >???????? /*
>  > >?????????? * TLB 4:?????? 256M??? Non-cacheable,
>  > guarded
>  > >?????????? * 0xc0000000?? 256M??? Rapid IO MEM
>  > First half
>  > >?????????? */
>  > >????????? .long TLB1_MAS0(1, 4, 0)
>  > >????????? .long TLB1_MAS1(1, 1, 0, 0,
>  > BOOKE_PAGESZ_256M)
> > >???????? .long
>  > TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE),
> > > 0,0,0,0,1,0,1,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE),
> > > 0,0,0,0,0,1,0,1,0,1)
> > >
>  > >???????? /*
>  > >?????????? * TLB 5:?????? 256M??? Non-cacheable,
>  > guarded
>  > >?????????? * 0xd0000000?? 256M??? Rapid IO MEM
>  > Second half
>  > >?????????? */
>  > >????????? .long TLB1_MAS0(1, 5, 0)
>  > >????????? .long TLB1_MAS1(1, 1, 0, 0,
>  > BOOKE_PAGESZ_256M)
> > >???????? .long
>  > TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE +
>  > >? 0x10000000), 0,0,0,0,1,0,1,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE +
>  > >? 0x10000000), 0,0,0,0,0,1,0,1,0,1)
> > >
>  > >???????? /*
>  > >?????????? * TLB 6:?????? 64M???? Non-cacheable,
>  > guarded
>  > >?????????? * 0xe000_0000? 1M????? CCSRBAR
>  > >?????????? * 0xe200_0000? 16M???? PCI1 IO
>  > >?????????? */
>  > >????????? .long TLB1_MAS0(1, 6, 0)
>  > >????????? .long TLB1_MAS1(1, 1, 0, 0,
>  > BOOKE_PAGESZ_64M)
> > >???????? .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR),
> > > 0,0,0,0,1,0,1,0)
> > >???????? .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR),
> > > 0,0,0,0,0,1,0,1,0,1)
> > >
>  > > #if !defined(CONFIG_SPD_EEPROM)
> > >???????? /*
>  > >?????????? * TLB 7:????????? 256M DDR
>  > >?????????? * 0x00000000?? 256M??? DDR System memory
>  > >?????????? * Without SPD EEPROM configured DDR,
>  > this must be
>  > >? setup manually.
>  > >?????????? * Make sure the TLB count at the top of
>  > this table
>  > >? is correct.
>  > >?????????? * Likely it needs to be increased by two
>  > for these
>  > >? entries.
>  > >?????????? */
>  > >? #error("Update the number of table entries in
> > > tlb1_entry")
>  > >????????? .long TLB1_MAS0(1, 8, 0)
>  > >????????? .long TLB1_MAS1(1, 1, 0, 0,
>  > BOOKE_PAGESZ_256M)
> > >???????? .long
>  > TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE),
> > > 0,0,0,0,0,0,0,0)
> > >???????? .long
>  > TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE),
> > > 0,0,0,0,0,1,0,1,0,1)
> > > #endif
>  > >
>  > >???????? entry_end
>  > >
>  > >
>  > >
>  > >
>  > >
>  > >???????????????
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