From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= Date: Mon, 5 Nov 2012 21:11:49 +0100 (CET) Subject: [U-Boot] [PATCH 07/13] ehci-mx5: Add missing OC_DIS for i.MX53 In-Reply-To: <412111025.587245.1352146184216.JavaMail.root@advansee.com> Message-ID: <686807652.587343.1352146309448.JavaMail.root@advansee.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin. Signed-off-by: Beno?t Th?baudeau Cc: Marek Vasut Cc: Stefano Babic --- .../drivers/usb/host/ehci-mx5.c | 25 ++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c index 8e42e56..7da1398 100644 --- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c +++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c @@ -32,12 +32,14 @@ #define MXC_OTG_OFFSET 0 #define MXC_H1_OFFSET 0x200 #define MXC_H2_OFFSET 0x400 +#define MXC_H3_OFFSET 0x600 #define MXC_USBCTRL_OFFSET 0 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc #define MXC_USB_CTRL_1_OFFSET 0x10 #define MXC_USBH2CTRL_OFFSET 0x14 +#define MXC_USBH3CTRL_OFFSET 0x18 /* USB_CTRL */ #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ @@ -51,10 +53,16 @@ #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ /* USBH2CTRL */ +#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) +/* USBH3CTRL */ +#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) +#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) +#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) + /* USB_CTRL_1 */ #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) @@ -196,9 +204,26 @@ int mxc_set_usbcontrol(int port, unsigned int flags) else v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */ #endif +#ifdef CONFIG_MX53 + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */ + else + v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */ +#endif __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); break; +#ifdef CONFIG_MX53 + case 3: /* Host 3 ULPI */ + v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); + if (flags & MXC_EHCI_POWER_PINS_ENABLED) + v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */ + else + v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */ + + __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); + break; +#endif } return ret;