From: "Jernej Škrabec" <jernej.skrabec@siol.net>
To: u-boot@lists.denx.de
Subject: [linux-sunxi] [PATCH] sunxi: clock: H6/H616: Fix PLL6 clock calculation
Date: Wed, 28 Apr 2021 17:21:36 +0200 [thread overview]
Message-ID: <6894461.cN26AFp3AY@kista> (raw)
In-Reply-To: <20210428100555.8077-1-andre.przywara@arm.com>
Hi!
Dne sreda, 28. april 2021 ob 12:05:55 CEST je Andre Przywara napisal(a):
> The "n" factor of the PLL_PERIPH0 clock is using the usual +1 encoding,
> so we need to adjust the register value before doing the calculation.
>
> This fixes the MMC clock setup on those SoCs, which could be slightly off
> due to the wrong parent frequency:
> mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Good catch!
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Best regards,
Jernej
prev parent reply other threads:[~2021-04-28 15:21 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-28 10:05 [PATCH] sunxi: clock: H6/H616: Fix PLL6 clock calculation Andre Przywara
2021-04-28 15:21 ` Jernej Škrabec [this message]
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