Re: [PATCH v3 2/4] riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next

[E Shattow <e@freeshell.de>]

On 9/16/25 17:02, E Shattow wrote:
> Sync automatic dtsi inclusion overrides for JH7110 CPU with upstream
> "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
> loader" from upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
> 
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
>  arch/riscv/dts/jh7110-u-boot.dtsi | 81 ++++++++++++-------------------
>  1 file changed, 31 insertions(+), 50 deletions(-)
> 
> diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
> index f8d13277d24..cc27dd648f8 100644
> --- a/arch/riscv/dts/jh7110-u-boot.dtsi
> +++ b/arch/riscv/dts/jh7110-u-boot.dtsi
> @@ -3,36 +3,10 @@
>   * Copyright (C) 2022 StarFive Technology Co., Ltd.
>   */
>  
> -#include <dt-bindings/reset/starfive,jh7110-crg.h>
> -
> -/ {
> -	timer {
> -		compatible = "riscv,timer";
> -		interrupts-extended = <&cpu0_intc 5>,
> -				      <&cpu1_intc 5>,
> -				      <&cpu2_intc 5>,
> -				      <&cpu3_intc 5>,
> -				      <&cpu4_intc 5>;
> -	};
> +// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
> +// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
>  
> -	soc {
> -		bootph-pre-ram;
> -
> -		dmc: dmc@15700000 {
> -			bootph-pre-ram;
> -			compatible = "starfive,jh7110-dmc";
> -			reg = <0x0 0x15700000 0x0 0x10000>,
> -				<0x0 0x13000000 0x0 0x10000>;
> -			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> -				<&syscrg JH7110_SYSRST_DDR_OSC>,
> -				<&syscrg JH7110_SYSRST_DDR_APB>;
> -			reset-names = "axi", "osc", "apb";
> -			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> -			clock-names = "pll1_out";
> -			clock-frequency = <2133>;
> -		};
> -	};
> -};
> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>  
>  &clint {
>  	bootph-pre-ram;
> @@ -58,22 +32,10 @@
>  	bootph-pre-ram;
>  };
>  
> -&cpus {
> -	bootph-pre-ram;
> -};
> -
>  &osc {
>  	bootph-pre-ram;
>  };
>  
> -&gmac0_rgmii_rxin {
> -	bootph-pre-ram;
> -};
> -
> -&gmac0_rmii_refin {
> -	bootph-pre-ram;
> -};
> -
>  &gmac1_rgmii_rxin {
>  	bootph-pre-ram;
>  };
> @@ -82,23 +44,42 @@
>  	bootph-pre-ram;
>  };
>  
> -&aoncrg {
> -	bootph-pre-ram;
> +/ {
> +	soc {
> +		memory-controller@15700000 {
> +			compatible = "starfive,jh7110-dmc";
> +			reg = <0x0 0x15700000 0x0 0x10000>,
> +			      <0x0 0x13000000 0x0 0x10000>;
> +			bootph-pre-ram;
> +			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> +			clock-names = "pll";
> +			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> +				 <&syscrg JH7110_SYSRST_DDR_OSC>,
> +				 <&syscrg JH7110_SYSRST_DDR_APB>;
> +			reset-names = "axi", "osc", "apb";
> +		};
> +	};
>  };
>  
> -&pllclk {
> +&syscrg {
>  	bootph-pre-ram;
>  };
>  
> -&syscrg {
> -	assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */
> +&pllclk {
>  	bootph-pre-ram;
>  };
>  
> -&stgcrg {
> -	bootph-pre-ram;
> +// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
> +
> +/ {
> +	soc {
> +		memory-controller@15700000 {
> +			clock-frequency = <2133>; /* FIXME: delete property and implement CCF */
> +		};
> +	};
>  };
>  
> -&sys_syscon {
> -	bootph-pre-ram;
> +&syscrg {
> +	assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */
>  };
> +

Newline at end of file gets a warning, will delete.

-E