From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47031CAC592 for ; Wed, 17 Sep 2025 02:59:22 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 63BA780325; Wed, 17 Sep 2025 04:59:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=freeshell.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 21F1F80B9B; Wed, 17 Sep 2025 04:59:19 +0200 (CEST) Received: from freeshell.de (freeshell.de [116.202.128.144]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2402A800D7 for ; Wed, 17 Sep 2025 04:59:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=freeshell.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=e@freeshell.de Received: from [192.168.2.54] (unknown [216.234.200.145]) (Authenticated sender: e) by freeshell.de (Postfix) with ESMTPSA id 23DA8B220315; Wed, 17 Sep 2025 04:59:14 +0200 (CEST) Message-ID: <73c422cb-ad9c-47a9-84eb-c878bf4b91d3@freeshell.de> Date: Tue, 16 Sep 2025 19:59:13 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/4] riscv: dts: starfive: sync visionfive2 overrides with upstream Linux for-next To: Rick Chen , Leo , Minda Chen , Hal Feng , Tom Rini Cc: u-boot@lists.denx.de, Heinrich Schuchardt References: <20250917000254.1134031-1-e@freeshell.de> <20250917000254.1134031-3-e@freeshell.de> Content-Language: en-US From: E Shattow In-Reply-To: <20250917000254.1134031-3-e@freeshell.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 9/16/25 17:02, E Shattow wrote: > Sync automatic dtsi inclusion overrides for JH7110 CPU with upstream > "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot > loader" from upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21 > > Signed-off-by: E Shattow > --- > arch/riscv/dts/jh7110-u-boot.dtsi | 81 ++++++++++++------------------- > 1 file changed, 31 insertions(+), 50 deletions(-) > > diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi > index f8d13277d24..cc27dd648f8 100644 > --- a/arch/riscv/dts/jh7110-u-boot.dtsi > +++ b/arch/riscv/dts/jh7110-u-boot.dtsi > @@ -3,36 +3,10 @@ > * Copyright (C) 2022 StarFive Technology Co., Ltd. > */ > > -#include > - > -/ { > - timer { > - compatible = "riscv,timer"; > - interrupts-extended = <&cpu0_intc 5>, > - <&cpu1_intc 5>, > - <&cpu2_intc 5>, > - <&cpu3_intc 5>, > - <&cpu4_intc 5>; > - }; > +// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" > +// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21 > > - soc { > - bootph-pre-ram; > - > - dmc: dmc@15700000 { > - bootph-pre-ram; > - compatible = "starfive,jh7110-dmc"; > - reg = <0x0 0x15700000 0x0 0x10000>, > - <0x0 0x13000000 0x0 0x10000>; > - resets = <&syscrg JH7110_SYSRST_DDR_AXI>, > - <&syscrg JH7110_SYSRST_DDR_OSC>, > - <&syscrg JH7110_SYSRST_DDR_APB>; > - reset-names = "axi", "osc", "apb"; > - clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; > - clock-names = "pll1_out"; > - clock-frequency = <2133>; > - }; > - }; > -}; > +#include > > &clint { > bootph-pre-ram; > @@ -58,22 +32,10 @@ > bootph-pre-ram; > }; > > -&cpus { > - bootph-pre-ram; > -}; > - > &osc { > bootph-pre-ram; > }; > > -&gmac0_rgmii_rxin { > - bootph-pre-ram; > -}; > - > -&gmac0_rmii_refin { > - bootph-pre-ram; > -}; > - > &gmac1_rgmii_rxin { > bootph-pre-ram; > }; > @@ -82,23 +44,42 @@ > bootph-pre-ram; > }; > > -&aoncrg { > - bootph-pre-ram; > +/ { > + soc { > + memory-controller@15700000 { > + compatible = "starfive,jh7110-dmc"; > + reg = <0x0 0x15700000 0x0 0x10000>, > + <0x0 0x13000000 0x0 0x10000>; > + bootph-pre-ram; > + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; > + clock-names = "pll"; > + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, > + <&syscrg JH7110_SYSRST_DDR_OSC>, > + <&syscrg JH7110_SYSRST_DDR_APB>; > + reset-names = "axi", "osc", "apb"; > + }; > + }; > }; > > -&pllclk { > +&syscrg { > bootph-pre-ram; > }; > > -&syscrg { > - assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */ > +&pllclk { > bootph-pre-ram; > }; > > -&stgcrg { > - bootph-pre-ram; > +// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader" > + > +/ { > + soc { > + memory-controller@15700000 { > + clock-frequency = <2133>; /* FIXME: delete property and implement CCF */ > + }; > + }; > }; > > -&sys_syscon { > - bootph-pre-ram; > +&syscrg { > + assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */ > }; > + Newline at end of file gets a warning, will delete. -E