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From: "Jernej Škrabec" <jernej.skrabec@siol.net>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RFC PATCH 1/3] sunxi: Add clocks for DE2/HDMI/TCON
Date: Tue, 13 Dec 2016 20:20:21 +0100	[thread overview]
Message-ID: <740829085.CNNSQe3VuG@jernej-laptop> (raw)
In-Reply-To: <20161213151858.73tnzfqsn4a72ivk@lukather>

Hi,

On Tue, Dec 13, 2016 at 16:18:58 CET, Maxime Ripard wrote:
> Hi,
> 
> First off, thanks a lot for working on this.
> 
> On Tue, Dec 13, 2016 at 01:36:28AM +0100, Jernej Skrabec wrote:
> > This is needed for HDMI support, which will be added later.
> > 
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > ---
> > 
> >  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 43
> >  +++++++++++++++++++++++++++ arch/arm/mach-sunxi/clock_sun6i.c           
> >   | 28 +++++++++++++++++ 2 files changed, 71 insertions(+)
> > 
> > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> > b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index be9fcfd..c19c200
> > 100644
> > --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> > @@ -67,12 +67,20 @@ struct sunxi_ccm_reg {
> > 
> >  	u32 dram_pll_cfg;	/* 0xf8 PLL_DDR cfg register, A33 only */
> >  	u32 mbus_reset;		/* 0xfc MBUS reset control, A33 only */
> >  	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
> > 
> > +#ifdef CONFIG_MACH_SUN8I_H3
> > +	u32 de_clk_cfg;		/* 0x104 DE module clock */
> > +#else
> > 
> >  	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
> > 
> > +#endif
> > 
> >  	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
> >  	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
> >  	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
> >  	u32 mp_clk_cfg;		/* 0x114 MP module clock */
> > 
> > +#ifdef CONFIG_MACH_SUN8I_H3
> > +	u32 tcon0_clk_cfg;	/* 0x118 TCON0 module clock */
> > +#else
> > 
> >  	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
> > 
> > +#endif
> > 
> >  	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
> >  	u32 reserved14[3];
> >  	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
> > 
> > @@ -85,7 +93,11 @@ struct sunxi_ccm_reg {
> > 
> >  	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
> >  	u32 reserved15;
> >  	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
> > 
> > +#ifdef CONFIG_MACH_SUN8I_H3
> > +	u32 hdmi_slow_clk_cfg;	/* 0x154 HDMI slow module clock */
> > +#else
> > 
> >  	u32 ps_clk_cfg;		/* 0x154 PS module clock */
> > 
> > +#endif
> > 
> >  	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
> >  	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
> >  	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
> > 
> > @@ -220,6 +232,15 @@ struct sunxi_ccm_reg {
> > 
> >  #define CCM_MIPI_PLL_CTRL_LDO_EN	(0x3 << 22)
> >  #define CCM_MIPI_PLL_CTRL_EN		(0x1 << 31)
> > 
> > +#define CCM_PLL10_CTRL_M_SHIFT		0
> > +#define CCM_PLL10_CTRL_M_MASK		(0xf << CCM_PLL10_CTRL_M_SHIFT)
> > +#define CCM_PLL10_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
> > +#define CCM_PLL10_CTRL_N_SHIFT		8
> > +#define CCM_PLL10_CTRL_N_MASK		(0x7f << CCM_PLL10_CTRL_N_SHIFT)
> > +#define CCM_PLL10_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
> > +#define CCM_PLL10_CTRL_INTEGER_MODE	(0x1 << 24)
> > +#define CCM_PLL10_CTRL_EN		(0x1 << 31)
> > +
> > 
> >  #define CCM_PLL11_CTRL_N(n)		((((n) - 1) & 0x3f) << 8)
> >  #define CCM_PLL11_CTRL_SIGMA_DELTA_EN	(0x1 << 24)
> >  #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
> > 
> > @@ -271,9 +292,12 @@ struct sunxi_ccm_reg {
> > 
> >  #define AHB_GATE_OFFSET_DRC0		25
> >  #define AHB_GATE_OFFSET_DE_FE0		14
> >  #define AHB_GATE_OFFSET_DE_BE0		12
> > 
> > +#define AHB_GATE_OFFSET_DE		12
> > 
> >  #define AHB_GATE_OFFSET_HDMI		11
> >  #define AHB_GATE_OFFSET_LCD1		5
> >  #define AHB_GATE_OFFSET_LCD0		4
> > 
> > +#define AHB_GATE_OFFSET_TCON1		4
> > +#define AHB_GATE_OFFSET_TCON0		3
> 
> Maybe having some ifdef here would help, only to differentiate between
> the DE1 and DE2 cases that would require different defines here.
> 
> Note that it also applies to the rest of that patch.

You mean something like this?

#ifdef CONFIG_SUNXI_DE2
#define AHB_GATE_OFFSET_TCON1		4
#define AHB_GATE_OFFSET_TCON0		3
#else
#define AHB_GATE_OFFSET_LCD1		5
#define AHB_GATE_OFFSET_LCD0		4
#endif

and then in include/configs/sun8i.h something like this?

#if defined(CONFIG_MACH_SUN8I_H3)
	#define CONFIG_SUNXI_DE2	1
#endif

Best regards,
Jernej Skrabec

> 
> Thanks,
> Maxime
> 
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

  reply	other threads:[~2016-12-13 19:20 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-13  0:36 [U-Boot] [RFC PATCH 0/3] sunxi: video: Add support for HDMI output on H3 Jernej Skrabec
2016-12-13  0:36 ` [U-Boot] [RFC PATCH 1/3] sunxi: Add clocks for DE2/HDMI/TCON Jernej Skrabec
2016-12-13 15:18   ` Maxime Ripard
2016-12-13 19:20     ` Jernej Škrabec [this message]
2016-12-14  2:39       ` Chen-Yu Tsai
2016-12-13  0:36 ` [U-Boot] [RFC PATCH 2/3] sunxi: video: Add video driver for H3 SoC Jernej Skrabec
2016-12-13 15:40   ` Maxime Ripard
2016-12-13 16:33     ` Chen-Yu Tsai
2016-12-13 20:13     ` Jernej Škrabec
2016-12-14 10:28       ` Maxime Ripard
2016-12-14 22:11         ` Jernej Škrabec
2016-12-19 13:28           ` Maxime Ripard
2017-02-05 22:23   ` Rask Ingemann Lambertsen
2016-12-13  0:36 ` [U-Boot] [RFC PATCH 3/3] sunxi: Enable H3 video driver in defconfigs Jernej Skrabec
2016-12-13 20:28 ` [U-Boot] [RFC PATCH 0/3] sunxi: video: Add support for HDMI output on H3 Simon Glass
2016-12-13 21:16   ` [U-Boot] [linux-sunxi] " Icenowy Zheng
2016-12-14  3:02     ` Chen-Yu Tsai
2016-12-14  9:25       ` Maxime Ripard
2016-12-14  9:37         ` Alexander Graf
2016-12-14  9:51           ` Emmanuel Vadot
2016-12-20 10:47           ` Maxime Ripard
2016-12-14  8:37   ` [U-Boot] " Hans de Goede
2016-12-14  9:24     ` Maxime Ripard
2016-12-17 22:47     ` Simon Glass
2017-02-05 22:14 ` Rask Ingemann Lambertsen

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