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Mon, 26 Jul 2021 18:19:49 +0200 (CEST) Received: from srv-mda-01.robart.cc (srv-mda-01.robart.cc [10.0.10.21]) by srv-mta-01.robart.cc (Postfix) with ESMTP id EB9071C039A; Mon, 26 Jul 2021 18:19:48 +0200 (CEST) Date: Mon, 26 Jul 2021 18:19:48 +0200 (CEST) From: Manuel Dipolt To: u-boot Cc: jagan Message-ID: <775585477.1144891.1627316388716.JavaMail.zimbra@robart.cc> Subject: [PATCH] sunxi: h3: enable clock support for r_pio gpios MIME-Version: 1.0 X-Originating-IP: [10.0.20.40] X-Mailer: Zimbra 8.8.15_GA_4059 (ZimbraWebClient - FF78 (Linux)/8.8.15_GA_4059) Thread-Index: HGfPpO21pdYMfDGZy/+sCIR4COgZWQ== Thread-Topic: sunxi: h3: enable clock support for r_pio gpios Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-Content-Filtered-By: Mailman/MimeDel 2.1.34 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean This patch enables clock for the r_pio gpios for the h3 Signed-off-by: Manuel Dipolt --- drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_h3-r.c | 51 ++++++++++++++++++++++++++++++++++++ drivers/gpio/sunxi_gpio.c | 9 +++++++ 3 files changed, 61 insertions(+) create mode 100644 drivers/clk/sunxi/clk_h3-r.c diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 36fb2aeb56..e93fe3c2f3 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -15,5 +15,6 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o +obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3-r.o obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_h3-r.c b/drivers/clk/sunxi/clk_h3-r.c new file mode 100644 index 0000000000..a314e37b87 --- /dev/null +++ b/drivers/clk/sunxi/clk_h3-r.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 RobArt GmbH + * Author: Manuel Dipolt + */ + +#include +#include +#include +#include +#include +#include +#include + +static struct ccu_clk_gate h3_r_gates[] = { + [CLK_APB0_PIO] = GATE(0x28, BIT(0)), +}; + +static struct ccu_reset h3_r_resets[] = { + [RST_APB0_IR] = RESET(0x0b0, BIT(2)), + [RST_APB0_TIMER] = RESET(0x0b0, BIT(3)), + [RST_APB0_UART] = RESET(0x0b0, BIT(4)), + [RST_APB0_I2C] = RESET(0x0b0, BIT(6)), +}; + +static const struct ccu_desc h3_r_ccu_desc = { + .gates = h3_r_gates, + .resets = h3_r_resets, +}; + +static int h3_r_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, ARRAY_SIZE(h3_r_resets)); +} + +static const struct udevice_id h3_r_ccu_ids[] = { + { .compatible = "allwinner,sun8i-h3-r-ccu", + .data = (ulong)&h3_r_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_h3_r) = { + .name = "sun8i_h3-r_ccu", + .id = UCLASS_CLK, + .of_match = h3_r_ccu_ids, + .priv_auto_alloc_size = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = sunxi_clk_probe, + .bind = h3_r_clk_bind, +}; + diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index cbed8d42b7..b505be4065 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -262,6 +263,14 @@ static int gpio_sunxi_probe(struct udevice *dev) { struct sunxi_gpio_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk gate_clk; + int ret; + + ret = clk_get_by_name(dev, "apb", &gate_clk); + + if (!ret) + clk_enable(&gate_clk); + /* Tell the uclass how many GPIOs we have */ if (plat) { -- 2.20.1