From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A07C0C6FD1D for ; Fri, 7 Apr 2023 08:57:36 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9083386147; Fri, 7 Apr 2023 10:57:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 1D8A88615F; Fri, 7 Apr 2023 10:57:33 +0200 (CEST) Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by phobos.denx.de (Postfix) with ESMTP id D47BD8601D for ; Fri, 7 Apr 2023 10:57:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=minda.chen@starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 4DB9924E14F; Fri, 7 Apr 2023 16:57:22 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 7 Apr 2023 16:57:22 +0800 Received: from [192.168.125.108] (183.27.97.179) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 7 Apr 2023 16:57:21 +0800 Message-ID: <7b957e33-5820-1595-7288-7277efbfe60e@starfivetech.com> Date: Fri, 7 Apr 2023 16:56:53 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v3 1/3] starfive: pci: Add StarFive JH7110 pcie driver Content-Language: en-US To: =?UTF-8?Q?Pali_Roh=c3=a1r?= CC: Simon Glass , Stefan Roese , Andrew Scull , Mark Kettenis , , Rick Chen , Leo , Mason Huo , Yanhong Wang , Leyfoon Tan , Kevin Xie References: <20230329100143.10724-1-minda.chen@starfivetech.com> <20230329100143.10724-2-minda.chen@starfivetech.com> <20230329172746.gjbmquqvadyxaxll@pali> <3fefac0c-52b1-f7af-d1e5-8564436be1a8@starfivetech.com> <20230331125912.4sclo6hadin7mkkd@pali> From: Minda Chen In-Reply-To: <20230331125912.4sclo6hadin7mkkd@pali> Content-Type: text/plain; charset="UTF-8" X-Originating-IP: [183.27.97.179] X-ClientProxiedBy: EXCAS065.cuchost.com (172.16.6.25) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 2023/3/31 20:59, Pali Roh=C3=A1r wrote: > On Friday 31 March 2023 18:35:00 Minda Chen wrote: >> On 2023/3/30 1:27, Pali Roh=C3=A1r wrote: >> > Hello! >> >=20 >> > On Wednesday 29 March 2023 18:01:41 Minda Chen wrote: >> >> + /* PCIe PCI Standard Configuration Identification Settings. */ >> >> + value =3D (PCI_CLASS_BRIDGE_PCI_NORMAL << IDS_CLASS_CODE_SHIFT) |= IDS_REVISION_ID; >> >> + writel(value, priv->reg_base + PCIE_PCI_IDS); >> >=20 >> > This looks like configuration of the PCI_CLASS_REVISION read-only >> > register. Is there any reason why you are removing the original >> > "revision" information by hardcoded IDS_REVISION_ID constant? >> >=20 >> This register is not read-only register, consist resion ID and class = code. >> Bit [39:32]: Revision ID >> Bit [63:40]: Class code >=20 > I mean that this "priv->reg_base + PCIE_PCI_IDS" read-write register > configures what is visible when reading read-only standard PCI register > PCI_CLASS_REVISION. >=20 > PCIe Root Port is by definition of PCI-to-PCI Bridge class and therefor= e > reading from PCI_CLASS_REVISION must return PCI_CLASS_BRIDGE_PCI_* valu= e. > This is required by PCIe spec. >=20 > With above driver init code it looks like that your PCIe controller doe= s > not set correct value into PCI_CLASS_REVISION register after power-on > and manually setting correct value via "priv->reg_base + PCIE_PCI_IDS" > is a workaround. >=20 > Hopefully it is a more clear what I mean in my previous email. >=20 > Also mvebu controller has this issue and has similar workaround in > pci_mvebu.c driver. >=20 >> And the register reset value is zero, Our PCIe version is 2.0. So set = value 2. >> Maybe I will add comment to this. >=20 > Well, Revision ID (low 8 bits of PCI_CLASS_REVISION) is the extension t= o > the vendor / device id register. It is not version of PCIe standard. >=20 > I would expect that this Vendor ID, Device ID and Revision ID values ar= e > not being changed by the driver as they identify PCI and PCIe devices. I am sorry. It is PCIe controller IP revision ID. I have make a mistake f= or it. So zero value is correct. I will remove writing IDS_REVISION_ID value.