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[173.73.95.180]) by smtp.gmail.com with ESMTPSA id ay29-20020a05622a229d00b0039cd4d87aacsm7139229qtb.15.2022.11.07.17.43.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Nov 2022 17:43:09 -0800 (PST) Message-ID: <7c1ff208-8b36-aa83-e302-cd6f24e9cef5@gmail.com> Date: Mon, 7 Nov 2022 20:43:08 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v2 2/5] usb: dwc3: reference clock period configuration Content-Language: en-US To: Marek Vasut , u-boot@lists.denx.de Cc: Balaji Prakash J , Baruch Siach , Angus Ainslie , Bin Meng , Fabio Estevam , Kunihiko Hayashi , Michal Simek , Peng Fan , Sean Anderson , Stefano Babic References: <20221108014013.750292-1-marex@denx.de> <20221108014013.750292-2-marex@denx.de> From: Sean Anderson In-Reply-To: <20221108014013.750292-2-marex@denx.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 11/7/22 20:40, Marek Vasut wrote: > From: Balaji Prakash J > > Set reference clock period when it differs from dwc3 default hardware > set. > > We could calculate clock period based on reference clock frequency. But > this information is not always available. This is the case of PCI bus > attached USB host. For that reason we use a custom property. > > Tested (USB2 only) on IPQ6010 SoC based board with 24 MHz reference > clock while hardware default is 19.2 MHz. > > [ baruch: rewrite commit message; drop GFLADJ code; remove 'quirk-' from > property name; mention tested hardware ] > > [ marek: Ported from Linux kernel commit > 7bee318838890 ("usb: dwc3: reference clock period configuration") ] > > Signed-off-by: Balaji Prakash J > Signed-off-by: Baruch Siach > Signed-off-by: Marek Vasut # Port from Linux > --- > Cc: Angus Ainslie > Cc: Bin Meng > Cc: Fabio Estevam > Cc: Kunihiko Hayashi > Cc: Michal Simek > Cc: Peng Fan > Cc: Sean Anderson > Cc: Stefano Babic > --- > V2: No change > --- > drivers/usb/dwc3/core.c | 27 +++++++++++++++++++++++++++ > drivers/usb/dwc3/core.h | 6 ++++++ > 2 files changed, 33 insertions(+) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index b592a487e00..300450100c9 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -28,6 +28,7 @@ > #include > #include > #include > +#include > > #include "core.h" > #include "gadget.h" > @@ -114,6 +115,28 @@ static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj) > dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); > } > > +/** > + * dwc3_ref_clk_period - Reference clock period configuration > + * Default reference clock period depends on hardware > + * configuration. For systems with reference clock that differs > + * from the default, this will set clock period in DWC3_GUCTL > + * register. > + * @dwc: Pointer to our controller context structure > + * @ref_clk_per: reference clock period in ns > + */ > +static void dwc3_ref_clk_period(struct dwc3 *dwc) > +{ > + u32 reg; > + > + if (dwc->ref_clk_per == 0) > + return; > + > + reg = dwc3_readl(dwc->regs, DWC3_GUCTL); > + reg &= ~DWC3_GUCTL_REFCLKPER_MASK; > + reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, dwc->ref_clk_per); > + dwc3_writel(dwc->regs, DWC3_GUCTL, reg); > +} > + > /** > * dwc3_free_one_event_buffer - Frees one event buffer > * @dwc: Pointer to our controller context structure > @@ -640,6 +663,9 @@ static int dwc3_core_init(struct dwc3 *dwc) > /* Adjust Frame Length */ > dwc3_frame_length_adjustment(dwc, dwc->fladj); > > + /* Adjust Reference Clock Period */ > + dwc3_ref_clk_period(dwc); > + > dwc3_set_incr_burst_type(dwc); > > return 0; > @@ -1043,6 +1069,7 @@ void dwc3_of_parse(struct dwc3 *dwc) > | (dwc->is_utmi_l1_suspend << 4); > > dev_read_u32(dev, "snps,quirk-frame-length-adjustment", &dwc->fladj); > + dev_read_u32(dev, "snps,ref-clock-period-ns", &dwc->ref_clk_per); > > /* > * Handle property "snps,incr-burst-type-adjustment". > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index 0d20fe285b0..b4a7d9e52bc 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -249,6 +249,10 @@ > #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7) > #define DWC3_GFLADJ_30MHZ_MASK 0x3f > > +/* Global User Control Register*/ > +#define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 > +#define DWC3_GUCTL_REFCLKPER_SEL 22 > + > /* Device Configuration Register */ > #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) > #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) > @@ -671,6 +675,7 @@ struct dwc3_scratchpad_array { > * @ref_clk: reference clock > * @regs: base address for our registers > * @regs_size: address space size > + * @ref_clk_per: reference clock period configuration > * @nr_scratch: number of scratch buffers > * @num_event_buffers: calculated number of event buffers > * @u1u2: only used on revisions <1.83a for workaround > @@ -832,6 +837,7 @@ struct dwc3 { > u8 lpm_nyet_threshold; > u8 hird_threshold; > u32 fladj; > + u32 ref_clk_per; > u8 incrx_mode; > u32 incrx_size; > Reviewed-by: Sean Anderson