[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[Akshay Saraswat]

Hi Nishanth,

>On 17:13-20150224, Nishanth Menon wrote:
>> On 13:27-20150220, Akshay Saraswat wrote:
>> > This patch adds workaround for ARM errata 798870 which says
>> > "If back-to-back speculative cache line fills (fill A and fill B) are
>> > issued from the L1 data cache of a CPU to the L2 cache, the second
>> > request (fill B) is then cancelled, and the second request would have
>> > detected a hazard against a recent write or eviction (write B) to the
>> > same cache line as fill B then the L2 logic might deadlock."
>> > 
>> > Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
>> > Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>> > Reviewed-by: Simon Glass <sjg@chromium.org>
>> > Tested-by: Simon Glass <sjg@chromium.org>
>> > ---
>> > Changes since v3:
>> > 	- Added errata number in comment.
>> > 	- Moved changes to arm generic armv7.h
>> > 
>> > Changes since v2:
>> > 	- No change.
>> > 
>> > Changes since v1:
>> > 	- Added Reviewed-by & Tested-by.
>> > 	- Added space before */ on line # 40.
>> > 
>> >  arch/arm/include/asm/armv7.h | 16 ++++++++++++++++
>> >  1 file changed, 16 insertions(+)
>> > 
>> > diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
>> > index a13da23..a2040b7 100644
>> > --- a/arch/arm/include/asm/armv7.h
>> > +++ b/arch/arm/include/asm/armv7.h
>> > @@ -69,6 +69,22 @@
>> >  #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
>> >  #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
>> >  
>> > +/*
>> > + * Workaround for ARM errata # 798870
>> > + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
>> > + * stalled for 1024 cycles to verify that its hazard condition still exists.
>> > + */
>> > +static inline void v7_enable_l2_hazard_detect(void)
>> > +{
>> > +	uint32_t val;
>> > +
>> > +	/* L2ACTLR[7]: Enable hazard detect timeout */
>> > +	asm volatile ("mrc     p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
>> > +	val |= (1 << 7);
>> > +	asm volatile ("mcr     p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
>> 
>> This wont work for us in DRA7/OMAP5 L2ACTLR cannot be modified by
>> u-boot. has to go to secure world using smc call.
>> 
>> > +}
>> > +
>> > +void v7_en_l2_hazard_detect(void);
>> >  void v7_outer_cache_enable(void);
>> >  void v7_outer_cache_disable(void);
>> >  void v7_outer_cache_flush_all(void);
>> 
>> How about this - using the series:
>> https://patchwork.ozlabs.org/patch/443261/                
>> https://patchwork.ozlabs.org/patch/443264/                
>> https://patchwork.ozlabs.org/patch/443268/                
>> https://patchwork.ozlabs.org/patch/443265/                
>> https://patchwork.ozlabs.org/patch/443263/                
>> https://patchwork.ozlabs.org/patch/443262/                
>> https://patchwork.ozlabs.org/patch/443267/                
>> https://patchwork.ozlabs.org/patch/443266/                
>> https://patchwork.ozlabs.org/patch/443260/                
>
>I think the following might work for exynos?
>

Yes, that will probably do and if you look at v3 of this patch,
we were doing something similar. But I was convinced with the
below mentioned comments I recieved over v3, so updated it.

" Having the ARM errata number mentioned in the comment here would make
the purpose of this code much more clear to anyone looking at it later
in the future.
Also isn't this a general purpose Cortex-A15 r2pX workaround,
also potentially useful for the other non-Exynos SoCs too? "

I don't think it hurts to have a generic function with ARM errata workaround
implementation. Whoever wish to use it can call it in their boot path. And it's
not even getting executed right now for any SoC other than Exynos542x, so those
who don't want it need not bother about it. This was the intention. :)

Please let me know if you still want me to move it from armv7.h to exynos/lowlevel_init.c

>diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>index 83e1dcfc1e13..0157105524ca 100644
>--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>@@ -42,6 +42,23 @@ enum {
> 	DO_POWER	= 1 << 4,
> };
> 
>+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA
>+void arch_cp15_errata_workaround(u32 midr, u32 variant, u32 rev, u32 comb)
>+{
>+#ifdef CONFIG_ARM_ERRATA_798870
>+	if (comb >= 0x20 && comb < 0x30) {
>+		uint32_t l2actlr;
>+
>+		mrc_l2_aux_ctlr(l2actlr);
>+		/* Disable ACE DVM/CMO message broadcas */
>+		l2actlr |= (1 << 7);
>+		mcr_l2_aux_ctlr(l2actlr);
>+		mrc_l2_ctlr(l2actlr);
>+	}
>+#endif
>+}
>+#endif
>+
> int do_lowlevel_init(void)
> {
> 	uint32_t reset_status;
>-- 
>Regards,
>Nishanth Menon

Regards,
Akshay Saraswat

[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[Nishanth Menon]

On Wed, Feb 25, 2015 at 2:27 AM, Akshay Saraswat <akshay.s@samsung.com> wrote:
> Hi Nishanth,
>
>>On 17:13-20150224, Nishanth Menon wrote:
>>> On 13:27-20150220, Akshay Saraswat wrote:
>>> > This patch adds workaround for ARM errata 798870 which says
>>> > "If back-to-back speculative cache line fills (fill A and fill B) are
>>> > issued from the L1 data cache of a CPU to the L2 cache, the second
>>> > request (fill B) is then cancelled, and the second request would have
>>> > detected a hazard against a recent write or eviction (write B) to the
>>> > same cache line as fill B then the L2 logic might deadlock."
>>> >
>>> > Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
>>> > Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>>> > Reviewed-by: Simon Glass <sjg@chromium.org>
>>> > Tested-by: Simon Glass <sjg@chromium.org>
>>> > ---
>>> > Changes since v3:
>>> >    - Added errata number in comment.
>>> >    - Moved changes to arm generic armv7.h
>>> >
>>> > Changes since v2:
>>> >    - No change.
>>> >
>>> > Changes since v1:
>>> >    - Added Reviewed-by & Tested-by.
>>> >    - Added space before */ on line # 40.
>>> >
>>> >  arch/arm/include/asm/armv7.h | 16 ++++++++++++++++
>>> >  1 file changed, 16 insertions(+)
>>> >
>>> > diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
>>> > index a13da23..a2040b7 100644
>>> > --- a/arch/arm/include/asm/armv7.h
>>> > +++ b/arch/arm/include/asm/armv7.h
>>> > @@ -69,6 +69,22 @@
>>> >  #define CP15DSB   asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
>>> >  #define CP15DMB   asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
>>> >
>>> > +/*
>>> > + * Workaround for ARM errata # 798870
>>> > + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
>>> > + * stalled for 1024 cycles to verify that its hazard condition still exists.
>>> > + */
>>> > +static inline void v7_enable_l2_hazard_detect(void)
>>> > +{
>>> > +  uint32_t val;
>>> > +
>>> > +  /* L2ACTLR[7]: Enable hazard detect timeout */
>>> > +  asm volatile ("mrc     p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
>>> > +  val |= (1 << 7);
>>> > +  asm volatile ("mcr     p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
>>>
>>> This wont work for us in DRA7/OMAP5 L2ACTLR cannot be modified by
>>> u-boot. has to go to secure world using smc call.
>>>
>>> > +}
>>> > +
>>> > +void v7_en_l2_hazard_detect(void);
>>> >  void v7_outer_cache_enable(void);
>>> >  void v7_outer_cache_disable(void);
>>> >  void v7_outer_cache_flush_all(void);
>>>
>>> How about this - using the series:
>>> https://patchwork.ozlabs.org/patch/443261/
>>> https://patchwork.ozlabs.org/patch/443264/
>>> https://patchwork.ozlabs.org/patch/443268/
>>> https://patchwork.ozlabs.org/patch/443265/
>>> https://patchwork.ozlabs.org/patch/443263/
>>> https://patchwork.ozlabs.org/patch/443262/
>>> https://patchwork.ozlabs.org/patch/443267/
>>> https://patchwork.ozlabs.org/patch/443266/
>>> https://patchwork.ozlabs.org/patch/443260/
>>
>>I think the following might work for exynos?
>>
>
> Yes, that will probably do and if you look at v3 of this patch,
> we were doing something similar. But I was convinced with the
> below mentioned comments I recieved over v3, so updated it.
>
> " Having the ARM errata number mentioned in the comment here would make
> the purpose of this code much more clear to anyone looking at it later
> in the future.
> Also isn't this a general purpose Cortex-A15 r2pX workaround,
> also potentially useful for the other non-Exynos SoCs too? "
>
> I don't think it hurts to have a generic function with ARM errata workaround
> implementation. Whoever wish to use it can call it in their boot path. And it's
> not even getting executed right now for any SoC other than Exynos542x, so those
> who don't want it need not bother about it. This was the intention. :)
>
> Please let me know if you still want me to move it from armv7.h to exynos/lowlevel_init.c
>

I think I can do a V3 on my series for a middle path between the two
approaches. Assuming that exynos does not need any specific custom smc
call for the l2actlr update. will split every erratum into a separate
patch of it's own.


>>diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>>index 83e1dcfc1e13..0157105524ca 100644
>>--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>>+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
>>@@ -42,6 +42,23 @@ enum {
>>       DO_POWER        = 1 << 4,
>> };
>>
>>+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA
>>+void arch_cp15_errata_workaround(u32 midr, u32 variant, u32 rev, u32 comb)
>>+{
>>+#ifdef CONFIG_ARM_ERRATA_798870
>>+      if (comb >= 0x20 && comb < 0x30) {
>>+              uint32_t l2actlr;
>>+
>>+              mrc_l2_aux_ctlr(l2actlr);
>>+              /* Disable ACE DVM/CMO message broadcas */
>>+              l2actlr |= (1 << 7);
>>+              mcr_l2_aux_ctlr(l2actlr);
>>+              mrc_l2_ctlr(l2actlr);
>>+      }
>>+#endif
>>+}
>>+#endif
>>+
>> int do_lowlevel_init(void)
>> {
>>       uint32_t reset_status;
>>--
>>Regards,
>>Nishanth Menon
>
> Regards,
> Akshay Saraswat
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot



-- 
---
Regards,
Nishanth Menon

[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[Kevin Hilman]

Akshay Saraswat <akshay.s@samsung.com> writes:

[...]

> I don't think it hurts to have a generic function with ARM errata
> workaround implementation. Whoever wish to use it can call it in their
> boot path. And it's not even getting executed right now for any SoC
> other than Exynos542x, so those who don't want it need not bother
> about it. This was the intention. :)

What about exynos542x platforms which also have secure firmware?  Are
you testing this on any of those (e.g. exynos5422-odroid-xu3?)

Kevin

[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[Akshay Saraswat]

Hi Kevin,

>Akshay Saraswat <akshay.s@samsung.com> writes:
>
>[...]
>
>> I don't think it hurts to have a generic function with ARM errata
>> workaround implementation. Whoever wish to use it can call it in their
>> boot path. And it's not even getting executed right now for any SoC
>> other than Exynos542x, so those who don't want it need not bother
>> about it. This was the intention. :)
>
>What about exynos542x platforms which also have secure firmware?  Are
>you testing this on any of those (e.g. exynos5422-odroid-xu3?)

No, I have not tested this series on exynos5422-odroid-xu3 becuase
I don't have it. :)

Probably those who are working on exynos5422-odroid-xu3 should comment.
I don't know anything about exynos5422-odroid-xu3 and don't have related
documents.
But as far as I know, from my past experience, for all such features
(SMC calls, secondary cores boot path and configuration), there should be
a different secure firmware which may not be U-Boot. If true, this whole
series of patches would be useless and CONFIG_EXYNOS5420 should not be
defined for such a SoC.

>
>Kevin

Regards,
Akshay Saraswat

[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[Akshay Saraswat]

>On 13:27-20150220, Akshay Saraswat wrote:
>> This patch adds workaround for ARM errata 798870 which says
>> "If back-to-back speculative cache line fills (fill A and fill B) are
>> issued from the L1 data cache of a CPU to the L2 cache, the second
>> request (fill B) is then cancelled, and the second request would have
>> detected a hazard against a recent write or eviction (write B) to the
>> same cache line as fill B then the L2 logic might deadlock."
>> 
>> Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> Tested-by: Simon Glass <sjg@chromium.org>
>> ---
>> Changes since v3:
>> 	- Added errata number in comment.
>> 	- Moved changes to arm generic armv7.h
>> 
>> Changes since v2:
>> 	- No change.
>> 
>> Changes since v1:
>> 	- Added Reviewed-by & Tested-by.
>> 	- Added space before */ on line # 40.
>> 
>>  arch/arm/include/asm/armv7.h | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>> 
>> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
>> index a13da23..a2040b7 100644
>> --- a/arch/arm/include/asm/armv7.h
>> +++ b/arch/arm/include/asm/armv7.h
>> @@ -69,6 +69,22 @@
>>  #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
>>  #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
>>  
>> +/*
>> + * Workaround for ARM errata # 798870
>> + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
>> + * stalled for 1024 cycles to verify that its hazard condition still exists.
>> + */
>> +static inline void v7_enable_l2_hazard_detect(void)
>> +{
>> +	uint32_t val;
>> +
>> +	/* L2ACTLR[7]: Enable hazard detect timeout */
>> +	asm volatile ("mrc     p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
>> +	val |= (1 << 7);
>> +	asm volatile ("mcr     p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
>
>This wont work for us in DRA7/OMAP5 L2ACTLR cannot be modified by
>u-boot. has to go to secure world using smc call.
>

If you dont want to execute it, don't call it. As simple as that. :)
If you want to execute it from secure world, then call it from your SMC handler.
Does it make sense?

>> +}
>> +
>> +void v7_en_l2_hazard_detect(void);
>>  void v7_outer_cache_enable(void);
>>  void v7_outer_cache_disable(void);
>>  void v7_outer_cache_flush_all(void);
>
>How about this - using the series:
>https://patchwork.ozlabs.org/patch/443261/                
>https://patchwork.ozlabs.org/patch/443264/                
>https://patchwork.ozlabs.org/patch/443268/                
>https://patchwork.ozlabs.org/patch/443265/                
>https://patchwork.ozlabs.org/patch/443263/                
>https://patchwork.ozlabs.org/patch/443262/                
>https://patchwork.ozlabs.org/patch/443267/                
>https://patchwork.ozlabs.org/patch/443266/                
>https://patchwork.ozlabs.org/patch/443260/                
>-- 
>Regards,
>Nishanth Menon


Regards,
Akshay Saraswat

[U-Boot] [PATCH v4 00/11] Add support for booting multiple cores

[Akshay Saraswat]

This patch series introduces changes for booting secondary CPUs
on Exynos5420 and Exynos5800.

Changes since v3:
	- Patch 2 & 3 : Added errata number in comments.
	- Patch 2 & 3 : Moved changes to ARM generic file.
	- Patch 6 : Removed this patch. Not required anymore.

Changes since v2:
	- Patch 7 & 8 : Replaced #ifdef and #ifndef -> if(proid_is_soc()).
	- Patch 11 : Removed #ifdef from enum definition.

Changes since v1:
	- Added Reviewed-by & Tested-by in the acked patches.
	- Removed unnecessary CONFIGS and macros.
	- Changed names of few macros for better understanding in patch 2.
	- Added MPIDR bit assignment info comment in power_down_core in patch 2.
	- Changed to SPDX header in sec_boot.S in patch 5.
	- Fixed compilation error for snow build in patch 11.

Akshay Saraswat (9):
  Exynos542x: Config: Add various configs
  Exynos542x: CPU: Power down all secondary cores
  Exynos542x: Add workaround for ARM errata 798870
  Exynos542x: Add workaround for ARM errata 799270
  Exynos542x: Add workaround for exynos iROM errata
  Exynos542x: cache: Disable clean/evict push to external
  Exynos542x: add L2 control register configuration
  Exynos542x: Fix secondary core booting for thumb
  Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset

Doug Anderson (1):
  Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800

 arch/arm/cpu/armv7/exynos/Makefile        |   2 +
 arch/arm/cpu/armv7/exynos/common_setup.h  |  62 +++++++++++++
 arch/arm/cpu/armv7/exynos/exynos5_setup.h |   3 +
 arch/arm/cpu/armv7/exynos/lowlevel_init.c | 147 ++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/exynos/sec_boot.S      | 128 ++++++++++++++++++++++++++
 arch/arm/cpu/armv7/exynos/soc.c           |  35 -------
 arch/arm/include/asm/arch-exynos/cpu.h    |   5 +
 arch/arm/include/asm/arch-exynos/system.h |  88 ++++++++++++++++++
 arch/arm/include/asm/armv7.h              |  44 +++++++++
 include/configs/exynos5420-common.h       |  16 ++++
 10 files changed, 495 insertions(+), 35 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/exynos/sec_boot.S

-- 
1.9.1

[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[Akshay Saraswat]

This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
---
Changes since v3:
	- Added errata number in comment.
	- Moved changes to arm generic armv7.h

Changes since v2:
	- No change.

Changes since v1:
	- Added Reviewed-by & Tested-by.
	- Added space before */ on line # 40.

 arch/arm/include/asm/armv7.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index a13da23..a2040b7 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -69,6 +69,22 @@
 #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
 #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
 
+/*
+ * Workaround for ARM errata # 798870
+ * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
+ * stalled for 1024 cycles to verify that its hazard condition still exists.
+ */
+static inline void v7_enable_l2_hazard_detect(void)
+{
+	uint32_t val;
+
+	/* L2ACTLR[7]: Enable hazard detect timeout */
+	asm volatile ("mrc     p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
+	val |= (1 << 7);
+	asm volatile ("mcr     p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
+}
+
+void v7_en_l2_hazard_detect(void);
 void v7_outer_cache_enable(void);
 void v7_outer_cache_disable(void);
 void v7_outer_cache_flush_all(void);
-- 
1.9.1

[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[Nishanth Menon]

On 13:27-20150220, Akshay Saraswat wrote:
> This patch adds workaround for ARM errata 798870 which says
> "If back-to-back speculative cache line fills (fill A and fill B) are
> issued from the L1 data cache of a CPU to the L2 cache, the second
> request (fill B) is then cancelled, and the second request would have
> detected a hazard against a recent write or eviction (write B) to the
> same cache line as fill B then the L2 logic might deadlock."
> 
> Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Tested-by: Simon Glass <sjg@chromium.org>
> ---
> Changes since v3:
> 	- Added errata number in comment.
> 	- Moved changes to arm generic armv7.h
> 
> Changes since v2:
> 	- No change.
> 
> Changes since v1:
> 	- Added Reviewed-by & Tested-by.
> 	- Added space before */ on line # 40.
> 
>  arch/arm/include/asm/armv7.h | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
> index a13da23..a2040b7 100644
> --- a/arch/arm/include/asm/armv7.h
> +++ b/arch/arm/include/asm/armv7.h
> @@ -69,6 +69,22 @@
>  #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
>  #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
>  
> +/*
> + * Workaround for ARM errata # 798870
> + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
> + * stalled for 1024 cycles to verify that its hazard condition still exists.
> + */
> +static inline void v7_enable_l2_hazard_detect(void)
> +{
> +	uint32_t val;
> +
> +	/* L2ACTLR[7]: Enable hazard detect timeout */
> +	asm volatile ("mrc     p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
> +	val |= (1 << 7);
> +	asm volatile ("mcr     p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));

This wont work for us in DRA7/OMAP5 L2ACTLR cannot be modified by
u-boot. has to go to secure world using smc call.

> +}
> +
> +void v7_en_l2_hazard_detect(void);
>  void v7_outer_cache_enable(void);
>  void v7_outer_cache_disable(void);
>  void v7_outer_cache_flush_all(void);

How about this - using the series:
https://patchwork.ozlabs.org/patch/443261/                
https://patchwork.ozlabs.org/patch/443264/                
https://patchwork.ozlabs.org/patch/443268/                
https://patchwork.ozlabs.org/patch/443265/                
https://patchwork.ozlabs.org/patch/443263/                
https://patchwork.ozlabs.org/patch/443262/                
https://patchwork.ozlabs.org/patch/443267/                
https://patchwork.ozlabs.org/patch/443266/                
https://patchwork.ozlabs.org/patch/443260/                
-- 
Regards,
Nishanth Menon

[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[Nishanth Menon]

On 17:13-20150224, Nishanth Menon wrote:
> On 13:27-20150220, Akshay Saraswat wrote:
> > This patch adds workaround for ARM errata 798870 which says
> > "If back-to-back speculative cache line fills (fill A and fill B) are
> > issued from the L1 data cache of a CPU to the L2 cache, the second
> > request (fill B) is then cancelled, and the second request would have
> > detected a hazard against a recent write or eviction (write B) to the
> > same cache line as fill B then the L2 logic might deadlock."
> > 
> > Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
> > Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
> > Reviewed-by: Simon Glass <sjg@chromium.org>
> > Tested-by: Simon Glass <sjg@chromium.org>
> > ---
> > Changes since v3:
> > 	- Added errata number in comment.
> > 	- Moved changes to arm generic armv7.h
> > 
> > Changes since v2:
> > 	- No change.
> > 
> > Changes since v1:
> > 	- Added Reviewed-by & Tested-by.
> > 	- Added space before */ on line # 40.
> > 
> >  arch/arm/include/asm/armv7.h | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
> > index a13da23..a2040b7 100644
> > --- a/arch/arm/include/asm/armv7.h
> > +++ b/arch/arm/include/asm/armv7.h
> > @@ -69,6 +69,22 @@
> >  #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
> >  #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
> >  
> > +/*
> > + * Workaround for ARM errata # 798870
> > + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
> > + * stalled for 1024 cycles to verify that its hazard condition still exists.
> > + */
> > +static inline void v7_enable_l2_hazard_detect(void)
> > +{
> > +	uint32_t val;
> > +
> > +	/* L2ACTLR[7]: Enable hazard detect timeout */
> > +	asm volatile ("mrc     p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
> > +	val |= (1 << 7);
> > +	asm volatile ("mcr     p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
> 
> This wont work for us in DRA7/OMAP5 L2ACTLR cannot be modified by
> u-boot. has to go to secure world using smc call.
> 
> > +}
> > +
> > +void v7_en_l2_hazard_detect(void);
> >  void v7_outer_cache_enable(void);
> >  void v7_outer_cache_disable(void);
> >  void v7_outer_cache_flush_all(void);
> 
> How about this - using the series:
> https://patchwork.ozlabs.org/patch/443261/                
> https://patchwork.ozlabs.org/patch/443264/                
> https://patchwork.ozlabs.org/patch/443268/                
> https://patchwork.ozlabs.org/patch/443265/                
> https://patchwork.ozlabs.org/patch/443263/                
> https://patchwork.ozlabs.org/patch/443262/                
> https://patchwork.ozlabs.org/patch/443267/                
> https://patchwork.ozlabs.org/patch/443266/                
> https://patchwork.ozlabs.org/patch/443260/                

I think the following might work for exynos?

diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index 83e1dcfc1e13..0157105524ca 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -42,6 +42,23 @@ enum {
 	DO_POWER	= 1 << 4,
 };
 
+#ifdef CONFIG_ARM_ARCH_CP15_ERRATA
+void arch_cp15_errata_workaround(u32 midr, u32 variant, u32 rev, u32 comb)
+{
+#ifdef CONFIG_ARM_ERRATA_798870
+	if (comb >= 0x20 && comb < 0x30) {
+		uint32_t l2actlr;
+
+		mrc_l2_aux_ctlr(l2actlr);
+		/* Disable ACE DVM/CMO message broadcas */
+		l2actlr |= (1 << 7);
+		mcr_l2_aux_ctlr(l2actlr);
+		mrc_l2_ctlr(l2actlr);
+	}
+#endif
+}
+#endif
+
 int do_lowlevel_init(void)
 {
 	uint32_t reset_status;
-- 
Regards,
Nishanth Menon

[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[Kevin Hilman]

Nishanth Menon <nm@ti.com> writes:

> On 13:27-20150220, Akshay Saraswat wrote:
>> This patch adds workaround for ARM errata 798870 which says
>> "If back-to-back speculative cache line fills (fill A and fill B) are
>> issued from the L1 data cache of a CPU to the L2 cache, the second
>> request (fill B) is then cancelled, and the second request would have
>> detected a hazard against a recent write or eviction (write B) to the
>> same cache line as fill B then the L2 logic might deadlock."
>> 
>> Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> Tested-by: Simon Glass <sjg@chromium.org>
>> ---
>> Changes since v3:
>> 	- Added errata number in comment.
>> 	- Moved changes to arm generic armv7.h
>> 
>> Changes since v2:
>> 	- No change.
>> 
>> Changes since v1:
>> 	- Added Reviewed-by & Tested-by.
>> 	- Added space before */ on line # 40.
>> 
>>  arch/arm/include/asm/armv7.h | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>> 
>> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
>> index a13da23..a2040b7 100644
>> --- a/arch/arm/include/asm/armv7.h
>> +++ b/arch/arm/include/asm/armv7.h
>> @@ -69,6 +69,22 @@
>>  #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
>>  #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
>>  
>> +/*
>> + * Workaround for ARM errata # 798870
>> + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
>> + * stalled for 1024 cycles to verify that its hazard condition still exists.
>> + */
>> +static inline void v7_enable_l2_hazard_detect(void)
>> +{
>> +	uint32_t val;
>> +
>> +	/* L2ACTLR[7]: Enable hazard detect timeout */
>> +	asm volatile ("mrc     p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
>> +	val |= (1 << 7);
>> +	asm volatile ("mcr     p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
>
> This wont work for us in DRA7/OMAP5 L2ACTLR cannot be modified by
> u-boot. has to go to secure world using smc call.
>

I believe the same may be true even on some exynos5 platforms with
secure firmware (e.g. exynos5422-odroid-xu3).

Kevin

[U-Boot] [PATCH v4 03/10] Exynos542x: Add workaround for ARM errata 798870

[Nishanth Menon]

On 02/25/2015 01:55 PM, Kevin Hilman wrote:
> Nishanth Menon <nm@ti.com> writes:
> 
>> On 13:27-20150220, Akshay Saraswat wrote:
>>> This patch adds workaround for ARM errata 798870 which says
>>> "If back-to-back speculative cache line fills (fill A and fill B) are
>>> issued from the L1 data cache of a CPU to the L2 cache, the second
>>> request (fill B) is then cancelled, and the second request would have
>>> detected a hazard against a recent write or eviction (write B) to the
>>> same cache line as fill B then the L2 logic might deadlock."
>>>
>>> Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
>>> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
>>> Reviewed-by: Simon Glass <sjg@chromium.org>
>>> Tested-by: Simon Glass <sjg@chromium.org>
>>> ---
>>> Changes since v3:
>>> 	- Added errata number in comment.
>>> 	- Moved changes to arm generic armv7.h
>>>
>>> Changes since v2:
>>> 	- No change.
>>>
>>> Changes since v1:
>>> 	- Added Reviewed-by & Tested-by.
>>> 	- Added space before */ on line # 40.
>>>
>>>  arch/arm/include/asm/armv7.h | 16 ++++++++++++++++
>>>  1 file changed, 16 insertions(+)
>>>
>>> diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
>>> index a13da23..a2040b7 100644
>>> --- a/arch/arm/include/asm/armv7.h
>>> +++ b/arch/arm/include/asm/armv7.h
>>> @@ -69,6 +69,22 @@
>>>  #define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
>>>  #define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
>>>  
>>> +/*
>>> + * Workaround for ARM errata # 798870
>>> + * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
>>> + * stalled for 1024 cycles to verify that its hazard condition still exists.
>>> + */
>>> +static inline void v7_enable_l2_hazard_detect(void)
>>> +{
>>> +	uint32_t val;
>>> +
>>> +	/* L2ACTLR[7]: Enable hazard detect timeout */
>>> +	asm volatile ("mrc     p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
>>> +	val |= (1 << 7);
>>> +	asm volatile ("mcr     p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
>>
>> This wont work for us in DRA7/OMAP5 L2ACTLR cannot be modified by
>> u-boot. has to go to secure world using smc call.
>>
> 
> I believe the same may be true even on some exynos5 platforms with
> secure firmware (e.g. exynos5422-odroid-xu3).


I hope http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213207
should probably help handle for secure and non-secure devices by some
soc specific glue layer (something similar to omap3 perhaps).. I am
not too familiar with exynos family to comment better.


-- 
Regards,
Nishanth Menon