[U-Boot] [PATCH 01/12] imx: iomux-mx51: Fix MX51_PAD_EIM_CS2__GPIO2_27

[U-Boot] [PATCH 01/12] imx: iomux-mx51: Fix MX51_PAD_EIM_CS2__GPIO2_27

[Benoît Thébaudeau]

In ALT1 mode, EIM_CS2 is GPIO2[27], not ESDHC1.CD. Hence, rename
MX51_PAD_EIM_CS2__SD1_CD to MX51_PAD_EIM_CS2__GPIO2_27.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 arch/arm/include/asm/arch-mx5/iomux-mx51.h |    2 +-
 board/genesi/mx51_efikamx/efikamx.c        |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
index 328c188..323e118 100644
--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
@@ -61,7 +61,7 @@ enum {
 	MX51_PAD_EIM_A26__USBH2_STP		= IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_EIM_A27__USBH2_NXT		= IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_EIM_CS0__GPIO2_25		= IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
-	MX51_PAD_EIM_CS2__SD1_CD		= IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_PAD_EIM_CS2__GPIO2_27		= IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_EIM_CS3__GPIO2_28		= IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_EIM_CS4__GPIO2_29		= IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_WE_B__PATA_DIOW		= IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
index 69d41db..13582a2 100644
--- a/board/genesi/mx51_efikamx/efikamx.c
+++ b/board/genesi/mx51_efikamx/efikamx.c
@@ -293,7 +293,7 @@ static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
 
 static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
 	MX51_PAD_GPIO1_0__SD1_CD,
-	MX51_PAD_EIM_CS2__SD1_CD,
+	NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
 };
 
 #define EFIKAMX_SDHC1_CD	IMX_GPIO_NR(1, 0)
-- 
1.7.10.4

[U-Boot] [PATCH 02/12] imx: iomux-v3: Add missing definitions to iomux-mx51.h

[Benoît Thébaudeau]

Add missing definitions that are required by future changes.

By the way, make some cosmetic cleanup.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 arch/arm/include/asm/arch-mx5/iomux-mx51.h |  151 +++++++++++++++++++++++-----
 1 file changed, 124 insertions(+), 27 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
index 323e118..70aaa37 100644
--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
@@ -22,7 +22,7 @@
 #include <asm/imx-common/iomux-v3.h>
 
 /* Pad control groupings */
-#define MX51_UART_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+#define MX51_UART_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
 				PAD_CTL_HYS | PAD_CTL_SRE_FAST)
 #define MX51_I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
 				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
@@ -30,7 +30,7 @@
 #define MX51_ESDHC_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
 				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
 				PAD_CTL_HYS)
-#define MX51_USBH1_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+#define MX51_USBH_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 				PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
 #define MX51_ECSPI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_HYS | \
 				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
@@ -38,32 +38,67 @@
 				PAD_CTL_SRE_FAST | PAD_CTL_DVS)
 #define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
 
+#define MX51_PAD_CTRL_2		(PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_4		(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5		(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
  * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
  * See also iomux-v3.h
  */
 
-/*								PAD    MUX   ALT INPSE PATH PADCTRL */
+/*							    PAD    MUX   ALT INPSE PATH PADCTRL */
 enum {
-	MX51_PAD_EIM_D16__USBH2_DATA0		= IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D17__USBH2_DATA1		= IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D18__USBH2_DATA2		= IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D19__USBH2_DATA3		= IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D20__USBH2_DATA4		= IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D21__USBH2_DATA5		= IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D22__USBH2_DATA6		= IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_D23__USBH2_DATA7		= IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_D16__USBH2_DATA0		= IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D17__GPIO2_1		= IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_D17__USBH2_DATA1		= IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D18__USBH2_DATA2		= IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D19__USBH2_DATA3		= IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D20__USBH2_DATA4		= IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D21__GPIO2_5		= IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_D21__USBH2_DATA5		= IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D22__USBH2_DATA6		= IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D23__USBH2_DATA7		= IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D25__UART3_RXD		= IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_EIM_D26__UART3_TXD		= IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
 	MX51_PAD_EIM_D27__GPIO2_9		= IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
-	MX51_PAD_EIM_A24__USBH2_CLK		= IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_A25__USBH2_DIR		= IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_A16__GPIO2_10		= IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A17__GPIO2_11		= IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A20__GPIO2_14		= IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A22__GPIO2_16		= IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A24__USBH2_CLK		= IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_A25__USBH2_DIR		= IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
 	MX51_PAD_EIM_A26__GPIO2_20		= IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
-	MX51_PAD_EIM_A26__USBH2_STP		= IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL),
-	MX51_PAD_EIM_A27__USBH2_NXT		= IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_A26__USBH2_STP		= IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_A27__USBH2_NXT		= IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_EB2__FEC_MDIO		= IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
+	MX51_PAD_EIM_EB3__FEC_RDATA1		= IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_EB3__GPIO2_23		= IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_EIM_CS0__GPIO2_25		= IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS2__FEC_RDATA2		= IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
 	MX51_PAD_EIM_CS2__GPIO2_27		= IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS3__FEC_RDATA3		= IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
 	MX51_PAD_EIM_CS3__GPIO2_28		= IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS4__FEC_RX_ER		= IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
 	MX51_PAD_EIM_CS4__GPIO2_29		= IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS5__FEC_CRS		= IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_DRAM_RAS__DRAM_RAS		= IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CAS__DRAM_CAS		= IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDWE__DRAM_SDWE		= IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0	= IOMUX_PAD(0x4b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1	= IOMUX_PAD(0x4b4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCLK__DRAM_SDCLK		= IOMUX_PAD(0x4b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS0__DRAM_SDQS0		= IOMUX_PAD(0x4bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS1__DRAM_SDQS1		= IOMUX_PAD(0x4c0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS2__DRAM_SDQS2		= IOMUX_PAD(0x4c4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS3__DRAM_SDQS3		= IOMUX_PAD(0x4c8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CS0__DRAM_CS0		= IOMUX_PAD(0x4cc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CS1__DRAM_CS1		= IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM0__DRAM_DQM0		= IOMUX_PAD(0x4d4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM1__DRAM_DQM1		= IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM2__DRAM_DQM2		= IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM3__DRAM_DQM3		= IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_WE_B__PATA_DIOW		= IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_RE_B__PATA_DIOR		= IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_ALE__PATA_BUFFER_EN	= IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
@@ -71,19 +106,38 @@ enum {
 	MX51_PAD_NANDF_WP_B__PATA_DMACK		= IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_RB0__PATA_DMARQ		= IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_RB1__PATA_IORDY		= IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_RB2__FEC_COL		= IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_NANDF_RB2__GPIO3_10		= IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_RB3__FEC_RX_CLK		= IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_NANDF_RB3__GPIO3_11		= IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_GPIO_NAND__PATA_INTRQ		= IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS2__FEC_TX_ER		= IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_CS2__PATA_CS_0		= IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS3__FEC_MDC		= IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_CS3__PATA_CS_1		= IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS4__FEC_TDATA1		= IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_CS4__PATA_DA_0		= IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS5__FEC_TDATA2		= IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_CS5__PATA_DA_1		= IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS6__FEC_TDATA3		= IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_CS6__PATA_DA_2		= IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS7__FEC_TX_EN		= IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	= IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
+	MX51_PAD_NANDF_D15__GPIO3_25		= IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_D15__PATA_DATA15		= IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D14__GPIO3_26		= IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_D14__PATA_DATA14		= IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D13__GPIO3_27		= IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_D13__PATA_DATA13		= IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D12__PATA_DATA12		= IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D11__FEC_RX_DV		= IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D11__PATA_DATA11		= IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D10__GPIO3_30		= IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_D10__PATA_DATA10		= IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D9__FEC_RDATA0		= IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4),
+	MX51_PAD_NANDF_D9__GPIO3_31		= IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_NANDF_D9__PATA_DATA9		= IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D8__FEC_TDATA0		= IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5),
 	MX51_PAD_NANDF_D8__PATA_DATA8		= IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D7__PATA_DATA7		= IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D6__PATA_DATA6		= IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
@@ -93,34 +147,52 @@ enum {
 	MX51_PAD_NANDF_D2__PATA_DATA2		= IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D1__PATA_DATA1		= IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_NANDF_D0__PATA_DATA0		= IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_CSI2_D12__GPIO4_9		= IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSI2_D13__GPIO4_10		= IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	= IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
 	MX51_PAD_CSPI1_MISO__ECSPI1_MISO	= IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_SS0__ECSPI1_SS0		= IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
 	MX51_PAD_CSPI1_SS0__GPIO4_24		= IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_SS1__ECSPI1_SS1		= IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
 	MX51_PAD_CSPI1_SS1__GPIO4_25		= IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_RDY__ECSPI1_RDY		= IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_RDY__GPIO4_26		= IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	= IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
 	MX51_PAD_UART1_RXD__UART1_RXD		= IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL),
 	MX51_PAD_UART1_TXD__UART1_TXD		= IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
 	MX51_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
 	MX51_PAD_UART1_CTS__UART1_CTS		= IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
-	MX51_PAD_USBH1_CLK__USBH1_CLK		= IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DIR__USBH1_DIR		= IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_STP__USBH1_STP		= IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+	MX51_PAD_USBH1_CLK__USBH1_CLK		= IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DIR__USBH1_DIR		= IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
 	MX51_PAD_USBH1_STP__GPIO1_27		= IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
-	MX51_PAD_USBH1_NXT__USBH1_NXT		= IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA0__USBH1_DATA0	= IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA1__USBH1_DATA1	= IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA2__USBH1_DATA2	= IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA3__USBH1_DATA3	= IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA4__USBH1_DATA4	= IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA5__USBH1_DATA5	= IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA6__USBH1_DATA6	= IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
-	MX51_PAD_USBH1_DATA7__USBH1_DATA7	= IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+	MX51_PAD_USBH1_STP__USBH1_STP		= IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_NXT__USBH1_NXT		= IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA0__USBH1_DATA0	= IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA1__USBH1_DATA1	= IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA2__USBH1_DATA2	= IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA3__USBH1_DATA3	= IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA4__USBH1_DATA4	= IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA5__USBH1_DATA5	= IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA6__USBH1_DATA6	= IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA7__USBH1_DATA7	= IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_DI1_PIN11__ECSPI1_SS2		= IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_DI1_PIN12__GPIO3_1		= IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_PIN13__GPIO3_2		= IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_D0_CS__GPIO3_3		= IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_D1_CS__GPIO3_4		= IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DISPB2_SER_DIN__GPIO3_5	= IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DISPB2_SER_DIO__GPIO3_6	= IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_PIN3__DI1_PIN3		= IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI1_PIN2__DI1_PIN2		= IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	= IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI_GP4__DI2_PIN15		= IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_SD1_CMD__SD1_CMD		= IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD1_CLK__SD1_CLK		= IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
 	MX51_PAD_SD1_DATA0__SD1_DATA0		= IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD1_DATA1__SD1_DATA1		= IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD1_DATA2__SD1_DATA2		= IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD1_DATA3__SD1_DATA3		= IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_GPIO1_0__GPIO1_0		= IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_GPIO1_0__SD1_CD		= IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
 	MX51_PAD_GPIO1_1__SD1_WP		= IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
 	MX51_PAD_SD2_CMD__SD2_CMD		= IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
@@ -129,11 +201,36 @@ enum {
 	MX51_PAD_SD2_DATA1__SD2_DATA1		= IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD2_DATA2__SD2_DATA2		= IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
 	MX51_PAD_SD2_DATA3__SD2_DATA3		= IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_GPIO1_2__GPIO1_2		= IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_2__PWM1_PWMO		= IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL),
 	MX51_PAD_GPIO1_3__GPIO1_3		= IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_GPIO1_5__GPIO1_5		= IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_GPIO1_6__GPIO1_6		= IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_7__GPIO1_7		= IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
 	MX51_PAD_GPIO1_7__SD2_WP		= IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
 	MX51_PAD_GPIO1_8__SD2_CD		= IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_GRP_DDRPKS				= IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B4			= IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_PKEDDR				= IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_A0				= IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_A1				= IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRAPUS			= IOMUX_PAD(0x84c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR0			= IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR1			= IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR2			= IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR3			= IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B0			= IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRAPKS			= IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B1			= IOMUX_PAD(0x880, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRPUS				= IOMUX_PAD(0x884, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B2			= IOMUX_PAD(0x88c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_PKEADDR			= IOMUX_PAD(0x890, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B4			= IOMUX_PAD(0x89c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_INMODE1			= IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B0			= IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B1			= IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B2			= IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_SR_A1			= IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
 };
 
 #endif /* __IOMUX_MX51_H__ */
-- 
1.7.10.4

[U-Boot] [PATCH 03/12] imx: mx51evk: Convert to iomux-v3

[Benoît Thébaudeau]

There is no change of behavior, except for older silicon revisions for which
support is removed.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 board/freescale/mx51evk/mx51evk.c       |  348 +++++++++++--------------------
 board/freescale/mx51evk/mx51evk_video.c |   22 +-
 2 files changed, 131 insertions(+), 239 deletions(-)

diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 54c16b1..369da6d 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -24,8 +24,7 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
@@ -64,160 +63,103 @@ u32 get_board_rev(void)
 	return rev;
 }
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
+
 static void setup_iomux_uart(void)
 {
-	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-			PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
-
-	mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
-	mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
-	mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
-	mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		MX51_PAD_UART1_RXD__UART1_RXD,
+		MX51_PAD_UART1_TXD__UART1_TXD,
+		NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 static void setup_iomux_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
-
-	/*FEC_MDC*/
-	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
-
-	/* FEC RDATA[3] */
-	mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
-
-	/* FEC RDATA[2] */
-	mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
-
-	/* FEC RDATA[1] */
-	mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
-
-	/* FEC RDATA[0] */
-	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
-
-	/* FEC TDATA[3] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
-
-	/* FEC TDATA[2] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
-
-	/* FEC TDATA[1] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
-
-	/* FEC TDATA[0] */
-	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
-
-	/* FEC TX_ER */
-	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
-
-	/* FEC TX_COL */
-	mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
-
-	/* FEC RX_CLK */
-	mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
-
-	/* FEC RX_CRS */
-	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
-
-	/* FEC RX_DV */
-	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
+				PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		MX51_PAD_NANDF_CS3__FEC_MDC,
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+		MX51_PAD_NANDF_D9__FEC_RDATA0,
+		MX51_PAD_NANDF_CS6__FEC_TDATA3,
+		MX51_PAD_NANDF_CS5__FEC_TDATA2,
+		MX51_PAD_NANDF_CS4__FEC_TDATA1,
+		MX51_PAD_NANDF_D8__FEC_TDATA0,
+		MX51_PAD_NANDF_CS7__FEC_TX_EN,
+		MX51_PAD_NANDF_CS2__FEC_TX_ER,
+		MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+		MX51_PAD_EIM_CS5__FEC_CRS,
+		MX51_PAD_EIM_CS4__FEC_RX_ER,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 #ifdef CONFIG_MXC_SPI
 static void setup_iomux_spi(void)
 {
-	/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
-	mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
-
-	/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
-
-	/* de-select SS1 of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
-
-	/* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
-	mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
-
-	/* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
-
-	/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
+	static const iomux_v3_cfg_t spi_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
+				MX51_GPIO_PAD_CTRL),
+		MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 }
 #endif
 
 #ifdef CONFIG_USB_EHCI_MX5
-#define MX51EVK_USBH1_HUB_RST	IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
-#define MX51EVK_USBH1_STP	IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
-#define MX51EVK_USB_CLK_EN_B	IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
-#define MX51EVK_USB_PHY_RESET	IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
-
-#define USBH1_PAD	(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |		\
-			 PAD_CTL_100K_PU | PAD_CTL_PUE_PULL |		\
-			 PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
-#define GPIO_PAD	(PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE |	\
-			 PAD_CTL_SRE_FAST)
-#define NO_PAD		(1 << 16)
+#define MX51EVK_USBH1_HUB_RST	IMX_GPIO_NR(1, 7)
+#define MX51EVK_USBH1_STP	IMX_GPIO_NR(1, 27)
+#define MX51EVK_USB_CLK_EN_B	IMX_GPIO_NR(2, 2)
+#define MX51EVK_USB_PHY_RESET	IMX_GPIO_NR(2, 5)
 
 static void setup_usb_h1(void)
 {
-	setup_iomux_usb_h1();
-
-	/* GPIO_1_7 for USBH1 hub reset */
-	mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
-
-	/* GPIO_2_1 */
-	mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
-
-	/* GPIO_2_5 for USB PHY reset */
-	mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
+	static const iomux_v3_cfg_t usb_h1_pads[] = {
+		MX51_PAD_USBH1_CLK__USBH1_CLK,
+		MX51_PAD_USBH1_DIR__USBH1_DIR,
+		MX51_PAD_USBH1_STP__USBH1_STP,
+		MX51_PAD_USBH1_NXT__USBH1_NXT,
+		MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+		MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+		MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+		MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+		MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+		MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+		MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+		MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
+		MX51_PAD_EIM_D17__GPIO2_1,
+		MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
+	};
+
+	imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
 }
 
 int board_ehci_hcd_init(int port)
 {
 	/* Set USBH1_STP to GPIO and toggle it */
-	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
+						MX51_USBH_PAD_CTRL));
 
 	gpio_direction_output(MX51EVK_USBH1_STP, 0);
 	gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
@@ -225,8 +167,7 @@ int board_ehci_hcd_init(int port)
 	gpio_set_value(MX51EVK_USBH1_STP, 1);
 
 	/* Set back USBH1_STP to be function */
-	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
+	imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
 
 	/* De-assert USB PHY RESETB */
 	gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
@@ -328,7 +269,8 @@ static void power_init(void)
 		VVIDEOEN | VAUDIOEN  | VSDEN;
 	pmic_reg_write(p, REG_MODE_1, val);
 
-	mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
+						NO_PAD_CTRL));
 	gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
 
 	udelay(500);
@@ -342,9 +284,11 @@ int board_mmc_getcd(struct mmc *mmc)
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret;
 
-	mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
+						NO_PAD_CTRL));
 	gpio_direction_input(IMX_GPIO_NR(1, 0));
-	mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
+						NO_PAD_CTRL));
 	gpio_direction_input(IMX_GPIO_NR(1, 6));
 
 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
@@ -357,6 +301,40 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
+			PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
+	};
+
+	static const iomux_v3_cfg_t sd2_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
+	};
+
 	u32 index;
 	s32 status = 0;
 
@@ -367,98 +345,12 @@ int board_mmc_init(bd_t *bis)
 			index++) {
 		switch (index) {
 		case 0:
-			mxc_request_iomux(MX51_PIN_SD1_CMD,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD1_CLK,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD1_DATA0,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD1_DATA1,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD1_DATA2,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD1_DATA3,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
-				PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
-				PAD_CTL_PUE_PULL |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-			mxc_request_iomux(MX51_PIN_GPIO1_0,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
-				PAD_CTL_HYS_ENABLE);
-			mxc_request_iomux(MX51_PIN_GPIO1_1,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
-				PAD_CTL_HYS_ENABLE);
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
 			break;
 		case 1:
-			mxc_request_iomux(MX51_PIN_SD2_CMD,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD2_CLK,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_SD2_DATA0,
-				IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX51_PIN_SD2_DATA1,
-				IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX51_PIN_SD2_DATA2,
-				IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX51_PIN_SD2_DATA3,
-				IOMUX_CONFIG_ALT0);
-			mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
-				PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
-				PAD_CTL_SRE_FAST);
-			mxc_request_iomux(MX51_PIN_SD2_CMD,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX51_PIN_GPIO1_6,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
-				PAD_CTL_HYS_ENABLE);
-			mxc_request_iomux(MX51_PIN_GPIO1_5,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
-				PAD_CTL_HYS_ENABLE);
+			imx_iomux_v3_setup_multiple_pads(sd2_pads,
+							 ARRAY_SIZE(sd2_pads));
 			break;
 		default:
 			printf("Warning: you configured more ESDHC controller"
diff --git a/board/freescale/mx51evk/mx51evk_video.c b/board/freescale/mx51evk/mx51evk_video.c
index 7be5c9b..556cb38 100644
--- a/board/freescale/mx51evk/mx51evk_video.c
+++ b/board/freescale/mx51evk/mx51evk_video.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <linux/list.h>
 #include <asm/gpio.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
 
@@ -67,25 +67,25 @@ static struct fb_videomode const dvi = {
 void setup_iomux_lcd(void)
 {
 	/* DI2_PIN15 */
-	mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4);
+	imx_iomux_v3_setup_pad(MX51_PAD_DI_GP4__DI2_PIN15);
 
-	/* Pad settings for MX51_PIN_DI2_DISP_CLK */
-	mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE |
-			  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-			  PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW);
+	/* Pad settings for DI2_DISP_CLK */
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK,
+			    PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW));
 
 	/* Turn on 3.3V voltage for LCD */
-	mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D12__GPIO4_9,
+						NO_PAD_CTRL));
 	gpio_direction_output(MX51EVK_LCD_3V3, 1);
 
 	/* Turn on 5V voltage for LCD */
-	mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D13__GPIO4_10,
+						NO_PAD_CTRL));
 	gpio_direction_output(MX51EVK_LCD_5V, 1);
 
 	/* Turn on GPIO backlight */
-	mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
-							INPUT_CTL_PATH1);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4,
+						NO_PAD_CTRL));
 	gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
 }
 
-- 
1.7.10.4

[U-Boot] [PATCH 04/12] imx: mx51_efikamx/sb: Convert to iomux-v3

[Benoît Thébaudeau]

There is no change of behavior, except for older silicon revisions for which
support is removed.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 board/genesi/mx51_efikamx/efikamx-usb.c |  122 +++++++++++++++++--------------
 1 file changed, 69 insertions(+), 53 deletions(-)

diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c
index cf020c3..cabad70 100644
--- a/board/genesi/mx51_efikamx/efikamx-usb.c
+++ b/board/genesi/mx51_efikamx/efikamx-usb.c
@@ -26,8 +26,7 @@
 #include <usb.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
 #include <asm/gpio.h>
 #include <usb/ehci-fsl.h>
 #include <usb/ulpi.h>
@@ -35,40 +34,57 @@
 
 #include "../../../drivers/usb/host/ehci.h"
 
-/* USB pin configuration */
-#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
-			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
-
 /*
  * Configure the USB H1 and USB H2 IOMUX
  */
 void setup_iomux_usb(void)
 {
-	setup_iomux_usb_h1();
-
-	if (machine_is_efikasb())
-		setup_iomux_usb_h2();
-
-	/* USB PHY reset */
-	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
-			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
-
-	/* USB HUB reset */
-	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
-			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
-
-	/* WIFI EN (act low) */
-	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
-	/* WIFI RESET */
-	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
-	/* BT EN (act low) */
-	mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+	static const iomux_v3_cfg_t usb_h1_pads[] = {
+		MX51_PAD_USBH1_CLK__USBH1_CLK,
+		MX51_PAD_USBH1_DIR__USBH1_DIR,
+		MX51_PAD_USBH1_STP__USBH1_STP,
+		MX51_PAD_USBH1_NXT__USBH1_NXT,
+		MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+		MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+		MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+		MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+		MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+		MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+		MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+		MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+	};
+
+	static const iomux_v3_cfg_t usb_pads[] = {
+		MX51_PAD_EIM_D27__GPIO2_9, /* USB PHY reset */
+		MX51_PAD_GPIO1_5__GPIO1_5, /* USB HUB reset */
+		NEW_PAD_CTRL(MX51_PAD_EIM_A22__GPIO2_16, 0), /* WIFI /EN */
+		NEW_PAD_CTRL(MX51_PAD_EIM_A16__GPIO2_10, 0), /* WIFI RESET */
+		NEW_PAD_CTRL(MX51_PAD_EIM_A17__GPIO2_11, 0), /* BT /EN */
+	};
+
+	imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
+
+	if (machine_is_efikasb()) {
+		static const iomux_v3_cfg_t usb_h2_pads[] = {
+			MX51_PAD_EIM_A24__USBH2_CLK,
+			MX51_PAD_EIM_A25__USBH2_DIR,
+			MX51_PAD_EIM_A26__USBH2_STP,
+			MX51_PAD_EIM_A27__USBH2_NXT,
+			MX51_PAD_EIM_D16__USBH2_DATA0,
+			MX51_PAD_EIM_D17__USBH2_DATA1,
+			MX51_PAD_EIM_D18__USBH2_DATA2,
+			MX51_PAD_EIM_D19__USBH2_DATA3,
+			MX51_PAD_EIM_D20__USBH2_DATA4,
+			MX51_PAD_EIM_D21__USBH2_DATA5,
+			MX51_PAD_EIM_D22__USBH2_DATA6,
+			MX51_PAD_EIM_D23__USBH2_DATA7,
+		};
+
+		imx_iomux_v3_setup_multiple_pads(usb_h2_pads,
+						 ARRAY_SIZE(usb_h2_pads));
+	}
+
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 }
 
 /*
@@ -77,18 +93,18 @@ void setup_iomux_usb(void)
 static void efika_usb_enable_devices(void)
 {
 	/* Enable Bluetooth */
-	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+	gpio_direction_output(IMX_GPIO_NR(2, 11), 0);
 	udelay(10000);
-	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+	gpio_set_value(IMX_GPIO_NR(2, 11), 1);
 
 	/* Enable WiFi */
-	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+	gpio_direction_output(IMX_GPIO_NR(2, 16), 1);
 	udelay(10000);
 
 	/* Reset the WiFi chip */
-	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+	gpio_direction_output(IMX_GPIO_NR(2, 10), 0);
 	udelay(10000);
-	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+	gpio_set_value(IMX_GPIO_NR(2, 10), 1);
 }
 
 /*
@@ -97,11 +113,11 @@ static void efika_usb_enable_devices(void)
 static void efika_usb_hub_reset(void)
 {
 	/* HUB reset */
-	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
 	udelay(1000);
-	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+	gpio_set_value(IMX_GPIO_NR(1, 5), 0);
 	udelay(1000);
-	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	gpio_set_value(IMX_GPIO_NR(1, 5), 1);
 }
 
 /*
@@ -110,28 +126,26 @@ static void efika_usb_hub_reset(void)
 static void efika_usb_phy_reset(void)
 {
 	/* SMSC 3317 PHY reset */
-	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+	gpio_direction_output(IMX_GPIO_NR(2, 9), 0);
 	udelay(1000);
-	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+	gpio_set_value(IMX_GPIO_NR(2, 9), 1);
 }
 
 static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio,
-				uint32_t alt0, uint32_t alt1)
+				iomux_v3_cfg_t stp_pad_gpio,
+				iomux_v3_cfg_t stp_pad_usb)
 {
 	int ret;
 	struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
 	struct ulpi_viewport ulpi_vp;
 
-	mxc_request_iomux(stp_gpio, alt0);
-	mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH |
-				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0);
+	imx_iomux_v3_setup_pad(stp_pad_gpio);
+	gpio_direction_output(stp_gpio, 0);
 	udelay(1000);
-	gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1);
+	gpio_set_value(stp_gpio, 1);
 	udelay(1000);
 
-	mxc_request_iomux(stp_gpio, alt1);
-	mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG);
+	imx_iomux_v3_setup_pad(stp_pad_usb);
 	udelay(10000);
 
 	ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
@@ -204,11 +218,13 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
 		tmp = (tmp & ~0x3) | 0x01;
 		writel(tmp, OTG_BASE_ADDR + 0x80c);
 	} else if (port == 1) {
-		efika_ehci_init(ehci, MX51_PIN_USBH1_STP,
-				IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0);
+		efika_ehci_init(ehci, IMX_GPIO_NR(1, 27),
+				MX51_PAD_USBH1_STP__GPIO1_27,
+				MX51_PAD_USBH1_STP__USBH1_STP);
 	} else if ((port == 2) && machine_is_efikasb()) {
-		efika_ehci_init(ehci, MX51_PIN_EIM_A26,
-				IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2);
+		efika_ehci_init(ehci, IMX_GPIO_NR(2, 20),
+				MX51_PAD_EIM_A26__GPIO2_20,
+				MX51_PAD_EIM_A26__USBH2_STP);
 	}
 
 	if (port)
-- 
1.7.10.4

[U-Boot] [PATCH 04/12] imx: mx51_efikamx/sb: Convert to iomux-v3

[Matt Sealey]

I had a patch queued which did exactly this, but I am fine with
someone else doing it ;)

Tested works exactly the same.

Signed-off-by: Matt Sealey <matt@genesi-usa.com>

On Thu, May 2, 2013 at 3:52 PM, Beno?t Th?baudeau
<benoit.thebaudeau@advansee.com> wrote:
> There is no change of behavior, except for older silicon revisions for which
> support is removed.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> ---
>  board/genesi/mx51_efikamx/efikamx-usb.c |  122 +++++++++++++++++--------------
>  1 file changed, 69 insertions(+), 53 deletions(-)
>
> diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c
> index cf020c3..cabad70 100644
> --- a/board/genesi/mx51_efikamx/efikamx-usb.c
> +++ b/board/genesi/mx51_efikamx/efikamx-usb.c
> @@ -26,8 +26,7 @@
>  #include <usb.h>
>  #include <asm/io.h>
>  #include <asm/arch/imx-regs.h>
> -#include <asm/arch/mx5x_pins.h>
> -#include <asm/arch/iomux.h>
> +#include <asm/arch/iomux-mx51.h>
>  #include <asm/gpio.h>
>  #include <usb/ehci-fsl.h>
>  #include <usb/ulpi.h>
> @@ -35,40 +34,57 @@
>
>  #include "../../../drivers/usb/host/ehci.h"
>
> -/* USB pin configuration */
> -#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
> -                       PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
> -                       PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
> -
>  /*
>   * Configure the USB H1 and USB H2 IOMUX
>   */
>  void setup_iomux_usb(void)
>  {
> -       setup_iomux_usb_h1();
> -
> -       if (machine_is_efikasb())
> -               setup_iomux_usb_h2();
> -
> -       /* USB PHY reset */
> -       mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
> -       mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
> -                       PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
> -
> -       /* USB HUB reset */
> -       mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
> -       mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
> -                       PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
> -
> -       /* WIFI EN (act low) */
> -       mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
> -       mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
> -       /* WIFI RESET */
> -       mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
> -       mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
> -       /* BT EN (act low) */
> -       mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
> -       mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
> +       static const iomux_v3_cfg_t usb_h1_pads[] = {
> +               MX51_PAD_USBH1_CLK__USBH1_CLK,
> +               MX51_PAD_USBH1_DIR__USBH1_DIR,
> +               MX51_PAD_USBH1_STP__USBH1_STP,
> +               MX51_PAD_USBH1_NXT__USBH1_NXT,
> +               MX51_PAD_USBH1_DATA0__USBH1_DATA0,
> +               MX51_PAD_USBH1_DATA1__USBH1_DATA1,
> +               MX51_PAD_USBH1_DATA2__USBH1_DATA2,
> +               MX51_PAD_USBH1_DATA3__USBH1_DATA3,
> +               MX51_PAD_USBH1_DATA4__USBH1_DATA4,
> +               MX51_PAD_USBH1_DATA5__USBH1_DATA5,
> +               MX51_PAD_USBH1_DATA6__USBH1_DATA6,
> +               MX51_PAD_USBH1_DATA7__USBH1_DATA7,
> +       };
> +
> +       static const iomux_v3_cfg_t usb_pads[] = {
> +               MX51_PAD_EIM_D27__GPIO2_9, /* USB PHY reset */
> +               MX51_PAD_GPIO1_5__GPIO1_5, /* USB HUB reset */
> +               NEW_PAD_CTRL(MX51_PAD_EIM_A22__GPIO2_16, 0), /* WIFI /EN */
> +               NEW_PAD_CTRL(MX51_PAD_EIM_A16__GPIO2_10, 0), /* WIFI RESET */
> +               NEW_PAD_CTRL(MX51_PAD_EIM_A17__GPIO2_11, 0), /* BT /EN */
> +       };
> +
> +       imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
> +
> +       if (machine_is_efikasb()) {
> +               static const iomux_v3_cfg_t usb_h2_pads[] = {
> +                       MX51_PAD_EIM_A24__USBH2_CLK,
> +                       MX51_PAD_EIM_A25__USBH2_DIR,
> +                       MX51_PAD_EIM_A26__USBH2_STP,
> +                       MX51_PAD_EIM_A27__USBH2_NXT,
> +                       MX51_PAD_EIM_D16__USBH2_DATA0,
> +                       MX51_PAD_EIM_D17__USBH2_DATA1,
> +                       MX51_PAD_EIM_D18__USBH2_DATA2,
> +                       MX51_PAD_EIM_D19__USBH2_DATA3,
> +                       MX51_PAD_EIM_D20__USBH2_DATA4,
> +                       MX51_PAD_EIM_D21__USBH2_DATA5,
> +                       MX51_PAD_EIM_D22__USBH2_DATA6,
> +                       MX51_PAD_EIM_D23__USBH2_DATA7,
> +               };
> +
> +               imx_iomux_v3_setup_multiple_pads(usb_h2_pads,
> +                                                ARRAY_SIZE(usb_h2_pads));
> +       }
> +
> +       imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
>  }
>
>  /*
> @@ -77,18 +93,18 @@ void setup_iomux_usb(void)
>  static void efika_usb_enable_devices(void)
>  {
>         /* Enable Bluetooth */
> -       gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
> +       gpio_direction_output(IMX_GPIO_NR(2, 11), 0);
>         udelay(10000);
> -       gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
> +       gpio_set_value(IMX_GPIO_NR(2, 11), 1);
>
>         /* Enable WiFi */
> -       gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
> +       gpio_direction_output(IMX_GPIO_NR(2, 16), 1);
>         udelay(10000);
>
>         /* Reset the WiFi chip */
> -       gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
> +       gpio_direction_output(IMX_GPIO_NR(2, 10), 0);
>         udelay(10000);
> -       gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
> +       gpio_set_value(IMX_GPIO_NR(2, 10), 1);
>  }
>
>  /*
> @@ -97,11 +113,11 @@ static void efika_usb_enable_devices(void)
>  static void efika_usb_hub_reset(void)
>  {
>         /* HUB reset */
> -       gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
> +       gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
>         udelay(1000);
> -       gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
> +       gpio_set_value(IMX_GPIO_NR(1, 5), 0);
>         udelay(1000);
> -       gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
> +       gpio_set_value(IMX_GPIO_NR(1, 5), 1);
>  }
>
>  /*
> @@ -110,28 +126,26 @@ static void efika_usb_hub_reset(void)
>  static void efika_usb_phy_reset(void)
>  {
>         /* SMSC 3317 PHY reset */
> -       gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
> +       gpio_direction_output(IMX_GPIO_NR(2, 9), 0);
>         udelay(1000);
> -       gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
> +       gpio_set_value(IMX_GPIO_NR(2, 9), 1);
>  }
>
>  static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio,
> -                               uint32_t alt0, uint32_t alt1)
> +                               iomux_v3_cfg_t stp_pad_gpio,
> +                               iomux_v3_cfg_t stp_pad_usb)
>  {
>         int ret;
>         struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
>         struct ulpi_viewport ulpi_vp;
>
> -       mxc_request_iomux(stp_gpio, alt0);
> -       mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH |
> -                               PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> -       gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0);
> +       imx_iomux_v3_setup_pad(stp_pad_gpio);
> +       gpio_direction_output(stp_gpio, 0);
>         udelay(1000);
> -       gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1);
> +       gpio_set_value(stp_gpio, 1);
>         udelay(1000);
>
> -       mxc_request_iomux(stp_gpio, alt1);
> -       mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG);
> +       imx_iomux_v3_setup_pad(stp_pad_usb);
>         udelay(10000);
>
>         ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
> @@ -204,11 +218,13 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
>                 tmp = (tmp & ~0x3) | 0x01;
>                 writel(tmp, OTG_BASE_ADDR + 0x80c);
>         } else if (port == 1) {
> -               efika_ehci_init(ehci, MX51_PIN_USBH1_STP,
> -                               IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0);
> +               efika_ehci_init(ehci, IMX_GPIO_NR(1, 27),
> +                               MX51_PAD_USBH1_STP__GPIO1_27,
> +                               MX51_PAD_USBH1_STP__USBH1_STP);
>         } else if ((port == 2) && machine_is_efikasb()) {
> -               efika_ehci_init(ehci, MX51_PIN_EIM_A26,
> -                               IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2);
> +               efika_ehci_init(ehci, IMX_GPIO_NR(2, 20),
> +                               MX51_PAD_EIM_A26__GPIO2_20,
> +                               MX51_PAD_EIM_A26__USBH2_STP);
>         }
>
>         if (port)
> --
> 1.7.10.4
>



-- 
Matt Sealey <matt@genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.

[U-Boot] [PATCH 04/12] imx: mx51_efikamx/sb: Convert to iomux-v3

[Benoît Thébaudeau]

On Friday, May 3, 2013 5:58:24 PM, Matt Sealey wrote:
> I had a patch queued which did exactly this, but I am fine with
> someone else doing it ;)
> 
> Tested works exactly the same.
> 
> Signed-off-by: Matt Sealey <matt@genesi-usa.com>

You probably mean "Tested-by".

Best regards,
Beno?t

[U-Boot] [PATCH 04/12] imx: mx51_efikamx/sb: Convert to iomux-v3

[Matt Sealey]

I mean Signed-off-by since I'm the maintainer on the file you changed
and I put the iomux-v3 support in the tree in the first place so I'm
in the delivery path of the patch ;)

Sure, I tested it, otherwise I wouldn't be totally fine with it. But
this is code I have to look after in the future... so I'm signing off
on it.

On Fri, May 3, 2013 at 11:01 AM, Beno?t Th?baudeau
<benoit.thebaudeau@advansee.com> wrote:
> On Friday, May 3, 2013 5:58:24 PM, Matt Sealey wrote:
>> I had a patch queued which did exactly this, but I am fine with
>> someone else doing it ;)
>>
>> Tested works exactly the same.
>>
>> Signed-off-by: Matt Sealey <matt@genesi-usa.com>
>
> You probably mean "Tested-by".
>
> Best regards,
> Beno?t



-- 
Matt Sealey <matt@genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.

[U-Boot] [PATCH 04/12] imx: mx51_efikamx/sb: Convert to iomux-v3

[Benoît Thébaudeau]

Hi Matt,

On Thursday, May 16, 2013 8:05:22 PM, Matt Sealey wrote:
> I mean Signed-off-by since I'm the maintainer on the file you changed
> and I put the iomux-v3 support in the tree in the first place so I'm
> in the delivery path of the patch ;)
> 
> Sure, I tested it, otherwise I wouldn't be totally fine with it. But
> this is code I have to look after in the future... so I'm signing off
> on it.

It's not how the rules in U-Boot work. See:
http://www.denx.de/wiki/view/U-Boot/Patches#Review_Process_Git_Tags
;)

Only the people directly involved in the development of a patch may add their
SoB line, not custodians, not maintainers, not people in its delivery path if
they have not changed anything, and not authors of previous commits of related
code.

And being the author of previous commits on which a new patch depends has
nothing to do with being in the delivery path of this patch.

Hence, the only options that you have in this particular case are Reviewed-by,
Acked-by (I think that this one is also available to maintainers, not only to
custodians), and Tested-by.

Best regards,
Beno?t

[U-Boot] [PATCH 05/12] imx: vision2: Convert to iomux-v3

[Benoît Thébaudeau]

There is no change of behavior, except for older silicon revisions for which
support is removed.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 board/ttcontrol/vision2/vision2.c |  585 ++++++++++++++-----------------------
 1 file changed, 223 insertions(+), 362 deletions(-)

diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index a471fec..9cc758a 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -26,10 +26,9 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx51.h>
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
 #include <i2c.h>
@@ -68,85 +67,67 @@ void hw_watchdog_reset(void)
 	int val;
 
 	/* toggle watchdog trigger pin */
-	val = gpio_get_value(66);
+	val = gpio_get_value(IMX_GPIO_NR(3, 2));
 	val = val ? 0 : 1;
-	gpio_set_value(66, val);
+	gpio_set_value(IMX_GPIO_NR(3, 2), val);
 }
 #endif
 
 static void init_drive_strength(void)
 {
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
-	mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
-
-	/* Setting pad options */
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
-		PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
-		PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+	static const iomux_v3_cfg_t ddr_pads[] = {
+		NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
+		NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
+		NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
+		NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
+		NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
+		NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
+		NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
+		NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
+
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
+				MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
+		NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
 }
 
 int dram_init(void)
@@ -170,134 +151,102 @@ static void setup_weim(void)
 
 static void setup_uart(void)
 {
-	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-			 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
-	/* console RX on Pin EIM_D25 */
-	mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
-	/* console TX on Pin EIM_D26 */
-	mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
+		MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 #ifdef CONFIG_MXC_SPI
 void spi_io_init(void)
 {
-	/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
-	mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
-	/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
-	/* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
-	/*
-	 * SS1 will be used as GPIO because of uninterrupted
-	 * long SPI transmissions (GPIO4_25)
-	 */
-	mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
-	/* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
-	mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
-	/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
-	mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+	static const iomux_v3_cfg_t spi_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
+			PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
+			PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
+			PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
+				PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
 }
 
 static void reset_peripherals(int reset)
 {
+#ifdef CONFIG_VISION2_HW_1_0
+	static const iomux_v3_cfg_t fec_cfg_pads[] = {
+		/* RXD1 */
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
+		/* RXD2 */
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
+		/* RXD3 */
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
+		/* RXER */
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
+		/* COL */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
+		/* RCLK */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
+		/* RXD0 */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+		MX51_PAD_NANDF_D9__FEC_RDATA0,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+		MX51_PAD_EIM_CS4__FEC_RX_ER,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+	};
+#endif
+
 	if (reset) {
 
 		/* reset_n is on NANDF_D15 */
-		gpio_direction_output(89, 0);
+		gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
 
 #ifdef CONFIG_VISION2_HW_1_0
 		/*
 		 * set FEC Configuration lines
 		 * set levels of FEC config lines
 		 */
-		gpio_direction_output(75, 0);
-		gpio_direction_output(74, 1);
-		gpio_direction_output(95, 1);
+		gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
+		gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
+		gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
 
 		/* set direction of FEC config lines */
-		gpio_direction_output(59, 0);
-		gpio_direction_output(60, 0);
-		gpio_direction_output(61, 0);
-		gpio_direction_output(55, 1);
-
-		/* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
-		mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
-		/* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
-		mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
-		/* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
-		mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
-		/* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
-		mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
-		/* FEC_COL  - sel GPIO (3-10) for configuration -> 1 */
-		mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
-		/* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
-		mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
-		/* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
-		mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
+		gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
+		gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
+		gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
+		gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
+
+		imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
+						 ARRAY_SIZE(fec_cfg_pads));
 #endif
 
-		/*
-		 * activate reset_n pin
-		 * Select mux mode: ALT3 mux port: NAND D15
-		 */
-		mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
-			PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
+		/* activate reset_n pin */
+		imx_iomux_v3_setup_pad(
+				NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
+						PAD_CTL_DSE_MAX));
 	} else {
 		/* set FEC Control lines */
-		gpio_direction_input(89);
+		gpio_direction_input(IMX_GPIO_NR(3, 25));
 		udelay(500);
 
 #ifdef CONFIG_VISION2_HW_1_0
-		/* FEC RDATA[3] */
-		mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
-
-		/* FEC RDATA[2] */
-		mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
-
-		/* FEC RDATA[1] */
-		mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
-
-		/* FEC RDATA[0] */
-		mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
-		mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
-
-		/* FEC RX_CLK */
-		mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
-		mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
-
-		/* FEC RX_ER */
-		mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
-		mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
-
-		/* FEC COL */
-		mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
-		mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
+		imx_iomux_v3_setup_multiple_pads(fec_pads,
+							ARRAY_SIZE(fec_pads));
 #endif
 	}
 }
@@ -376,155 +325,94 @@ static void power_init_mx51(void)
 
 static void setup_gpios(void)
 {
-	unsigned int i;
-
-	/* CAM_SUP_DISn, GPIO1_7 */
-	mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
+	static const iomux_v3_cfg_t gpio_pads_1[] = {
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
+		NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* DAB Display EN */
+		NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
+	};
+
+	static const iomux_v3_cfg_t gpio_pads_2[] = {
+		NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* Display2 TxEN */
+		NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* DAB Light EN */
+		NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* AUDIO_MUTE */
+		NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* SPARE_OUT */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* BEEPER_EN */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* POWER_OFF */
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* FRAM_WE */
+		NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
+				PAD_CTL_DSE_MED), /* EXPANSION_EN */
+		MX51_PAD_GPIO1_2__PWM1_PWMO,
+	};
 
-	/* DAB Display EN, GPIO3_1 */
-	mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
+	unsigned int i;
 
-	/* WDOG_TRIGGER, GPIO3_2 */
-	mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
+	imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
 
 	/* Now we need to trigger the watchdog */
 	WATCHDOG_RESET();
 
-	/* Display2 TxEN, GPIO3_3 */
-	mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
-
-	/* DAB Light EN, GPIO3_4 */
-	mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
-
-	/* AUDIO_MUTE, GPIO3_5 */
-	mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
-
-	/* SPARE_OUT, GPIO3_6 */
-	mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
-	mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
-
-	/* BEEPER_EN, GPIO3_26 */
-	mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
-
-	/* POWER_OFF, GPIO3_27 */
-	mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
-
-	/* FRAM_WE, GPIO3_30 */
-	mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
-
-	/* EXPANSION_EN, GPIO4_26 */
-	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
-
-	/* PWM Output GPIO1_2 */
-	mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
 
 	/*
 	 * Set GPIO1_4 to high and output; it is used to reset
 	 * the system on reboot
 	 */
-	gpio_direction_output(4, 1);
+	gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
 
-	gpio_direction_output(7, 0);
-	for (i = 65; i < 71; i++)
+	gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
+	for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
 		gpio_direction_output(i, 0);
 
-	gpio_direction_output(94, 0);
+	gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
 
 	/* Set POWER_OFF high */
-	gpio_direction_output(91, 1);
+	gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
 
-	gpio_direction_output(90, 0);
+	gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
 
-	gpio_direction_output(122, 0);
+	gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
 
-	gpio_direction_output(121, 1);
+	gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
 
 	WATCHDOG_RESET();
 }
 
 static void setup_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
-
-	/*FEC_MDC*/
-	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
-
-	/* FEC RDATA[3] */
-	mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
-
-	/* FEC RDATA[2] */
-	mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
-
-	/* FEC RDATA[1] */
-	mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
-
-	/* FEC RDATA[0] */
-	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
-
-	/* FEC TDATA[3] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
-
-	/* FEC TDATA[2] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
-
-	/* FEC TDATA[1] */
-	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
-
-	/* FEC TDATA[0] */
-	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
-
-	/* FEC TX_ER */
-	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
-
-	/* FEC TX_COL */
-	mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
-
-	/* FEC RX_CLK */
-	mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
-
-	/* FEC RX_CRS */
-	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
-
-	/* FEC RX_DV */
-	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
+				PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+		MX51_PAD_NANDF_CS3__FEC_MDC,
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+		NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+		MX51_PAD_NANDF_D9__FEC_RDATA0,
+		MX51_PAD_NANDF_CS6__FEC_TDATA3,
+		MX51_PAD_NANDF_CS5__FEC_TDATA2,
+		MX51_PAD_NANDF_CS4__FEC_TDATA1,
+		MX51_PAD_NANDF_D8__FEC_TDATA0,
+		MX51_PAD_NANDF_CS7__FEC_TX_EN,
+		MX51_PAD_NANDF_CS2__FEC_TX_ER,
+		MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+		NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+		MX51_PAD_EIM_CS5__FEC_CRS,
+		MX51_PAD_EIM_CS4__FEC_RX_ER,
+		NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
@@ -536,7 +424,7 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc)
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 
 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
-		*cd = gpio_get_value(0);
+		*cd = gpio_get_value(IMX_GPIO_NR(1, 0));
 	else
 		*cd = 0;
 
@@ -546,56 +434,24 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc)
 #ifdef CONFIG_FSL_ESDHC
 int board_mmc_init(bd_t *bis)
 {
-	mxc_request_iomux(MX51_PIN_SD1_CMD,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_request_iomux(MX51_PIN_SD1_CLK,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_request_iomux(MX51_PIN_SD1_DATA0,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_request_iomux(MX51_PIN_SD1_DATA1,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_request_iomux(MX51_PIN_SD1_DATA2,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_request_iomux(MX51_PIN_SD1_DATA3,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
-		PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
-		PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
-	mxc_request_iomux(MX51_PIN_GPIO1_0,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
-		PAD_CTL_HYS_ENABLE);
-	mxc_request_iomux(MX51_PIN_GPIO1_1,
-		IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
-		PAD_CTL_HYS_ENABLE);
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
+			PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
+			PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
+		NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 
 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
@@ -604,13 +460,18 @@ int board_mmc_init(bd_t *bis)
 
 void lcd_enable(void)
 {
+	static const iomux_v3_cfg_t lcd_pads[] = {
+		MX51_PAD_DI1_PIN2__DI1_PIN2,
+		MX51_PAD_DI1_PIN3__DI1_PIN3,
+	};
+
 	int ret;
 
-	mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 
-	gpio_set_value(2, 1);
-	mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
+	gpio_set_value(IMX_GPIO_NR(1, 2), 1);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
+						NO_PAD_CTRL));
 
 	ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
 	if (ret)
@@ -624,9 +485,9 @@ int board_early_init_f(void)
 	init_drive_strength();
 
 	/* Setup debug led */
-	gpio_direction_output(6, 0);
-	mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
+					PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
 
 	/* wait a little while to give the pll time to settle */
 	sdelay(100000);
@@ -644,12 +505,12 @@ int board_early_init_f(void)
 static void backlight(int on)
 {
 	if (on) {
-		gpio_set_value(65, 1);
+		gpio_set_value(IMX_GPIO_NR(3, 1), 1);
 		udelay(10000);
-		gpio_set_value(68, 1);
+		gpio_set_value(IMX_GPIO_NR(3, 4), 1);
 	} else {
-		gpio_set_value(65, 0);
-		gpio_set_value(68, 0);
+		gpio_set_value(IMX_GPIO_NR(3, 1), 0);
+		gpio_set_value(IMX_GPIO_NR(3, 4), 0);
 	}
 }
 
-- 
1.7.10.4

[U-Boot] [PATCH 06/12] imx: iomux-v3: Add iomux-mx53.h

[Benoît Thébaudeau]

Allow usage of the imx-common/iomux-v3.h framework by including pad settings for
the i.MX53. The content of the file is taken from Freescale's Linux kernel at
commit 4ab3715, plus the required changes to make it work in U-Boot.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 arch/arm/include/asm/arch-mx5/iomux-mx53.h | 1232 ++++++++++++++++++++++++++++
 1 file changed, 1232 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-mx5/iomux-mx53.h

diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx53.h b/arch/arm/include/asm/arch-mx5/iomux-mx53.h
new file mode 100644
index 0000000..f55c0f5
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx53.h
@@ -0,0 +1,1232 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on Freescale's Linux i.MX iomux-mx53.h file:
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_MX53_H__
+#define __IOMUX_MX53_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX53_UART_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX53_SDHC_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+
+/*
+ * The naming convention for the pad modes is MX53_PAD_<padname>__<padmode>
+ * If <padname> refers to a GPIO, it is named GPIO_<unit>
+ * If <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*								    PAD    MUX   ALT INPSE PATH PADCTRL */
+enum {
+	MX53_PAD_GPIO_19__KPP_COL_5			= IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__GPIO4_5			= IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__CCM_CLKO			= IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__SPDIF_OUT1			= IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2		= IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__ECSPI1_RDY			= IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__FEC_TDATA_3			= IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__SRC_INT_BOOT			= IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__KPP_COL_0			= IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__GPIO4_6			= IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC		= IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__UART4_TXD_MUX		= IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL0__ECSPI1_SCLK			= IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__FEC_RDATA_3			= IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__SRC_ANY_PU_RST		= IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__KPP_ROW_0			= IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__GPIO4_7			= IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD		= IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__UART4_RXD_MUX		= IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__ECSPI1_MOSI			= IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__FEC_TX_ER			= IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__KPP_COL_1			= IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__GPIO4_8			= IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS		= IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__UART5_TXD_MUX		= IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL1__ECSPI1_MISO			= IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__FEC_RX_CLK			= IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__USBPHY1_TXREADY		= IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__KPP_ROW_1			= IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__GPIO4_9			= IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD		= IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__UART5_RXD_MUX		= IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__ECSPI1_SS0			= IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__FEC_COL			= IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__USBPHY1_RXVALID		= IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__KPP_COL_2			= IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__GPIO4_10			= IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__CAN1_TXCAN			= IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__FEC_MDIO			= IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__ECSPI1_SS1			= IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__FEC_RDATA_2			= IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE		= IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__KPP_ROW_2			= IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__GPIO4_11			= IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__CAN1_RXCAN			= IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__FEC_MDC			= IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__ECSPI1_SS2			= IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__FEC_TDATA_2			= IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__USBPHY1_RXERROR		= IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__KPP_COL_3			= IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__GPIO4_12			= IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__USBOH3_H2_DP			= IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__SPDIF_IN1			= IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__I2C2_SCL			= IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__ECSPI1_SS3			= IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__FEC_CRS			= IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK		= IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__KPP_ROW_3			= IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__GPIO4_13			= IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__USBOH3_H2_DM			= IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK		= IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__I2C2_SDA			= IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__OSC32K_32K_OUT		= IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__CCM_PLL4_BYP			= IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0		= IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__KPP_COL_4			= IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__GPIO4_14			= IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__CAN2_TXCAN			= IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__IPU_SISG_4			= IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__UART5_RTS			= IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC		= IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1		= IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__KPP_ROW_4			= IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__GPIO4_15			= IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__CAN2_RXCAN			= IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__IPU_SISG_5			= IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__UART5_CTS			= IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR		= IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID		= IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK		= IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__GPIO4_16			= IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR		= IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0	= IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0		= IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID		= IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__IPU_DI0_PIN15		= IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__GPIO4_17			= IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC		= IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1	= IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1		= IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__USBPHY1_BVALID		= IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__IPU_DI0_PIN2			= IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__GPIO4_18			= IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD		= IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2	= IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2		= IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION		= IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__IPU_DI0_PIN3			= IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__GPIO4_19			= IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS		= IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3	= IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3		= IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__USBPHY1_IDDIG		= IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__IPU_DI0_PIN4			= IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__GPIO4_20			= IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD		= IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__ESDHC1_WP			= IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD		= IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4		= IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT	= IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0		= IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__GPIO4_21			= IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__CSPI_SCLK			= IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0	= IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN	= IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5		= IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY		= IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1		= IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__GPIO4_22			= IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__CSPI_MOSI			= IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1	= IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL
+							= IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6		= IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID		= IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2		= IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__GPIO4_23			= IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__CSPI_MISO			= IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2	= IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE		= IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7		= IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE		= IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3		= IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__GPIO4_24			= IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__CSPI_SS0			= IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3	= IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR	= IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8		= IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR		= IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4		= IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__GPIO4_25			= IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__CSPI_SS1			= IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4	= IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB		= IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9		= IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK		= IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5		= IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__GPIO4_26			= IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__CSPI_SS2			= IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5	= IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS	= IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10		= IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0	= IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6		= IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__GPIO4_27			= IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__CSPI_SS3			= IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6	= IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE	= IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11		= IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1	= IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7		= IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__GPIO4_28			= IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__CSPI_RDY			= IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7	= IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0	= IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12		= IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID		= IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8		= IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__GPIO4_29			= IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__PWM1_PWMO			= IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B		= IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1	= IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13		= IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__USBPHY2_AVALID		= IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9		= IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__GPIO4_30			= IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__PWM2_PWMO			= IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B		= IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2	= IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14		= IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0		= IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10		= IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__GPIO4_31			= IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP		= IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3
+							= IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15		= IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1		= IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11		= IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__GPIO5_5			= IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT		= IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4
+							= IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16		= IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2		= IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12		= IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__GPIO5_6			= IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK		= IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5
+							= IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17		= IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3		= IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13		= IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__GPIO5_7			= IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS		= IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0
+							= IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18		= IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4		= IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14		= IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__GPIO5_8			= IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC		= IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1
+							= IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19		= IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5		= IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15		= IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__GPIO5_9			= IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__ECSPI1_SS1		= IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__ECSPI2_SS1		= IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2
+							= IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20		= IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6		= IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16		= IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__GPIO5_10			= IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__ECSPI2_MOSI		= IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC		= IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0		= IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3
+							= IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21		= IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7		= IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17		= IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__GPIO5_11			= IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__ECSPI2_MISO		= IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD		= IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1		= IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4
+							= IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22		= IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18		= IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__GPIO5_12			= IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__ECSPI2_SS0		= IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS		= IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS		= IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5
+							= IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23		= IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2		= IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19		= IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__GPIO5_13			= IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__ECSPI2_SCLK		= IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD		= IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC		= IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6
+							= IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24		= IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3		= IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20		= IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__GPIO5_14			= IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__ECSPI1_SCLK		= IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC		= IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7
+							= IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25		= IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__SATA_PHY_TDI		= IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21		= IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__GPIO5_15			= IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__ECSPI1_MOSI		= IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD		= IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0	= IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26		= IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__SATA_PHY_TDO		= IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22		= IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__GPIO5_16			= IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__ECSPI1_MISO		= IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS		= IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1	= IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27		= IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__SATA_PHY_TCK		= IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23		= IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__GPIO5_17			= IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__ECSPI1_SS0		= IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD		= IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2	= IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28		= IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__SATA_PHY_TMS		= IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK		= IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__GPIO5_18			= IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0		= IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29		= IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC		= IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__GPIO5_19			= IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK		= IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1		= IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30		= IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__TPIU_TRCTL			= IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN		= IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__GPIO5_20			= IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2		= IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31		= IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK		= IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC		= IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__GPIO5_21			= IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3		= IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32		= IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0		= IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4		= IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__GPIO5_22			= IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__KPP_COL_5			= IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__ECSPI1_SCLK			= IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP		= IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC		= IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33		= IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__TPIU_TRACE_1		= IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5		= IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__GPIO5_23			= IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__KPP_ROW_5			= IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__ECSPI1_MOSI			= IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT		= IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD		= IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34		= IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__TPIU_TRACE_2		= IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6		= IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__GPIO5_24			= IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__KPP_COL_6			= IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__ECSPI1_MISO			= IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK		= IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS		= IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35		= IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__TPIU_TRACE_3		= IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7		= IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__GPIO5_25			= IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__KPP_ROW_6			= IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__ECSPI1_SS0			= IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR		= IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD		= IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36		= IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__TPIU_TRACE_4		= IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8		= IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__GPIO5_26			= IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__KPP_COL_7			= IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__ECSPI2_SCLK			= IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC		= IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__I2C1_SDA			= IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37		= IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__TPIU_TRACE_5		= IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9		= IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__GPIO5_27			= IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__KPP_ROW_7			= IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__ECSPI2_MOSI			= IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR		= IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__I2C1_SCL			= IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38		= IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__TPIU_TRACE_6		= IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10		= IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__GPIO5_28			= IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX		= IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__ECSPI2_MISO		= IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC		= IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4		= IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39		= IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__TPIU_TRACE_7		= IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11		= IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__GPIO5_29			= IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX		= IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__ECSPI2_SS0			= IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS		= IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5		= IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40		= IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__TPIU_TRACE_8		= IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12		= IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__GPIO5_30			= IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__UART4_TXD_MUX		= IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0	= IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6		= IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41		= IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__TPIU_TRACE_9		= IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13		= IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__GPIO5_31			= IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__UART4_RXD_MUX		= IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1	= IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7		= IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42		= IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__TPIU_TRACE_10		= IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14		= IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__GPIO6_0			= IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__UART5_TXD_MUX		= IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2	= IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8		= IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43		= IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__TPIU_TRACE_11		= IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15		= IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__GPIO6_1			= IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__UART5_RXD_MUX		= IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3	= IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9		= IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44		= IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__TPIU_TRACE_12		= IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16		= IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__GPIO6_2			= IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__UART4_RTS			= IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4	= IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10		= IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45		= IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__TPIU_TRACE_13		= IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17		= IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__GPIO6_3			= IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__UART4_CTS			= IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5	= IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11		= IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46		= IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__TPIU_TRACE_14		= IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18		= IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__GPIO6_4			= IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__UART5_RTS			= IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6	= IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12		= IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47		= IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__TPIU_TRACE_15		= IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19		= IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__GPIO6_5			= IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__UART5_CTS			= IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7	= IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13		= IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48		= IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK		= IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__EMI_WEIM_A_25			= IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__GPIO5_2			= IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__ECSPI2_RDY			= IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__IPU_DI1_PIN12			= IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__CSPI_SS1			= IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__IPU_DI0_D1_CS			= IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__USBPHY1_BISTOK		= IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__EMI_WEIM_EB_2			= IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__GPIO2_30			= IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK		= IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS		= IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__ECSPI1_SS0			= IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__I2C2_SCL			= IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__EMI_WEIM_D_16			= IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__GPIO3_16			= IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__IPU_DI0_PIN5			= IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK		= IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__ECSPI1_SCLK			= IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__I2C2_SDA			= IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__EMI_WEIM_D_17			= IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__GPIO3_17			= IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__IPU_DI0_PIN6			= IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN		= IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__ECSPI1_MISO			= IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__I2C3_SCL			= IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__EMI_WEIM_D_18			= IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__GPIO3_18			= IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DI0_PIN7			= IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO		= IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__ECSPI1_MOSI			= IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__I2C3_SDA			= IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DI1_D0_CS			= IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__EMI_WEIM_D_19			= IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__GPIO3_19			= IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__IPU_DI0_PIN8			= IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS		= IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__ECSPI1_SS1			= IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__EPIT1_EPITO			= IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__UART1_CTS			= IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D19__USBOH3_USBH2_OC		= IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__EMI_WEIM_D_20			= IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__GPIO3_20			= IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__IPU_DI0_PIN16			= IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__IPU_SER_DISP0_CS		= IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__CSPI_SS0			= IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__EPIT2_EPITO			= IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__UART1_RTS			= IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D20__USBOH3_USBH2_PWR		= IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__EMI_WEIM_D_21			= IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__GPIO3_21			= IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__IPU_DI0_PIN17			= IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK		= IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__CSPI_SCLK			= IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__I2C1_SCL			= IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__USBOH3_USBOTG_OC		= IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__EMI_WEIM_D_22			= IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__GPIO3_22			= IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__IPU_DI0_PIN1			= IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN		= IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__CSPI_MISO			= IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR		= IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__EMI_WEIM_D_23			= IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__GPIO3_23			= IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__UART3_CTS			= IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D23__UART1_DCD			= IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI0_D0_CS			= IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI1_PIN2			= IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN		= IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI1_PIN14			= IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__EMI_WEIM_EB_3			= IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__GPIO2_31			= IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__UART3_RTS			= IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_EB3__UART1_RI			= IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_DI1_PIN3			= IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC		= IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_DI1_PIN16			= IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__EMI_WEIM_D_24			= IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__GPIO3_24			= IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__UART3_TXD_MUX			= IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D24__ECSPI1_SS2			= IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__CSPI_SS2			= IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS		= IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__ECSPI2_SS2			= IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__UART1_DTR			= IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__EMI_WEIM_D_25			= IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__GPIO3_25			= IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__UART3_RXD_MUX			= IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D25__ECSPI1_SS3			= IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__CSPI_SS3			= IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC		= IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__ECSPI2_SS3			= IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__UART1_DSR			= IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__EMI_WEIM_D_26			= IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__GPIO3_26			= IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__UART2_TXD_MUX			= IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D26__FIRI_RXD			= IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_CSI0_D_1			= IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_DI1_PIN11			= IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_SISG_2			= IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_DISP1_DAT_22		= IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__EMI_WEIM_D_27			= IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__GPIO3_27			= IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__UART2_RXD_MUX			= IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D27__FIRI_TXD			= IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_CSI0_D_0			= IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_DI1_PIN13			= IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_SISG_3			= IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_DISP1_DAT_23		= IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__EMI_WEIM_D_28			= IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__GPIO3_28			= IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__UART2_CTS			= IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO		= IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__CSPI_MOSI			= IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__I2C1_SDA			= IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_EXT_TRIG			= IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_DI0_PIN13			= IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__EMI_WEIM_D_29			= IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__GPIO3_29			= IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__UART2_RTS			= IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS		= IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__CSPI_SS0			= IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DI1_PIN15			= IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_CSI1_VSYNC		= IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DI0_PIN14			= IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__EMI_WEIM_D_30			= IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__GPIO3_30			= IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__UART3_CTS			= IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_CSI0_D_3			= IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_DI0_PIN11			= IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_DISP1_DAT_21		= IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__USBOH3_USBH1_OC		= IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__USBOH3_USBH2_OC		= IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__EMI_WEIM_D_31			= IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__GPIO3_31			= IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__UART3_RTS			= IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_CSI0_D_2			= IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_DI0_PIN12			= IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_DISP1_DAT_20		= IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__USBOH3_USBH1_PWR		= IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__USBOH3_USBH2_PWR		= IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__EMI_WEIM_A_24			= IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__GPIO5_4			= IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_DISP1_DAT_19		= IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_CSI1_D_19			= IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_SISG_2			= IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__USBPHY2_BVALID		= IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__EMI_WEIM_A_23			= IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__GPIO6_6			= IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_DISP1_DAT_18		= IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_CSI1_D_18			= IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_SISG_3			= IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__USBPHY2_ENDSESSION		= IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__EMI_WEIM_A_22			= IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__GPIO2_16			= IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__IPU_DISP1_DAT_17		= IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__IPU_CSI1_D_17			= IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__SRC_BT_CFG1_7			= IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__EMI_WEIM_A_21			= IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__GPIO2_17			= IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__IPU_DISP1_DAT_16		= IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__IPU_CSI1_D_16			= IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__SRC_BT_CFG1_6			= IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__EMI_WEIM_A_20			= IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__GPIO2_18			= IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__IPU_DISP1_DAT_15		= IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__IPU_CSI1_D_15			= IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__SRC_BT_CFG1_5			= IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__EMI_WEIM_A_19			= IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__GPIO2_19			= IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__IPU_DISP1_DAT_14		= IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__IPU_CSI1_D_14			= IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__SRC_BT_CFG1_4			= IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__EMI_WEIM_A_18			= IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__GPIO2_20			= IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__IPU_DISP1_DAT_13		= IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__IPU_CSI1_D_13			= IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__SRC_BT_CFG1_3			= IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__EMI_WEIM_A_17			= IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__GPIO2_21			= IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__IPU_DISP1_DAT_12		= IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__IPU_CSI1_D_12			= IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__SRC_BT_CFG1_2			= IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__EMI_WEIM_A_16			= IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__GPIO2_22			= IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK		= IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK		= IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__SRC_BT_CFG1_1			= IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__EMI_WEIM_CS_0			= IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__GPIO2_23			= IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__ECSPI2_SCLK			= IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__IPU_DI1_PIN5			= IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__EMI_WEIM_CS_1			= IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__GPIO2_24			= IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__ECSPI2_MOSI			= IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__IPU_DI1_PIN6			= IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__EMI_WEIM_OE			= IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__GPIO2_25			= IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__ECSPI2_MISO			= IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__IPU_DI1_PIN7			= IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__USBPHY2_IDDIG			= IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__EMI_WEIM_RW			= IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__GPIO2_26			= IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__ECSPI2_SS0			= IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__IPU_DI1_PIN8			= IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT		= IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__EMI_WEIM_LBA			= IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__GPIO2_27			= IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__ECSPI2_SS1			= IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__IPU_DI1_PIN17			= IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__SRC_BT_CFG1_0			= IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__EMI_WEIM_EB_0			= IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__GPIO2_28			= IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11		= IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__IPU_CSI1_D_11			= IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__GPC_PMIC_RDY			= IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__SRC_BT_CFG2_7			= IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__EMI_WEIM_EB_1			= IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__GPIO2_29			= IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10		= IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__IPU_CSI1_D_10			= IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__SRC_BT_CFG2_6			= IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0		= IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__GPIO3_0			= IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9		= IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__IPU_CSI1_D_9			= IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__SRC_BT_CFG2_5			= IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1		= IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__GPIO3_1			= IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8		= IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__IPU_CSI1_D_8			= IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__SRC_BT_CFG2_4			= IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2		= IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__GPIO3_2			= IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7		= IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__IPU_CSI1_D_7			= IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__SRC_BT_CFG2_3			= IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3		= IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__GPIO3_3			= IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6		= IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__IPU_CSI1_D_6			= IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__SRC_BT_CFG2_2			= IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4		= IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__GPIO3_4			= IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5		= IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__IPU_CSI1_D_5			= IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__SRC_BT_CFG3_7			= IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5		= IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__GPIO3_5			= IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4		= IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__IPU_CSI1_D_4			= IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__SRC_BT_CFG3_6			= IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6		= IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__GPIO3_6			= IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3		= IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__IPU_CSI1_D_3			= IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__SRC_BT_CFG3_5			= IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7		= IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__GPIO3_7			= IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2		= IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__IPU_CSI1_D_2			= IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__SRC_BT_CFG3_4			= IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8		= IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__GPIO3_8			= IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1		= IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__IPU_CSI1_D_1			= IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__SRC_BT_CFG3_3			= IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9		= IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__GPIO3_9			= IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0		= IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__IPU_CSI1_D_0			= IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__SRC_BT_CFG3_2			= IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10		= IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__GPIO3_10			= IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__IPU_DI1_PIN15		= IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN		= IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__SRC_BT_CFG3_1		= IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11		= IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__GPIO3_11			= IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__IPU_DI1_PIN2			= IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC		= IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12		= IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__GPIO3_12			= IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__IPU_DI1_PIN3			= IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC		= IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13		= IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__GPIO3_13			= IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__IPU_DI1_D0_CS		= IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK		= IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14		= IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__GPIO3_14			= IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__IPU_DI1_D1_CS		= IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK		= IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15		= IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__GPIO3_15			= IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__IPU_DI1_PIN1			= IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__IPU_DI1_PIN4			= IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B		= IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WE_B__GPIO6_12			= IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B		= IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RE_B__GPIO6_13			= IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT		= IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__GPIO5_0			= IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B		= IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX3_P__GPIO6_22			= IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3		= IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX2_P__GPIO6_24			= IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2		= IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_CLK_P__GPIO6_26			= IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK		= IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX1_P__GPIO6_28			= IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1		= IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX0_P__GPIO6_30			= IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0		= IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX3_P__GPIO7_22			= IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3		= IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_CLK_P__GPIO7_24			= IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK		= IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX2_P__GPIO7_26			= IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2		= IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX1_P__GPIO7_28			= IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1		= IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX0_P__GPIO7_30			= IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0		= IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_10__GPIO4_0			= IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_10__OSC32k_32K_OUT		= IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_11__GPIO4_1			= IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_12__GPIO4_2			= IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_13__GPIO4_3			= IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_14__GPIO4_4			= IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__EMI_NANDF_CLE		= IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__GPIO6_7			= IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0		= IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__EMI_NANDF_ALE		= IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__GPIO6_8			= IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1		= IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B		= IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__GPIO6_9			= IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2		= IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0		= IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__GPIO6_10			= IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3		= IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0		= IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__GPIO6_11			= IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4		= IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1		= IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__GPIO6_14			= IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__MLB_MLBCLK			= IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5		= IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2		= IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__GPIO6_15			= IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__IPU_SISG_0			= IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__ESAI1_TX0			= IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__EMI_WEIM_CRE		= IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK		= IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__MLB_MLBSIG			= IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6		= IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3		= IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__GPIO6_16			= IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__IPU_SISG_1			= IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__ESAI1_TX1			= IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__EMI_WEIM_A_26		= IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__MLB_MLBDAT			= IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7		= IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__FEC_MDIO			= IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__GPIO1_22			= IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__ESAI1_SCKR			= IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__FEC_COL			= IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2		= IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3	= IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49		= IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__FEC_TX_CLK		= IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__GPIO1_23			= IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__ESAI1_FSR			= IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4	= IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50		= IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__FEC_RX_ER			= IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__GPIO1_24			= IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__ESAI1_HCKR			= IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__FEC_RX_CLK			= IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3		= IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__FEC_RX_DV			= IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__GPIO1_25			= IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__ESAI1_SCKT			= IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__FEC_RDATA_1			= IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__GPIO1_26			= IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__ESAI1_FST			= IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__MLB_MLBSIG			= IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1		= IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__FEC_RDATA_0			= IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__GPIO1_27			= IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__ESAI1_HCKT			= IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__OSC32k_32K_OUT		= IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__FEC_TX_EN			= IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__GPIO1_28			= IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2		= IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__FEC_TDATA_1			= IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__GPIO1_29			= IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3		= IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__MLB_MLBCLK			= IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK		= IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__FEC_TDATA_0			= IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__GPIO1_30			= IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1		= IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0		= IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__FEC_MDC			= IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__GPIO1_31			= IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__ESAI1_TX5_RX0			= IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__MLB_MLBDAT			= IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG	= IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1		= IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__PATA_DIOW			= IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__GPIO6_17			= IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__UART1_TXD_MUX		= IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2		= IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__PATA_DMACK			= IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__GPIO6_18			= IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__UART1_RXD_MUX		= IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3		= IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__PATA_DMARQ			= IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__GPIO7_0			= IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__UART2_TXD_MUX		= IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0		= IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4		= IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN		= IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__GPIO7_1		= IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX		= IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1		= IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5	= IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__PATA_INTRQ			= IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__GPIO7_2			= IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__UART2_CTS			= IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__CAN1_TXCAN			= IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2		= IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6		= IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__PATA_DIOR			= IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__GPIO7_3			= IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__UART2_RTS			= IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__CAN1_RXCAN			= IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7		= IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B	= IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__GPIO7_4			= IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__ESDHC3_CMD		= IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__UART1_CTS		= IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__CAN2_TXCAN		= IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0	= IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__PATA_IORDY			= IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__GPIO7_5			= IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__ESDHC3_CLK			= IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__UART1_RTS			= IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__CAN2_RXCAN			= IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1		= IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__PATA_DA_0			= IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__GPIO7_6			= IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__ESDHC3_RST			= IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__OWIRE_LINE			= IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2		= IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__PATA_DA_1			= IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__GPIO7_7			= IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__ESDHC4_CMD			= IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__UART3_CTS			= IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3		= IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__PATA_DA_2			= IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__GPIO7_8			= IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__ESDHC4_CLK			= IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__UART3_RTS			= IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4		= IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__PATA_CS_0			= IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__GPIO7_9			= IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__UART3_TXD_MUX		= IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5		= IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__PATA_CS_1			= IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__GPIO7_10			= IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__UART3_RXD_MUX		= IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6		= IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__PATA_DATA_0		= IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__GPIO2_0			= IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__EMI_NANDF_D_0		= IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__ESDHC3_DAT4		= IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0	= IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0		= IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7		= IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__PATA_DATA_1		= IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__GPIO2_1			= IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__EMI_NANDF_D_1		= IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__ESDHC3_DAT5		= IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1	= IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1		= IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__PATA_DATA_2		= IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__GPIO2_2			= IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__EMI_NANDF_D_2		= IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__ESDHC3_DAT6		= IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2	= IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2		= IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__PATA_DATA_3		= IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__GPIO2_3			= IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__EMI_NANDF_D_3		= IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__ESDHC3_DAT7		= IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3	= IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3		= IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__PATA_DATA_4		= IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__GPIO2_4			= IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__EMI_NANDF_D_4		= IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__ESDHC4_DAT4		= IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4	= IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4		= IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__PATA_DATA_5		= IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__GPIO2_5			= IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__EMI_NANDF_D_5		= IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__ESDHC4_DAT5		= IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5	= IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5		= IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__PATA_DATA_6		= IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__GPIO2_6			= IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__EMI_NANDF_D_6		= IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__ESDHC4_DAT6		= IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6	= IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6		= IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__PATA_DATA_7		= IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__GPIO2_7			= IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__EMI_NANDF_D_7		= IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__ESDHC4_DAT7		= IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7	= IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7		= IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__PATA_DATA_8		= IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__GPIO2_8			= IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__ESDHC1_DAT4		= IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__EMI_NANDF_D_8		= IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__ESDHC3_DAT0		= IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8	= IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8		= IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__PATA_DATA_9		= IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__GPIO2_9			= IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__ESDHC1_DAT5		= IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__EMI_NANDF_D_9		= IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__ESDHC3_DAT1		= IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9	= IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9		= IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__PATA_DATA_10		= IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__GPIO2_10			= IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__ESDHC1_DAT6		= IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__EMI_NANDF_D_10		= IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__ESDHC3_DAT2		= IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10	= IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10		= IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__PATA_DATA_11		= IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__GPIO2_11			= IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__ESDHC1_DAT7		= IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__EMI_NANDF_D_11		= IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__ESDHC3_DAT3		= IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11	= IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11		= IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__PATA_DATA_12		= IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__GPIO2_12			= IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__ESDHC2_DAT4		= IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__EMI_NANDF_D_12		= IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__ESDHC4_DAT0		= IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12	= IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12		= IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__PATA_DATA_13		= IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__GPIO2_13			= IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__ESDHC2_DAT5		= IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__EMI_NANDF_D_13		= IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__ESDHC4_DAT1		= IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13	= IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13		= IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__PATA_DATA_14		= IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__GPIO2_14			= IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__ESDHC2_DAT6		= IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__EMI_NANDF_D_14		= IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__ESDHC4_DAT2		= IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14	= IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14		= IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__PATA_DATA_15		= IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__GPIO2_15			= IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__ESDHC2_DAT7		= IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__EMI_NANDF_D_15		= IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__ESDHC4_DAT3		= IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15	= IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15		= IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__ESDHC1_DAT0			= IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__GPIO1_16			= IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__GPT_CAPIN1			= IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__CSPI_MISO			= IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__CCM_PLL3_BYP		= IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__ESDHC1_DAT1			= IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__GPIO1_17			= IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__GPT_CAPIN2			= IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__CSPI_SS0			= IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__CCM_PLL4_BYP		= IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__ESDHC1_CMD			= IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_CMD__GPIO1_18			= IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__GPT_CMPOUT1			= IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__CSPI_MOSI			= IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__CCM_PLL1_BYP			= IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__ESDHC1_DAT2			= IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__GPIO1_19			= IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__GPT_CMPOUT2			= IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__PWM2_PWMO			= IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__WDOG1_WDOG_B		= IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__CSPI_SS1			= IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB	= IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__CCM_PLL2_BYP		= IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__ESDHC1_CLK			= IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_CLK__GPIO1_20			= IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__OSC32k_32K_OUT		= IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__GPT_CLKIN			= IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__CSPI_SCLK			= IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__SATA_PHY_DTB_0		= IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__ESDHC1_DAT3			= IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__GPIO1_21			= IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__GPT_CMPOUT3			= IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__PWM1_PWMO			= IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__WDOG2_WDOG_B		= IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__CSPI_SS2			= IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB	= IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1		= IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__ESDHC2_CLK			= IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_CLK__GPIO1_10			= IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__KPP_COL_5			= IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS		= IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__CSPI_SCLK			= IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__SCC_RANDOM_V			= IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__ESDHC2_CMD			= IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_CMD__GPIO1_11			= IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__KPP_ROW_5			= IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC		= IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__CSPI_MOSI			= IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__SCC_RANDOM			= IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__ESDHC2_DAT3			= IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__GPIO1_12			= IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__KPP_COL_6			= IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC		= IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__CSPI_SS2			= IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__SJC_DONE			= IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__ESDHC2_DAT2			= IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__GPIO1_13			= IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__KPP_ROW_6			= IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD		= IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__CSPI_SS1			= IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__SJC_FAIL			= IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__ESDHC2_DAT1			= IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__GPIO1_14			= IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__KPP_COL_7			= IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS		= IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__CSPI_SS0			= IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__RTIC_SEC_VIO		= IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__ESDHC2_DAT0			= IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__GPIO1_15			= IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__KPP_ROW_7			= IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD		= IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__CSPI_MISO			= IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__RTIC_DONE_INT		= IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CCM_CLKO			= IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__GPIO1_0			= IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__KPP_COL_5			= IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK		= IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__EPIT1_EPITO			= IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__SRTC_ALARM_DEB			= IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__USBOH3_USBH1_PWR		= IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CSU_TD				= IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__ESAI1_SCKR			= IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__GPIO1_1			= IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__KPP_ROW_5			= IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK		= IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__PWM2_PWMO			= IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__WDOG2_WDOG_B			= IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__ESDHC1_CD			= IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__SRC_TESTER_ACK			= IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__ESAI1_FSR			= IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__GPIO1_9			= IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__KPP_COL_6			= IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__CCM_REF_EN_B			= IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__PWM1_PWMO			= IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__WDOG1_WDOG_B			= IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__ESDHC1_WP			= IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__SCC_FAIL_STATE			= IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__ESAI1_HCKR			= IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__GPIO1_3			= IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__I2C3_SCL			= IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__DPLLIP1_TOG_EN			= IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__CCM_CLKO2			= IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0	= IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__USBOH3_USBH1_OC		= IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__MLB_MLBCLK			= IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__ESAI1_SCKT			= IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__GPIO1_6			= IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__I2C3_SDA			= IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__CCM_CCM_OUT_0			= IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__CSU_CSU_INT_DEB		= IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1	= IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__ESDHC2_LCTL			= IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__MLB_MLBSIG			= IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__ESAI1_FST			= IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__GPIO1_2			= IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__KPP_ROW_6			= IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__CCM_CCM_OUT_1			= IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0		= IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2	= IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__ESDHC2_WP			= IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__MLB_MLBDAT			= IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__ESAI1_HCKT			= IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__GPIO1_4			= IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__KPP_COL_7			= IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__CCM_CCM_OUT_2			= IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1		= IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3	= IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__ESDHC2_CD			= IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__SCC_SEC_STATE			= IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__ESAI1_TX2_RX3			= IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__GPIO1_5			= IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__KPP_ROW_7			= IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CCM_CLKO			= IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2		= IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4	= IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__I2C3_SCL			= IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CCM_PLL1_BYP			= IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__ESAI1_TX4_RX1			= IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__GPIO1_7			= IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__EPIT1_EPITO			= IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__CAN1_TXCAN			= IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__UART2_TXD_MUX			= IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_GPIO_7__FIRI_RXD			= IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__SPDIF_PLOCK			= IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__CCM_PLL2_BYP			= IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__ESAI1_TX5_RX0			= IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__GPIO1_8			= IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__EPIT2_EPITO			= IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__CAN1_RXCAN			= IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__UART2_RXD_MUX			= IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL),
+	MX53_PAD_GPIO_8__FIRI_TXD			= IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__SPDIF_SRCLK			= IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__CCM_PLL3_BYP			= IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__ESAI1_TX3_RX2			= IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__GPIO7_11			= IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT		= IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1		= IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__SPDIF_IN1			= IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__I2C3_SDA			= IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__SJC_DE_B			= IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__ESAI1_TX0			= IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__GPIO7_12			= IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0		= IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__GPC_PMIC_RDY			= IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG		= IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SPDIF_OUT1			= IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__IPU_SNOOP2			= IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SJC_JTAG_ACT			= IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__ESAI1_TX1			= IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__GPIO7_13			= IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1		= IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__OWIRE_LINE			= IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG	= IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK		= IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__ESDHC1_LCTL			= IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__SRC_SYSTEM_RST		= IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX53_H__ */
-- 
1.7.10.4

[U-Boot] [PATCH 07/12] imx: ima3-mx53: Convert to iomux-v3

[Benoît Thébaudeau]

There is no change of behavior.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 board/esg/ima3-mx53/ima3-mx53.c |  227 +++++++++++++--------------------------
 include/configs/ima3-mx53.h     |    3 -
 2 files changed, 72 insertions(+), 158 deletions(-)

diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c
index 41d6bb6..d1817fa 100644
--- a/board/esg/ima3-mx53/ima3-mx53.c
+++ b/board/esg/ima3-mx53/ima3-mx53.c
@@ -23,11 +23,10 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <asm/errno.h>
 #include <netdev.h>
 #include <mmc.h>
@@ -66,109 +65,53 @@ int dram_init(void)
 	return 0;
 }
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_uart(void)
 {
-	/* UART4 RXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D13,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
-		PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
-
-	/* UART4 TXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D12,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
-		PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 static void setup_iomux_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU |
-		PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
-	/*FEC_MDC*/
-	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
-	/* FEC RXD3 */
-	mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD2 */
-	mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC TXD3 */
-	mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD2 */
-	mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC RX_DV */
-	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC CRS */
-	mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-
-	/* FEC COL */
-	mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0);
-
-	/* FEC RX_CLK */
-	mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6);
-	mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PKE_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -178,76 +121,50 @@ int board_mmc_getcd(struct mmc *mmc)
 {
 	int ret;
 
-	ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
+	ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
 
 	return ret;
 }
 
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
 int board_mmc_init(bd_t *bis)
 {
-	mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
-	mxc_iomux_set_pad(MX53_PIN_GPIO_1,
-		PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
-		PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
-		PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE);
-	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
-
-	mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-	mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
-		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
-		PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH);
-	mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CMD_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+	gpio_direction_input(IMX_GPIO_NR(1, 1));
 
 	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }
 #endif
 
+#define SPI_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
+
 static void setup_iomux_spi(void)
 {
-	/* SCLK */
-	mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1);
-	/* MOSI */
-	mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1);
-	/* MISO */
-	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1);
-	/* SSEL 0 */
-	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
-		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
-		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1);
+	static const iomux_v3_cfg_t spi_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
+		/* SSEL 0 */
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+	gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
 }
 
 int board_early_init_f(void)
diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
index c663700..327a866 100644
--- a/include/configs/ima3-mx53.h
+++ b/include/configs/ima3-mx53.h
@@ -26,7 +26,6 @@
 /* SOC type must be included before imx-regs.h */
 #define CONFIG_MX53
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -79,8 +78,6 @@
 /* SPI FLASH - not used for environment */
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_CS		(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11) \
-						 << 8) | 0
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		25000000
 
-- 
1.7.10.4

[U-Boot] [PATCH 08/12] imx: mx53ard: Convert to iomux-v3

[Benoît Thébaudeau]

There is no change of behavior.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 board/freescale/mx53ard/mx53ard.c |  327 ++++++++++++++++---------------------
 1 file changed, 141 insertions(+), 186 deletions(-)

diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index 32c4d5f..f953aa9 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -23,11 +23,10 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <asm/errno.h>
 #include <netdev.h>
 #include <mmc.h>
@@ -61,6 +60,41 @@ void dram_init_banksize(void)
 #ifdef CONFIG_NAND_MXC
 static void setup_iomux_nand(void)
 {
+	static const iomux_v3_cfg_t nand_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
+				PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
+				PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+				PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+				PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+				PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+				PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+				PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+				PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+				PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
+				PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH),
+	};
+
 	u32 i, reg;
 
 	reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
@@ -72,48 +106,7 @@ static void setup_iomux_nand(void)
 		__raw_writel(reg, WEIM_BASE_ADDR + i);
 	}
 
-	mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
-	mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
-	mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
-	mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE |
-					PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 }
 #else
 static void setup_iomux_nand(void)
@@ -121,24 +114,17 @@ static void setup_iomux_nand(void)
 }
 #endif
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_uart(void)
 {
-	/* UART1 RXD */
-	mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
-
-	/* UART1 TXD */
-	mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
-	mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -152,9 +138,9 @@ int board_mmc_getcd(struct mmc *mmc)
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret;
 
-	mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 	gpio_direction_input(IMX_GPIO_NR(1, 1));
-	mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
 	gpio_direction_input(IMX_GPIO_NR(1, 4));
 
 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
@@ -165,8 +151,36 @@ int board_mmc_getcd(struct mmc *mmc)
 	return ret;
 }
 
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_CLK_PAD_CTRL		(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t sd2_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
+	};
+
 	u32 index;
 	s32 status = 0;
 
@@ -176,56 +190,12 @@ int board_mmc_init(bd_t *bis)
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:
-			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA0,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA1,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA2,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA3,
-						IOMUX_CONFIG_ALT0);
-
-			mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
-			mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
 			break;
 		case 1:
-			mxc_request_iomux(MX53_PIN_SD2_CMD,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX53_PIN_SD2_CLK,
-				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
-			mxc_request_iomux(MX53_PIN_SD2_DATA0,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD2_DATA1,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD2_DATA2,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD2_DATA3,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_ATA_DATA12,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_DATA13,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_DATA14,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_DATA15,
-						IOMUX_CONFIG_ALT2);
-
-			mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
-			mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
-			mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
+			imx_iomux_v3_setup_multiple_pads(sd2_pads,
+							 ARRAY_SIZE(sd2_pads));
 			break;
 		default:
 			printf("Warning: you configured more ESDHC controller"
@@ -242,85 +212,70 @@ int board_mmc_init(bd_t *bis)
 
 static void weim_smc911x_iomux(void)
 {
+	static const iomux_v3_cfg_t weim_smc911x_pads[] = {
+		/* Data bus */
+		NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+
+		/* Address lines */
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+				PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+
+		/* other EIM signals for ethernet */
+		MX53_PAD_EIM_OE__EMI_WEIM_OE,
+		MX53_PAD_EIM_RW__EMI_WEIM_RW,
+		MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
+	};
+
 	/* ETHERNET_INT as GPIO2_31 */
-	mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
 	gpio_direction_input(ETHERNET_INT);
 
-	/* Data bus */
-	mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
-
-	/* Address lines */
-	mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
-
-	mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
-
-	/* other EIM signals for ethernet */
-	mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
+	/* WEIM bus */
+	imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
+						ARRAY_SIZE(weim_smc911x_pads));
 }
 
 static void weim_cs1_settings(void)
-- 
1.7.10.4

[U-Boot] [PATCH 09/12] imx: mx53evk: Convert to iomux-v3

[Benoît Thébaudeau]

There is no change of behavior.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 board/freescale/mx53evk/mx53evk.c |  289 +++++++++++--------------------------
 1 file changed, 83 insertions(+), 206 deletions(-)

diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index 1273501..c984339 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -23,11 +23,10 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <asm/errno.h>
 #include <asm/imx-common/boot_mode.h>
 #include <netdev.h>
@@ -49,69 +48,42 @@ int dram_init(void)
 	return 0;
 }
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_uart(void)
 {
-	/* UART1 RXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
-
-	/* UART1 TXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_ODE)
+
 static void setup_i2c(unsigned int port_number)
 {
+	static const iomux_v3_cfg_t i2c1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+	};
+
+	static const iomux_v3_cfg_t i2c2_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
+	};
+
 	switch (port_number) {
 	case 0:
-		/* i2c1 SDA */
-		mxc_request_iomux(MX53_PIN_CSI0_D8,
-				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
-		mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
-				INPUT_CTL_PATH0);
-		mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
-				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-		/* i2c1 SCL */
-		mxc_request_iomux(MX53_PIN_CSI0_D9,
-				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
-		mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
-				INPUT_CTL_PATH0);
-		mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
-				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		imx_iomux_v3_setup_multiple_pads(i2c1_pads,
+							ARRAY_SIZE(i2c1_pads));
 		break;
 	case 1:
-		/* i2c2 SDA */
-		mxc_request_iomux(MX53_PIN_KEY_ROW3,
-				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
-		mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
-				INPUT_CTL_PATH0);
-		mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
-				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-
-		/* i2c2 SCL */
-		mxc_request_iomux(MX53_PIN_KEY_COL3,
-				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
-		mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
-				INPUT_CTL_PATH0);
-		mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
-				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+		imx_iomux_v3_setup_multiple_pads(i2c2_pads,
+							ARRAY_SIZE(i2c2_pads));
 		break;
 	default:
 		printf("Warning: Wrong I2C port number\n");
@@ -160,54 +132,26 @@ void power_init(void)
 
 static void setup_iomux_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
-	/*FEC_MDC*/
-	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
-	/* FEC RXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	 /* FEC TXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC CRS */
-	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -221,9 +165,9 @@ int board_mmc_getcd(struct mmc *mmc)
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret;
 
-	mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
 	gpio_direction_input(IMX_GPIO_NR(3, 11));
-	mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
 	gpio_direction_input(IMX_GPIO_NR(3, 13));
 
 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
@@ -234,8 +178,38 @@ int board_mmc_getcd(struct mmc *mmc)
 	return ret;
 }
 
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+	};
+
+	static const iomux_v3_cfg_t sd2_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+				SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA11__GPIO3_11,
+	};
+
 	u32 index;
 	s32 status = 0;
 
@@ -245,109 +219,12 @@ int board_mmc_init(bd_t *bis)
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:
-			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA0,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA1,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA2,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA3,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_EIM_DA13,
-						IOMUX_CONFIG_ALT1);
-
-			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
 			break;
 		case 1:
-			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_IORDY,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_DATA8,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA9,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA10,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA11,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA0,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA1,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA2,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA3,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_EIM_DA11,
-						IOMUX_CONFIG_ALT1);
-
-			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-
+			imx_iomux_v3_setup_multiple_pads(sd2_pads,
+							 ARRAY_SIZE(sd2_pads));
 			break;
 		default:
 			printf("Warning: you configured more ESDHC controller"
-- 
1.7.10.4

[U-Boot] [PATCH 10/12] imx: mx53loco: Convert to iomux-v3

[Benoît Thébaudeau]

There is no change of behavior.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 board/freescale/mx53loco/mx53loco.c       |  268 +++++++++--------------------
 board/freescale/mx53loco/mx53loco_video.c |   68 ++++----
 2 files changed, 113 insertions(+), 223 deletions(-)

diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index 8f39c38..10e9d36 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -24,11 +24,10 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/imx-common/mx5_video.h>
@@ -82,86 +81,51 @@ u32 get_board_rev(void)
 	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 }
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_uart(void)
 {
-	/* UART1 RXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
-
-	/* UART1 TXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 #ifdef CONFIG_USB_EHCI_MX5
 int board_ehci_hcd_init(int port)
 {
 	/* request VBUS power enable pin, GPIO7_8 */
-	mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
+	imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
+	gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
 	return 0;
 }
 #endif
 
 static void setup_iomux_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
-	/*FEC_MDC*/
-	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
-	/* FEC RXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	 /* FEC TXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC CRS */
-	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -175,9 +139,9 @@ int board_mmc_getcd(struct mmc *mmc)
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret;
 
-	mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
 	gpio_direction_input(IMX_GPIO_NR(3, 11));
-	mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
 	gpio_direction_input(IMX_GPIO_NR(3, 13));
 
 	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
@@ -188,8 +152,38 @@ int board_mmc_getcd(struct mmc *mmc)
 	return ret;
 }
 
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+	};
+
+	static const iomux_v3_cfg_t sd2_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+				SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA11__GPIO3_11,
+	};
+
 	u32 index;
 	s32 status = 0;
 
@@ -199,109 +193,12 @@ int board_mmc_init(bd_t *bis)
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:
-			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA0,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA1,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA2,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA3,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_EIM_DA13,
-						IOMUX_CONFIG_ALT1);
-
-			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
 			break;
 		case 1:
-			mxc_request_iomux(MX53_PIN_ATA_RESET_B,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_IORDY,
-						IOMUX_CONFIG_ALT2);
-			mxc_request_iomux(MX53_PIN_ATA_DATA8,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA9,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA10,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA11,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA0,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA1,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA2,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_ATA_DATA3,
-						IOMUX_CONFIG_ALT4);
-			mxc_request_iomux(MX53_PIN_EIM_DA11,
-						IOMUX_CONFIG_ALT1);
-
-			mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-
+			imx_iomux_v3_setup_multiple_pads(sd2_pads,
+							 ARRAY_SIZE(sd2_pads));
 			break;
 		default:
 			printf("Warning: you configured more ESDHC controller"
@@ -316,28 +213,17 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_i2c(void)
 {
-	/* I2C1 SDA */
-	mxc_request_iomux(MX53_PIN_CSI0_D8,
-		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
-		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	/* I2C1 SCL */
-	mxc_request_iomux(MX53_PIN_CSI0_D9,
-		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
-	mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
-		INPUT_CTL_PATH0);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
-		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
-		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
-		PAD_CTL_PUE_PULL |
-		PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	static const iomux_v3_cfg_t i2c1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
 }
 
 static int power_init(void)
diff --git a/board/freescale/mx53loco/mx53loco_video.c b/board/freescale/mx53loco/mx53loco_video.c
index a4d5a6a..c4654c9 100644
--- a/board/freescale/mx53loco/mx53loco_video.c
+++ b/board/freescale/mx53loco/mx53loco_video.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <linux/list.h>
 #include <asm/gpio.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
 
@@ -63,42 +63,46 @@ static struct fb_videomode const seiko_wvga = {
 
 void setup_iomux_lcd(void)
 {
-	mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0);
-	mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0);
+	static const iomux_v3_cfg_t lcd_pads[] = {
+		MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+		MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+		MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+		MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+		MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+		MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+		MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+		MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+		MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+		MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+		MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+		MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+		MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+		MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+		MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+		MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+		MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+		MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+		MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+		MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+		MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+		MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+		MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+		MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+		MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+		MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+		MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+		MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 
 	/* Turn on GPIO backlight */
-	mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_D24__GPIO3_24);
 	gpio_direction_output(MX53LOCO_LCD_POWER, 1);
 
 	/* Turn on display contrast */
-	mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+	gpio_direction_output(IMX_GPIO_NR(1, 1), 1);
 }
 
 int board_video_skip(void)
-- 
1.7.10.4

[U-Boot] [PATCH 11/12] imx: mx53smd: Convert to iomux-v3

[Benoît Thébaudeau]

There is no change of behavior.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 board/freescale/mx53smd/mx53smd.c |  152 ++++++++++++-------------------------
 1 file changed, 48 insertions(+), 104 deletions(-)

diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
index 761f727..d04f44f 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -23,11 +23,10 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
 #include <asm/errno.h>
 #include <netdev.h>
 #include <mmc.h>
@@ -56,76 +55,41 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 }
 
+#define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
 static void setup_iomux_uart(void)
 {
-	/* UART1 RXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
-
-	/* UART1 TXD */
-	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
-				PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	static const iomux_v3_cfg_t uart_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
 static void setup_iomux_fec(void)
 {
-	/*FEC_MDIO*/
-	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
-	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
-	/*FEC_MDC*/
-	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
-	/* FEC RXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	 /* FEC TXD1 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
-	/* FEC TXD0 */
-	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_EN */
-	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
-	/* FEC TX_CLK */
-	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC RX_ER */
-	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
-	/* FEC CRS */
-	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+	static const iomux_v3_cfg_t fec_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -135,13 +99,28 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = {
 
 int board_mmc_getcd(struct mmc *mmc)
 {
-	mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+	imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
 	gpio_direction_input(IMX_GPIO_NR(3, 13));
 	return !gpio_get_value(IMX_GPIO_NR(3, 13));
 }
 
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
 int board_mmc_init(bd_t *bis)
 {
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+	};
+
 	u32 index;
 	s32 status = 0;
 
@@ -150,43 +129,8 @@ int board_mmc_init(bd_t *bis)
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:
-			mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA0,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA1,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA2,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_SD1_DATA3,
-						IOMUX_CONFIG_ALT0);
-			mxc_request_iomux(MX53_PIN_EIM_DA13,
-						IOMUX_CONFIG_ALT1);
-
-			mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
-				PAD_CTL_DRV_HIGH);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
-			mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
-				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
-				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
-				PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+			imx_iomux_v3_setup_multiple_pads(sd1_pads,
+							 ARRAY_SIZE(sd1_pads));
 			break;
 
 		default:
-- 
1.7.10.4

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Benoît Thébaudeau]

Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
---
 arch/arm/cpu/armv7/mx5/Makefile           |    2 +-
 arch/arm/cpu/armv7/mx5/iomux.c            |  186 ------
 arch/arm/include/asm/arch-mx5/iomux.h     |   91 ---
 arch/arm/include/asm/arch-mx5/mx5x_pins.h |  879 -----------------------------
 drivers/usb/host/ehci-mx5.c               |   73 ---
 include/usb/ehci-fsl.h                    |    6 -
 6 files changed, 1 insertion(+), 1236 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/mx5/iomux.c
 delete mode 100644 arch/arm/include/asm/arch-mx5/iomux.h
 delete mode 100644 arch/arm/include/asm/arch-mx5/mx5x_pins.h

diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
index ecd1184..e05fae9 100644
--- a/arch/arm/cpu/armv7/mx5/Makefile
+++ b/arch/arm/cpu/armv7/mx5/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	= soc.o clock.o iomux.o
+COBJS	= soc.o clock.o
 SOBJS = lowlevel_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/mx5/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c
deleted file mode 100644
index d4e3bbb..0000000
--- a/arch/arm/cpu/armv7/mx5/iomux.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-
-/* IOMUX register (base) addresses */
-enum iomux_reg_addr {
-	IOMUXGPR0 = IOMUXC_BASE_ADDR,
-	IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
-	IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
-	IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
-	IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
-	IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
-};
-
-#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
-
-/* Get the iomux register address of this pin */
-static inline u32 get_mux_reg(iomux_pin_name_t pin)
-{
-	u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
-#if defined(CONFIG_MX51)
-	if (is_soc_rev(CHIP_REV_2_0) < 0) {
-		/*
-		 * Fixup register address:
-		 * i.MX51 TO1 has offset with the register
-		 * which is define as TO2.
-		 */
-		if ((pin == MX51_PIN_NANDF_RB5) ||
-			(pin == MX51_PIN_NANDF_RB6) ||
-			(pin == MX51_PIN_NANDF_RB7))
-			; /* Do nothing */
-		else if (mux_reg >= 0x2FC)
-			mux_reg += 8;
-		else if (mux_reg >= 0x130)
-			mux_reg += 0xC;
-	}
-#endif
-	mux_reg += IOMUXSW_MUX_CTL;
-	return mux_reg;
-}
-
-/* Get the pad register address of this pin */
-static inline u32 get_pad_reg(iomux_pin_name_t pin)
-{
-	u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
-#if defined(CONFIG_MX51)
-	if (is_soc_rev(CHIP_REV_2_0) < 0) {
-		/*
-		 * Fixup register address:
-		 * i.MX51 TO1 has offset with the register
-		 * which is define as TO2.
-		 */
-		if ((pin == MX51_PIN_NANDF_RB5) ||
-			(pin == MX51_PIN_NANDF_RB6) ||
-			(pin == MX51_PIN_NANDF_RB7))
-			; /* Do nothing */
-		else if (pad_reg == 0x4D0 - PAD_I_START)
-			pad_reg += 0x4C;
-		else if (pad_reg == 0x860 - PAD_I_START)
-			pad_reg += 0x9C;
-		else if (pad_reg >= 0x804 - PAD_I_START)
-			pad_reg += 0xB0;
-		else if (pad_reg >= 0x7FC - PAD_I_START)
-			pad_reg += 0xB4;
-		else if (pad_reg >= 0x4E4 - PAD_I_START)
-			pad_reg += 0xCC;
-		else
-			pad_reg += 8;
-	}
-#endif
-	pad_reg += IOMUXSW_PAD_CTL;
-	return pad_reg;
-}
-
-/* Get the last iomux register address */
-static inline u32 get_mux_end(void)
-{
-#if defined(CONFIG_MX51)
-	if (is_soc_rev(CHIP_REV_2_0) < 0)
-		return IOMUXC_BASE_ADDR + (0x3F8 - 4);
-	else
-		return IOMUXC_BASE_ADDR + (0x3F0 - 4);
-#endif
-	return IOMUXSW_MUX_END;
-}
-
-/*
- * This function is used to configure a pin through the IOMUX module.
- * @param  pin		a pin number as defined in iomux_pin_name_t
- * @param  cfg		an output function as defined in iomux_pin_cfg_t
- *
- * @return 		0 if successful; Non-zero otherwise
- */
-static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-	u32 mux_reg = get_mux_reg(pin);
-
-	if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
-		return ;
-	if (cfg == IOMUX_CONFIG_GPIO)
-		writel(PIN_TO_ALT_GPIO(pin), mux_reg);
-	else
-		writel(cfg, mux_reg);
-}
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- *
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-	iomux_config_mux(pin, cfg);
-}
-
-/*
- * Release ownership for an IO pin
- *
- * @param  pin		a name defined by iomux_pin_name_t
- * @param  cfg		an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param  pin     a pin number as defined in iomux_pin_name_t
- * @param  config  the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
-	u32 pad_reg = get_pad_reg(pin);
-	writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
-	u32 pad_reg = get_pad_reg(pin);
-	return readl(pad_reg);
-}
-
-/*
- * This function configures daisy-chain
- *
- * @param input    index of input select register
- * @param config   the binary value of elements
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
-	u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
-	writel(config, reg);
-}
diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h
deleted file mode 100644
index e3765a3..0000000
--- a/arch/arm/include/asm/arch-mx5/iomux.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX5_IOMUX_H__
-#define __MACH_MX5_IOMUX_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-
-typedef unsigned int iomux_pin_name_t;
-
-/* various IOMUX output functions */
-typedef enum iomux_config {
-	IOMUX_CONFIG_ALT0,	/*!< used as alternate function 0 */
-	IOMUX_CONFIG_ALT1,	/*!< used as alternate function 1 */
-	IOMUX_CONFIG_ALT2,	/*!< used as alternate function 2 */
-	IOMUX_CONFIG_ALT3,	/*!< used as alternate function 3 */
-	IOMUX_CONFIG_ALT4,	/*!< used as alternate function 4 */
-	IOMUX_CONFIG_ALT5,	/*!< used as alternate function 5 */
-	IOMUX_CONFIG_ALT6,	/*!< used as alternate function 6 */
-	IOMUX_CONFIG_ALT7,	/*!< used as alternate function 7 */
-	IOMUX_CONFIG_GPIO,	/*!< added to help user use GPIO mode */
-	IOMUX_CONFIG_SION = 0x1 << 4,	/*!< used as LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
-/* various IOMUX pad functions */
-typedef enum iomux_pad_config {
-	PAD_CTL_SRE_SLOW = 0x0 << 0,	/* Slow slew rate */
-	PAD_CTL_SRE_FAST = 0x1 << 0,	/* Fast slew rate */
-	PAD_CTL_DRV_LOW = 0x0 << 1,	/* Low drive strength */
-	PAD_CTL_DRV_MEDIUM = 0x1 << 1,	/* Medium drive strength */
-	PAD_CTL_DRV_HIGH = 0x2 << 1,	/* High drive strength */
-	PAD_CTL_DRV_MAX = 0x3 << 1,	/* Max drive strength */
-	PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,	/* Opendrain disable */
-	PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */
-	PAD_CTL_100K_PD = 0x0 << 4,	/* 100Kohm pulldown */
-	PAD_CTL_47K_PU = 0x1 << 4,	/* 47Kohm pullup */
-	PAD_CTL_100K_PU = 0x2 << 4,	/* 100Kohm pullup */
-	PAD_CTL_22K_PU = 0x3 << 4,	/* 22Kohm pullup */
-	PAD_CTL_PUE_KEEPER = 0x0 << 6,	/* enable pulldown */
-	PAD_CTL_PUE_PULL = 0x1 << 6,	/* enable pullup */
-	PAD_CTL_PKE_NONE = 0x0 << 7,	/* Disable pullup/pulldown */
-	PAD_CTL_PKE_ENABLE = 0x1 << 7,	/* Enable pullup/pulldown */
-	PAD_CTL_HYS_NONE = 0x0 << 8,	/* Hysteresis disabled */
-	PAD_CTL_HYS_ENABLE = 0x1 << 8,	/* Hysteresis enabled */
-	PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
-	PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
-	PAD_CTL_DRV_VOT_LOW = 0x1 << 13, /* Low voltage mode */
-	PAD_CTL_DRV_VOT_HIGH = 0x0 << 13,/* High voltage mode */
-} iomux_pad_config_t;
-
-/* various IOMUX input functions */
-typedef enum iomux_input_config {
-	INPUT_CTL_PATH0 = 0x0,
-	INPUT_CTL_PATH1,
-	INPUT_CTL_PATH2,
-	INPUT_CTL_PATH3,
-	INPUT_CTL_PATH4,
-	INPUT_CTL_PATH5,
-	INPUT_CTL_PATH6,
-	INPUT_CTL_PATH7,
-} iomux_input_config_t;
-
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-
-#endif				/*  __MACH_MX5_IOMUX_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
deleted file mode 100644
index 3457f6a..0000000
--- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h
+++ /dev/null
@@ -1,879 +0,0 @@
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
-#define __ASM_ARCH_MX5_MX5X_PINS_H__
-
-#ifndef __ASSEMBLY__
-
-/*
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |  23 - 21 | 20  - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P  |  IO_I   | GPIO_I   | PAD_I   | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * The IOMUX controller can be split in two parts. At the begeinning,
- * there is the register definitions for the multiplexing each pin.
- * Then there is a set of registers (PAD_I) to configure each pin
- * (pullup, pulldown, etc).
- * PAD_I defines the offset of the pad register for each pin.
- * GPIO_I defines, if available, the number of gpio that can be
- * connected to that pad
- * IO_I defines the multiplexer mode required to set the pad in gpio mode
- * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
- *
- * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
- *    ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
- * It means the mux control register is@register offset 0x28. The pad control
- * register offset is: 0x250 and also occupy the least significant bits
- * within the register.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I			0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I			10
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I			21
-
-#define MUX_IO_P                29
-#define MUX_IO_I                24
-#define IOMUX_TO_GPIO(pin)      ((((unsigned int)pin >> MUX_IO_P) * \
-					GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
-					((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin)       (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-
-#define NON_GPIO_PORT		0x7
-#define PIN_TO_MUX_MASK		((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK		((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK		((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I              PIN_TO_MUX_MASK
-#define NON_PAD_I              PIN_TO_PAD_MASK
-
-#if defined(CONFIG_MX51)
-#define MUX_I_START		0x001C
-#define PAD_I_START		0x3F0
-#define INPUT_CTL_START		0x8C4
-#define MUX_I_END		(PAD_I_START - 4)
-#elif defined(CONFIG_MX53)
-#define MUX_I_START            0x0020
-#define PAD_I_START            0x348
-#define INPUT_CTL_START        0x730
-#define MUX_I_END              (PAD_I_START - 4)
-#else
-#error "CPU_TYPE not defined"
-#endif
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
-	(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
-	((mi) << MUX_I) | \
-	((pi - PAD_I_START) << PAD_I) | \
-	((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
-	_MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
-	_MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin)	((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin)	((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin)	((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin)	(PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum {
-	MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
-	MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
-	MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
-	MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
-	MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
-	MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
-	MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
-	MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
-	MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
-	MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
-	MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
-	MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
-	MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
-	MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
-	MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
-	MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
-	MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
-	MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
-	MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
-	MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
-	MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
-	MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
-	MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
-	MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
-	MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
-	MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
-	MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
-	MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
-	MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
-	MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
-	MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
-	MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
-	MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
-	MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
-	MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
-	MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
-	MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
-	MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
-	MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
-	MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
-	MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
-	MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
-	MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
-	MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
-	MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
-	MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
-	MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
-	MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
-	MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
-	MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
-	MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
-	MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
-	MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
-	MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
-	MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
-	MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
-	MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
-	MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
-	MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
-	MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
-	MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
-	MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
-	MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
-	MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
-	MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
-	MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
-	MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
-	MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
-	MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
-	MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
-	MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
-	MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
-	MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
-	MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
-	MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
-	MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
-	MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
-	MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
-	MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
-	MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
-	MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
-	MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
-	MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
-	MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
-	MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
-	MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
-	MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
-	MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
-	MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
-	MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
-	MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
-	MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
-	MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
-	MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
-	MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
-	MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
-	MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
-	MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
-	MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
-	MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
-	MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
-	MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
-	MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
-	MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
-	MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
-	MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
-	MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
-	MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
-	MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
-	MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
-	MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
-	MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
-	MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
-	MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
-	MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
-	MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
-	MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
-	MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
-	MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
-	MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
-	MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
-	MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
-	MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
-	MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
-	MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
-	MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
-	MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
-	MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
-	MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
-	MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
-	MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
-	MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
-	MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
-	MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
-	MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
-	MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
-	MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
-	MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
-	MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
-	MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
-	MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
-	MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
-	MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
-	MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
-	MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
-	MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
-	MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
-	MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
-	MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
-	MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
-	MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
-	MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
-	MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
-	MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
-	MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
-	MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
-	MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
-	MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
-	MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
-	MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
-	MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
-	MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
-	MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
-	MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
-	MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
-	MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
-	MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
-	MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
-	MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
-	MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
-	MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
-	MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
-	MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
-	MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
-	MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
-	MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
-	MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
-	MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
-	MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
-	MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
-	MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
-	MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
-	MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
-	MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
-	MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
-	MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
-	MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
-	MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
-	MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
-	MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
-	MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
-	MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
-	MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
-	MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
-	MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
-	MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
-	MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
-	MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
-	MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
-	MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
-	MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
-	MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
-	MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
-	MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
-	MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
-	MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
-	MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
-	MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
-	MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
-	MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
-	MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
-	MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
-	MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
-	MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
-	MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
-	MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
-	MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
-	MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
-	MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
-	MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
-	MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
-	MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
-	MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
-	MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
-	MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
-	MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
-	MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
-	MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
-	MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
-	MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
-	MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
-	MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
-	MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
-	MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
-	MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
-	MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
-	MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
-	MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
-	MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
-	MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
-	MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
-	MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
-	MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
-	MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
-	MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
-	MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
-	MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
-	MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
-	MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
-	MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
-	MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
-	MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
-
-	/* The following are PADS used for drive strength */
-
-	MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
-	MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
-	MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
-	MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
-	MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
-	MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
-	MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
-	MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
-	MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
-	MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
-	MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
-	MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
-	MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
-	MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
-	MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
-	MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
-	MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
-	MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
-	MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
-	MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
-	MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
-	MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
-	MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
-	MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
-	MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
-	MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
-	MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
-	MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
-	MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
-	MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
-	MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
-	MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
-	MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
-	MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
-	MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
-	MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
-	MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
-	MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
-	MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
-	MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
-	MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
-};
-
-enum {
-	MX53_PIN_GPIO_19  = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
-	MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
-	MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
-	MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
-	MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
-	MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
-	MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
-	MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
-	MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
-	MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
-	MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
-	MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
-	MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
-	MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
-	MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
-	MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
-	MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
-	MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
-	MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
-	MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
-	MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
-	MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
-	MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
-	MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
-	MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
-	MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
-	MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
-	MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
-	MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
-	MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
-	MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
-	MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
-	MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
-	MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
-	MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
-	MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
-	MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
-	MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
-	MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
-	MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
-	MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
-	MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
-	MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
-	MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
-	MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
-	MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
-	MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
-	MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
-	MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
-	MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
-	MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
-	MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
-	MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
-	MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
-	MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
-	MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
-	MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
-	MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
-	MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
-	MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
-	MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
-	MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
-	MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
-	MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
-	MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
-	MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
-	MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
-	MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
-	MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
-	MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
-	MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
-	MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
-	MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
-	MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
-	MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
-	MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
-	MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
-	MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
-	MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
-	MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
-	MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
-	MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
-	MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
-	MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
-	MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
-	MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
-	MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
-	MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
-	MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
-	MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
-	MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
-	MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
-	MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
-	MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
-	MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
-	MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
-	MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
-	MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
-	MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
-	MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
-	MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
-	MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
-	MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
-	MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
-	MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
-	MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
-	MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
-	MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
-	MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
-	MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
-	MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
-	MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
-	MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
-	MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
-	MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
-	MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
-	MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
-	MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
-	MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
-	MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
-	MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
-	MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
-	MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
-	MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
-	MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
-	MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
-	MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
-	MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
-	MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
-	MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
-	MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
-	MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
-	MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
-	MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
-	MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
-	MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
-	MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
-	MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
-	MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
-	MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
-	MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
-	MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
-	MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
-	MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
-	MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
-	MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
-	MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
-	MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
-	MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
-	MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
-	MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
-	MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
-	MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
-	MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
-	MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
-	MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
-	MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
-	MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
-	MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
-	MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
-	MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
-	MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
-	MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
-	MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
-	MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
-	MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
-	MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
-	MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
-	MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
-	MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
-	MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
-	MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
-	MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
-	MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
-	MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
-	MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
-	MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
-	MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
-	MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
-	MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
-	MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
-	MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
-	MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
-	MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
-	MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
-	MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
-	MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
-	MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
-	MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
-	MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
-	MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
-	MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
-	MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
-	MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
-	MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
-	MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
-	MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
-	MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
-	MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
-	MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
-	MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
-	MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
-	MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
-	MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
-	MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
-	MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
-	MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
-	MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
-	MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
-	MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
-	MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
-	MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
-	MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
-	MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
-	MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
-	MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
-	MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
-	MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
-	MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
-	MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
-	MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
-	MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
-	MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
-	MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
-	MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
-	MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
-	MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
-	MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
-	MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
-	MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
-	MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
-	MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
-	MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
-	MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
-	MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
-	MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
-	MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
-	MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
-	MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
-	MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
-	MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
-	MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
-	MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
-	MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
-	MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
-	MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
-	MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
-	MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
-	MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
-	MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
-	MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
-	MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
-	MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
-	MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
-	MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
-	MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
-	MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
-};
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
-	MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-	MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-	MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
-	MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
-	/* TO2 */
-	MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
-	MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-	MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-	MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-	MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
-	/* TO2 */
-	MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
-	MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
-	MX51_FEC_FEC_COL_SELECT_INPUT,
-	MX51_FEC_FEC_CRS_SELECT_INPUT,
-	MX51_FEC_FEC_MDI_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
-	MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
-	MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
-	MX51_FEC_FEC_RX_DV_SELECT_INPUT,
-	MX51_FEC_FEC_RX_ER_SELECT_INPUT,
-	MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
-	MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
-	/* TO2 */
-	MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
-	MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-	MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
-	/* TO2 */
-	MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
-	/* TO2 */
-	MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
-	MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
-	MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
-	MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
-	MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
-	MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
-	MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-	MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-	MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
-	MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-	MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-	MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-	MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
-	MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
-	MX51PUT_NUM_MUX,
-	/* MX53 */
-	MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
-	MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
-	MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
-	MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
-	MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
-	MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
-	MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT,
-	MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
-	MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
-	MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
-	MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
-	MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
-	MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
-	MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
-	MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
-	MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
-	MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
-	MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT,
-	MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
-	MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
-	MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
-	MX53_FEC_FEC_COL_SELECT_INPUT,
-	MX53_FEC_FEC_MDI_SELECT_INPUT,
-	MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
-	MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
-	MX53_GPC_PMIC_RDY_SELECT_INPUT,
-	MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
-	MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
-	MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
-	MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
-	MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
-	MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
-	MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
-	MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
-	MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
-	MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
-	MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
-	MX53_KPP_IPP_IND_COL_5_SELECT_INPUT,
-	MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
-	MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
-	MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
-	MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
-	MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
-	MX53_MLB_MLBCLK_IN_SELECT_INPUT,
-	MX53_MLB_MLBDAT_IN_SELECT_INPUT,
-	MX53_MLB_MLBSIG_IN_SELECT_INPUT,
-	MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
-	MX53_SDMA_EVENTS_14_SELECT_INPUT,
-	MX53_SDMA_EVENTS_15_SELECT_INPUT,
-	MX53_SPDIF_SPDIF_IN1_SELECT_INPUT,
-	MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
-	MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
-	MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
-	MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
-	MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
-} iomux_input_select_t;
-
-#endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_ARCH_MX5_MX5X_PINS_H__ */
diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index adbed5c..f43c38d 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -21,8 +21,6 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
 
 #include "ehci.h"
 
@@ -87,77 +85,6 @@
 /* USB_CTRL_1 */
 #define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)
 
-/* USB pin configuration */
-#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
-			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
-
-#ifdef CONFIG_MX51
-/*
- * Configure the MX51 USB H1 IOMUX
- */
-void setup_iomux_usb_h1(void)
-{
-	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
-
-	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
-}
-
-/*
- * Configure the MX51 USB H2 IOMUX
- */
-void setup_iomux_usb_h2(void)
-{
-	mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
-
-	mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
-}
-#endif
-
 int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index a1438d6..29b136d 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -277,10 +277,4 @@ struct usb_ehci {
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);
 
-/* CPU-specific abstracted-out IOMUX init */
-#ifdef CONFIG_MX51
-void setup_iomux_usb_h1(void);
-void setup_iomux_usb_h2(void);
-#endif
-
 #endif /* _EHCI_FSL_H */
-- 
1.7.10.4

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Marek Vasut]

Dear Beno?t Th?baudeau,

> Legacy iomux support is no longer needed now that all boards have been
> converted to iomux-v3.
> 
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>

Yes, good move

Reviewed-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Benoît Thébaudeau]

Dear Marek Vasut,

On Friday, May 3, 2013 4:38:43 AM, Marek Vasut wrote:
> Dear Beno?t Th?baudeau,
> 
> > Legacy iomux support is no longer needed now that all boards have been
> > converted to iomux-v3.
> > 
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> 
> Yes, good move
> 
> Reviewed-by: Marek Vasut <marex@denx.de>

How do you plan to handle the conversion to iomux-v3 of the not-yet-applied
m53evk:
 - You rebase your series on mine?
 - I rebase my series on yours?
 - I convert m53evk, then I send you the file so that you can refactor your
   series and trivially rebase it on mine?

Best regards,
Beno?t

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Marek Vasut]

Dear Beno?t Th?baudeau,

> Dear Marek Vasut,
> 
> On Friday, May 3, 2013 4:38:43 AM, Marek Vasut wrote:
> > Dear Beno?t Th?baudeau,
> > 
> > > Legacy iomux support is no longer needed now that all boards have been
> > > converted to iomux-v3.
> > > 
> > > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > 
> > Yes, good move
> > 
> > Reviewed-by: Marek Vasut <marex@denx.de>
> 
> How do you plan to handle the conversion to iomux-v3 of the not-yet-applied
> m53evk:
>  - You rebase your series on mine?
>  - I rebase my series on yours?

Did you not send this stuff after m53evk? So let's let Stefano merge it all in 
sequence (poor Stefano though, patches seem to be piling up).

>  - I convert m53evk, then I send you the file so that you can refactor your
>    series and trivially rebase it on mine?

I can convert it, but being lazy as hell, of course the idea of you doing all 
the work seems very tempting ;-)

Best regards,
Marek Vasut

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Benoît Thébaudeau]

Dear Marek Vasut,

On Friday, May 3, 2013 2:42:04 PM, Marek Vasut wrote:
> Dear Beno?t Th?baudeau,
> 
> > Dear Marek Vasut,
> > 
> > On Friday, May 3, 2013 4:38:43 AM, Marek Vasut wrote:
> > > Dear Beno?t Th?baudeau,
> > > 
> > > > Legacy iomux support is no longer needed now that all boards have been
> > > > converted to iomux-v3.
> > > > 
> > > > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > > 
> > > Yes, good move
> > > 
> > > Reviewed-by: Marek Vasut <marex@denx.de>
> > 
> > How do you plan to handle the conversion to iomux-v3 of the not-yet-applied
> > m53evk:
> >  - You rebase your series on mine?
> >  - I rebase my series on yours?
> 
> Did you not send this stuff after m53evk?

Correct.

> So let's let Stefano merge it all
> in
> sequence

We can do that, but this will add another conversion patch that would not be
needed the other way around, for something not yet applied.

> (poor Stefano though, patches seem to be piling up).

True.

> >  - I convert m53evk, then I send you the file so that you can refactor your
> >    series and trivially rebase it on mine?
> 
> I can convert it, but being lazy as hell, of course the idea of you doing all
> the work seems very tempting ;-)

After having done all other boards, one more should be quick. ;)

So I will:
 - Extract m53evk.c from your series.
 - Convert it to iomux-v3.
 - Send it to you.

Then you will:
 - Update and resend your series with this file.

Then Stefano will:
 - Apply my mx25/35/5x series.
 - Apply your converted m53evk series.

Does it sound like a good plan to you?

Best regards,
Beno?t

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Marek Vasut]

Dear Beno?t Th?baudeau,

> Dear Marek Vasut,
> 
> On Friday, May 3, 2013 2:42:04 PM, Marek Vasut wrote:
> > Dear Beno?t Th?baudeau,
> > 
> > > Dear Marek Vasut,
> > > 
> > > On Friday, May 3, 2013 4:38:43 AM, Marek Vasut wrote:
> > > > Dear Beno?t Th?baudeau,
> > > > 
> > > > > Legacy iomux support is no longer needed now that all boards have
> > > > > been converted to iomux-v3.
> > > > > 
> > > > > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > > > 
> > > > Yes, good move
> > > > 
> > > > Reviewed-by: Marek Vasut <marex@denx.de>
> > > 
> > > How do you plan to handle the conversion to iomux-v3 of the
> > > not-yet-applied
> > > 
> > > m53evk:
> > >  - You rebase your series on mine?
> > >  - I rebase my series on yours?
> > 
> > Did you not send this stuff after m53evk?
> 
> Correct.
> 
> > So let's let Stefano merge it all
> > in
> > sequence
> 
> We can do that, but this will add another conversion patch that would not
> be needed the other way around, for something not yet applied.
> 
> > (poor Stefano though, patches seem to be piling up).
> 
> True.
> 
> > >  - I convert m53evk, then I send you the file so that you can refactor
> > >  your
> > >  
> > >    series and trivially rebase it on mine?
> > 
> > I can convert it, but being lazy as hell, of course the idea of you doing
> > all the work seems very tempting ;-)
> 
> After having done all other boards, one more should be quick. ;)
> 
> So I will:
>  - Extract m53evk.c from your series.
>  - Convert it to iomux-v3.
>  - Send it to you.
> 
> Then you will:
>  - Update and resend your series with this file.
> 
> Then Stefano will:
>  - Apply my mx25/35/5x series.
>  - Apply your converted m53evk series.

Hm, I will still argument with the fact that yours was sent later and for me, 
this will mean another round of testing. If we swap them, I will have a good 
bisect point right before your series too.

Best regards,
Marek Vasut

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Benoît Thébaudeau]

Dear Marek Vasut,

On Friday, May 3, 2013 3:18:33 PM, Marek Vasut wrote:
> Dear Beno?t Th?baudeau,
> 
> > Dear Marek Vasut,
> > 
> > On Friday, May 3, 2013 2:42:04 PM, Marek Vasut wrote:
> > > Dear Beno?t Th?baudeau,
> > > 
> > > > Dear Marek Vasut,
> > > > 
> > > > On Friday, May 3, 2013 4:38:43 AM, Marek Vasut wrote:
> > > > > Dear Beno?t Th?baudeau,
> > > > > 
> > > > > > Legacy iomux support is no longer needed now that all boards have
> > > > > > been converted to iomux-v3.
> > > > > > 
> > > > > > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > > > > 
> > > > > Yes, good move
> > > > > 
> > > > > Reviewed-by: Marek Vasut <marex@denx.de>
> > > > 
> > > > How do you plan to handle the conversion to iomux-v3 of the
> > > > not-yet-applied
> > > > 
> > > > m53evk:
> > > >  - You rebase your series on mine?
> > > >  - I rebase my series on yours?
> > > 
> > > Did you not send this stuff after m53evk?
> > 
> > Correct.
> > 
> > > So let's let Stefano merge it all
> > > in
> > > sequence
> > 
> > We can do that, but this will add another conversion patch that would not
> > be needed the other way around, for something not yet applied.
> > 
> > > (poor Stefano though, patches seem to be piling up).
> > 
> > True.
> > 
> > > >  - I convert m53evk, then I send you the file so that you can refactor
> > > >  your
> > > >  
> > > >    series and trivially rebase it on mine?
> > > 
> > > I can convert it, but being lazy as hell, of course the idea of you doing
> > > all the work seems very tempting ;-)
> > 
> > After having done all other boards, one more should be quick. ;)
> > 
> > So I will:
> >  - Extract m53evk.c from your series.
> >  - Convert it to iomux-v3.
> >  - Send it to you.
> > 
> > Then you will:
> >  - Update and resend your series with this file.
> > 
> > Then Stefano will:
> >  - Apply my mx25/35/5x series.
> >  - Apply your converted m53evk series.
> 
> Hm, I will still argument with the fact that yours was sent later and for me,
> this will mean another round of testing. If we swap them, I will have a good
> bisect point right before your series too.

OK, then I will just send a standalone patch converting m53evk to iomux-v3, and
I will tell Stefano where to insert it in my mx5x iomux series, or he can also
choose to merge it to your series as a fixup patch, depending on the order he
prefers to apply things.

Best regards,
Beno?t

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Marek Vasut]

Dear Beno?t Th?baudeau,

> Dear Marek Vasut,
> 
> On Friday, May 3, 2013 3:18:33 PM, Marek Vasut wrote:
> > Dear Beno?t Th?baudeau,
> > 
> > > Dear Marek Vasut,
> > > 
> > > On Friday, May 3, 2013 2:42:04 PM, Marek Vasut wrote:
> > > > Dear Beno?t Th?baudeau,
> > > > 
> > > > > Dear Marek Vasut,
> > > > > 
> > > > > On Friday, May 3, 2013 4:38:43 AM, Marek Vasut wrote:
> > > > > > Dear Beno?t Th?baudeau,
> > > > > > 
> > > > > > > Legacy iomux support is no longer needed now that all boards
> > > > > > > have been converted to iomux-v3.
> > > > > > > 
> > > > > > > Signed-off-by: Beno?t Th?baudeau
> > > > > > > <benoit.thebaudeau@advansee.com>
> > > > > > 
> > > > > > Yes, good move
> > > > > > 
> > > > > > Reviewed-by: Marek Vasut <marex@denx.de>
> > > > > 
> > > > > How do you plan to handle the conversion to iomux-v3 of the
> > > > > not-yet-applied
> > > > > 
> > > > > m53evk:
> > > > >  - You rebase your series on mine?
> > > > >  - I rebase my series on yours?
> > > > 
> > > > Did you not send this stuff after m53evk?
> > > 
> > > Correct.
> > > 
> > > > So let's let Stefano merge it all
> > > > in
> > > > sequence
> > > 
> > > We can do that, but this will add another conversion patch that would
> > > not be needed the other way around, for something not yet applied.
> > > 
> > > > (poor Stefano though, patches seem to be piling up).
> > > 
> > > True.
> > > 
> > > > >  - I convert m53evk, then I send you the file so that you can
> > > > >  refactor your
> > > > >  
> > > > >    series and trivially rebase it on mine?
> > > > 
> > > > I can convert it, but being lazy as hell, of course the idea of you
> > > > doing all the work seems very tempting ;-)
> > > 
> > > After having done all other boards, one more should be quick. ;)
> > > 
> > > So I will:
> > >  - Extract m53evk.c from your series.
> > >  - Convert it to iomux-v3.
> > >  - Send it to you.
> > > 
> > > Then you will:
> > >  - Update and resend your series with this file.
> > > 
> > > Then Stefano will:
> > >  - Apply my mx25/35/5x series.
> > >  - Apply your converted m53evk series.
> > 
> > Hm, I will still argument with the fact that yours was sent later and for
> > me, this will mean another round of testing. If we swap them, I will
> > have a good bisect point right before your series too.
> 
> OK, then I will just send a standalone patch converting m53evk to iomux-v3,
> and I will tell Stefano where to insert it in my mx5x iomux series, or he
> can also choose to merge it to your series as a fixup patch, depending on
> the order he prefers to apply things.

You can also just send a V2 of this single patch, no ?

Best regards,
Marek Vasut

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Benoît Thébaudeau]

Dear Marek Vasut,

On Friday, May 3, 2013 3:39:39 PM, Marek Vasut wrote:
> Dear Beno?t Th?baudeau,
> 
> > Dear Marek Vasut,
> > 
> > On Friday, May 3, 2013 3:18:33 PM, Marek Vasut wrote:
> > > Dear Beno?t Th?baudeau,
> > > 
> > > > Dear Marek Vasut,
> > > > 
> > > > On Friday, May 3, 2013 2:42:04 PM, Marek Vasut wrote:
> > > > > Dear Beno?t Th?baudeau,
> > > > > 
> > > > > > Dear Marek Vasut,
> > > > > > 
> > > > > > On Friday, May 3, 2013 4:38:43 AM, Marek Vasut wrote:
> > > > > > > Dear Beno?t Th?baudeau,
> > > > > > > 
> > > > > > > > Legacy iomux support is no longer needed now that all boards
> > > > > > > > have been converted to iomux-v3.
> > > > > > > > 
> > > > > > > > Signed-off-by: Beno?t Th?baudeau
> > > > > > > > <benoit.thebaudeau@advansee.com>
> > > > > > > 
> > > > > > > Yes, good move
> > > > > > > 
> > > > > > > Reviewed-by: Marek Vasut <marex@denx.de>
> > > > > > 
> > > > > > How do you plan to handle the conversion to iomux-v3 of the
> > > > > > not-yet-applied
> > > > > > 
> > > > > > m53evk:
> > > > > >  - You rebase your series on mine?
> > > > > >  - I rebase my series on yours?
> > > > > 
> > > > > Did you not send this stuff after m53evk?
> > > > 
> > > > Correct.
> > > > 
> > > > > So let's let Stefano merge it all
> > > > > in
> > > > > sequence
> > > > 
> > > > We can do that, but this will add another conversion patch that would
> > > > not be needed the other way around, for something not yet applied.
> > > > 
> > > > > (poor Stefano though, patches seem to be piling up).
> > > > 
> > > > True.
> > > > 
> > > > > >  - I convert m53evk, then I send you the file so that you can
> > > > > >  refactor your
> > > > > >  
> > > > > >    series and trivially rebase it on mine?
> > > > > 
> > > > > I can convert it, but being lazy as hell, of course the idea of you
> > > > > doing all the work seems very tempting ;-)
> > > > 
> > > > After having done all other boards, one more should be quick. ;)
> > > > 
> > > > So I will:
> > > >  - Extract m53evk.c from your series.
> > > >  - Convert it to iomux-v3.
> > > >  - Send it to you.
> > > > 
> > > > Then you will:
> > > >  - Update and resend your series with this file.
> > > > 
> > > > Then Stefano will:
> > > >  - Apply my mx25/35/5x series.
> > > >  - Apply your converted m53evk series.
> > > 
> > > Hm, I will still argument with the fact that yours was sent later and for
> > > me, this will mean another round of testing. If we swap them, I will
> > > have a good bisect point right before your series too.
> > 
> > OK, then I will just send a standalone patch converting m53evk to iomux-v3,
> > and I will tell Stefano where to insert it in my mx5x iomux series, or he
> > can also choose to merge it to your series as a fixup patch, depending on
> > the order he prefers to apply things.
> 
> You can also just send a V2 of this single patch, no ?

But there is no V1!?

Or I could just send a V3 concatenating all my iomux series (there are
dependencies among those series) and rebasing them on top of yours in order to
make things easier and clearer for Stefano.

Best regards,
Beno?t

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Marek Vasut]

Dear Beno?t Th?baudeau,

> Dear Marek Vasut,
> 
> On Friday, May 3, 2013 3:39:39 PM, Marek Vasut wrote:
> > Dear Beno?t Th?baudeau,
> > 
> > > Dear Marek Vasut,
> > > 
> > > On Friday, May 3, 2013 3:18:33 PM, Marek Vasut wrote:
> > > > Dear Beno?t Th?baudeau,
> > > > 
> > > > > Dear Marek Vasut,
> > > > > 
> > > > > On Friday, May 3, 2013 2:42:04 PM, Marek Vasut wrote:
> > > > > > Dear Beno?t Th?baudeau,
> > > > > > 
> > > > > > > Dear Marek Vasut,
> > > > > > > 
> > > > > > > On Friday, May 3, 2013 4:38:43 AM, Marek Vasut wrote:
> > > > > > > > Dear Beno?t Th?baudeau,
> > > > > > > > 
> > > > > > > > > Legacy iomux support is no longer needed now that all
> > > > > > > > > boards have been converted to iomux-v3.
> > > > > > > > > 
> > > > > > > > > Signed-off-by: Beno?t Th?baudeau
> > > > > > > > > <benoit.thebaudeau@advansee.com>
> > > > > > > > 
> > > > > > > > Yes, good move
> > > > > > > > 
> > > > > > > > Reviewed-by: Marek Vasut <marex@denx.de>
> > > > > > > 
> > > > > > > How do you plan to handle the conversion to iomux-v3 of the
> > > > > > > not-yet-applied
> > > > > > > 
> > > > > > > m53evk:
> > > > > > >  - You rebase your series on mine?
> > > > > > >  - I rebase my series on yours?
> > > > > > 
> > > > > > Did you not send this stuff after m53evk?
> > > > > 
> > > > > Correct.
> > > > > 
> > > > > > So let's let Stefano merge it all
> > > > > > in
> > > > > > sequence
> > > > > 
> > > > > We can do that, but this will add another conversion patch that
> > > > > would not be needed the other way around, for something not yet
> > > > > applied.
> > > > > 
> > > > > > (poor Stefano though, patches seem to be piling up).
> > > > > 
> > > > > True.
> > > > > 
> > > > > > >  - I convert m53evk, then I send you the file so that you can
> > > > > > >  refactor your
> > > > > > >  
> > > > > > >    series and trivially rebase it on mine?
> > > > > > 
> > > > > > I can convert it, but being lazy as hell, of course the idea of
> > > > > > you doing all the work seems very tempting ;-)
> > > > > 
> > > > > After having done all other boards, one more should be quick. ;)
> > > > > 
> > > > > So I will:
> > > > >  - Extract m53evk.c from your series.
> > > > >  - Convert it to iomux-v3.
> > > > >  - Send it to you.
> > > > > 
> > > > > Then you will:
> > > > >  - Update and resend your series with this file.
> > > > > 
> > > > > Then Stefano will:
> > > > >  - Apply my mx25/35/5x series.
> > > > >  - Apply your converted m53evk series.
> > > > 
> > > > Hm, I will still argument with the fact that yours was sent later and
> > > > for me, this will mean another round of testing. If we swap them, I
> > > > will have a good bisect point right before your series too.
> > > 
> > > OK, then I will just send a standalone patch converting m53evk to
> > > iomux-v3, and I will tell Stefano where to insert it in my mx5x iomux
> > > series, or he can also choose to merge it to your series as a fixup
> > > patch, depending on the order he prefers to apply things.
> > 
> > You can also just send a V2 of this single patch, no ?
> 
> But there is no V1!?
> 
> Or I could just send a V3 concatenating all my iomux series (there are
> dependencies among those series) and rebasing them on top of yours in order
> to make things easier and clearer for Stefano.

Bah, I didn't know that. Ok, if you're up to fixing up M53EVK, send a patch that 
does it and let Stefano (or me?) amend it to the M53EVK patch.

Best regards,
Marek Vasut

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Stefano Babic]

On 03/05/2013 15:18, Marek Vasut wrote:
> Dear Beno?t Th?baudeau,
> 
>> Dear Marek Vasut,
>>
>> On Friday, May 3, 2013 2:42:04 PM, Marek Vasut wrote:
>>> Dear Beno?t Th?baudeau,
>>>
>>>> Dear Marek Vasut,
>>>>
>>>> On Friday, May 3, 2013 4:38:43 AM, Marek Vasut wrote:
>>>>> Dear Beno?t Th?baudeau,
>>>>>
>>>>>> Legacy iomux support is no longer needed now that all boards have
>>>>>> been converted to iomux-v3.
>>>>>>
>>>>>> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
>>>>>
>>>>> Yes, good move
>>>>>
>>>>> Reviewed-by: Marek Vasut <marex@denx.de>
>>>>
>>>> How do you plan to handle the conversion to iomux-v3 of the
>>>> not-yet-applied
>>>>
>>>> m53evk:
>>>>  - You rebase your series on mine?
>>>>  - I rebase my series on yours?
>>>
>>> Did you not send this stuff after m53evk?
>>
>> Correct.
>>
>>> So let's let Stefano merge it all
>>> in
>>> sequence
>>
>> We can do that, but this will add another conversion patch that would not
>> be needed the other way around, for something not yet applied.
>>
>>> (poor Stefano though, patches seem to be piling up).
>>
>> True.
>>
>>>>  - I convert m53evk, then I send you the file so that you can refactor
>>>>  your
>>>>  
>>>>    series and trivially rebase it on mine?
>>>
>>> I can convert it, but being lazy as hell, of course the idea of you doing
>>> all the work seems very tempting ;-)
>>
>> After having done all other boards, one more should be quick. ;)
>>
>> So I will:
>>  - Extract m53evk.c from your series.
>>  - Convert it to iomux-v3.
>>  - Send it to you.
>>
>> Then you will:
>>  - Update and resend your series with this file.
>>
>> Then Stefano will:
>>  - Apply my mx25/35/5x series.
>>  - Apply your converted m53evk series.
> 
> Hm, I will still argument with the fact that yours was sent later and for me, 
> this will mean another round of testing. If we swap them, I will have a good 
> bisect point right before your series too.

Marek, apart who send patches earlier, I stick with Benoit's approach.
The reason: first patches that provide a general framework (in this
case, the iomux) for the SOC, and then board support already using the
right approach.

Best regards,
Stefano


-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 12/12] imx: mx5: Remove legacy iomux support

[Stefano Babic]

On 03/05/2013 14:42, Marek Vasut wrote:
> Dear Beno?t Th?baudeau,
> 
>> Dear Marek Vasut,
>>
>> On Friday, May 3, 2013 4:38:43 AM, Marek Vasut wrote:
>>> Dear Beno?t Th?baudeau,
>>>
>>>> Legacy iomux support is no longer needed now that all boards have been
>>>> converted to iomux-v3.
>>>>
>>>> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
>>>
>>> Yes, good move
>>>
>>> Reviewed-by: Marek Vasut <marex@denx.de>
>>
>> How do you plan to handle the conversion to iomux-v3 of the not-yet-applied
>> m53evk:
>>  - You rebase your series on mine?
>>  - I rebase my series on yours?
> 
> Did you not send this stuff after m53evk? So let's let Stefano merge it all in 
> sequence (poor Stefano though, patches seem to be piling up).

Well, I confess that I let patches fill my "virtual" desk, but I will
try to make order ;-)

And I enjoy that we have now a larger as in the past iMX community that
bring support and fixes to this family of processors ;-)

Regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================