From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kumar Gala Date: Wed, 19 Jan 2011 21:06:56 -0600 Subject: [U-Boot] [Patch v3 5/7] mpc85xx: Enable unique mode registers and dynamic ODT for DDR3 In-Reply-To: <1294696982-20556-6-git-send-email-yorksun@freescale.com> References: <1294696982-20556-1-git-send-email-yorksun@freescale.com> <1294696982-20556-6-git-send-email-yorksun@freescale.com> Message-ID: <8306002A-5B97-4554-8EC5-555F11CDDE5A@kernel.crashing.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Jan 10, 2011, at 4:03 PM, York Sun wrote: > Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version > (major, minor, errata) to determine if unique mode registers are available. > If true, always use unique mode registers. Dynamic ODT is enabled if needed. > The table is documented in doc/README.fsl-ddr. This function may also need > to be extend for future other platforms if such a feature exists. > > Enable address parity and RCW by default for RDIMMs. > > Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for > quad-rank RDIMMs. > > Use a formula to calculate rodt_on for timing_cfg_5. > > Signed-off-by: York Sun > --- > arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 6 + > arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 250 ++++++++++++++++++++----- > arch/powerpc/cpu/mpc8xxx/ddr/options.c | 308 +++++++++++++++++++++++++++++- > arch/powerpc/include/asm/fsl_ddr_sdram.h | 18 ++ > doc/README.fsl-ddr | 67 +++++++- > 5 files changed, 595 insertions(+), 54 deletions(-) applied to 85xx - k