From: Peter.Chubb at data61.csiro.au <Peter.Chubb@data61.csiro.au>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] tegra: mmc: Set the bus width correctly
Date: Thu, 8 Jun 2017 04:03:29 +0000 [thread overview]
Message-ID: <84mv9junvy.wl-Peter.Chubb@data61.csiro.au> (raw)
In-Reply-To: <20170608031148.21101-1-sjg@chromium.org>
>>>>> "Simon" == Simon Glass <sjg@chromium.org> writes:
Simon> The driver currently does not reset bit 5 of the hostctl
Simon> register even if the MMC stack requests it. Then means that
Simon> once a bus width of 8 is selected it is not possible to change
Simon> it back to 1. This breaks 'mmc rescan' which needs to start off
Simon> with a bus width of 1.
Simon> The problem was surfaced by enabling CONFIG_DM_MMC_OPS on
Simon> tegra. Without this option the MMC stack fully reinits the
Simon> driver on a 'mmc rescan'. But with this option driver model
Simon> does not re-probe a driver once it has been probed once.
Simon> Fix the driver to honour the request.
Simon> Signed-off-by: Simon Glass <sjg@chromium.org> ---
Tested-by: Peter Chubb <peter.chubb@data61.csiro.au>
Simon> drivers/mmc/tegra_mmc.c | 2 +- 1 file changed, 1 insertion(+),
Simon> 1 deletion(-)
Simon> diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
Simon> index 338e42b528..7d945a172e 100644 ---
Simon> a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@
Simon> -438,7 +438,7 @@ static int tegra_mmc_set_ios(struct udevice
Simon> *dev) else if (mmc->bus_width == 4) ctrl |= (1 << 1); else -
Simon> ctrl &= ~(1 << 1); + ctrl &= ~(1 << 1 | 1 << 5);
Simon> writeb(ctrl, &priv->reg->hostctl); debug("mmc_set_ios:
Simon> hostctl = %08X\n", ctrl); -- 2.13.0.506.g27d5fe0cd-goog
Simon> --
Dr Peter Chubb Tel: +61 2 9490 5852 http://ts.data61.csiro.au/
Trustworthy Systems Group Data61 (formerly NICTA)
next prev parent reply other threads:[~2017-06-08 4:03 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-08 3:11 [U-Boot] [PATCH] tegra: mmc: Set the bus width correctly Simon Glass
2017-06-08 4:03 ` Peter.Chubb at data61.csiro.au [this message]
2017-06-14 11:32 ` Simon Glass
2017-06-14 15:33 ` Tom Warren
2017-06-20 16:40 ` Thierry Reding
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