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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9f0107sm7790915f8f.99.2025.03.23.05.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 05:26:34 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Tom Rini , Andre Przywara Cc: Simon Glass , Mikhail Kalashnikov , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: Re: [PATCH 28/34] sunxi: armv8: FEL: save and restore SP_IRQ Date: Sun, 23 Mar 2025 13:26:34 +0100 Message-ID: <8544399.NyiUUSuA9g@jernej-laptop> In-Reply-To: <20250323113544.7933-29-andre.przywara@arm.com> References: <20250323113544.7933-1-andre.przywara@arm.com> <20250323113544.7933-29-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Dne nedelja, 23. marec 2025 ob 12:35:38 Srednjeevropski standardni =C4=8Das= je Andre Przywara napisal(a): > Thanks for Jernej's JTAG debugging effort, it turns out that the BROM > expects SP_IRQ to be saved and restored, when we want to enter back into > FEL after the SPL's AArch64 stint. > Save and restore SP_IRQ as part of the FEL state handling. The banked > MRS/MSR access to SP_IRQ, without actually being in IRQ mode, was > introduced with the ARMv7 virtualisation extensions. The Arm Cortex-A8 > cores used in the A10/A13s or older F1C100s SoCs would not support that, > but this code here is purely in the ARMv8/AArch64 code path, so it's > safe to use unconditionally. >=20 > Reported-by: Jernej Skrabec > Signed-off-by: Andre Przywara I have sneaky suspicion that this is already the issue on H616, but I haven't yet confirmed. =46WIW: Reviewed-by: Jernej Skrabec Best regards, Jernej