From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5158C83F01 for ; Sat, 26 Aug 2023 10:22:12 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4466186B3C; Sat, 26 Aug 2023 12:22:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="eFOZ6MeE"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D061886B3D; Sat, 26 Aug 2023 12:22:09 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id F172586ACC for ; Sat, 26 Aug 2023 12:22:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=maz@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E7A6A60B81; Sat, 26 Aug 2023 10:22:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BC0DC433C7; Sat, 26 Aug 2023 10:22:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1693045324; bh=mRbyyWuflEMpT2d41V/k1Oq4F9yHbIMTBtn8bN5q6D4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=eFOZ6MeE97mnlUR9TFL8aHYBydWUcBZ21IV+yPBfR2eBY824JUBSv8iMMMKWJuU// PYR8NBJjyFGjD3dxACu+kEfI/nvlFbKx34WM0IqsPJzYy0deerzIjiHGr79xztNNXK F0wC4J1Ur2RDPUM2nly+2JpCbbUPFRZgFB/A9Idp+2Grlpk+meo+UwSlxtnrIojTCf PlU6za3o7K9pFKnXHcXo2MN2aMax3xY21zB6w/r7WNKrYr8Q7zIUxH1FHPHBmdNUdZ QlEZeOh14bmpOeMBK4RzezehfdMXCRMyo82hGn3tVB2o8rpd8cxzDT5siGzyNZK34w tAn5mQ4Z69r7A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qZqQb-008Gc9-S6; Sat, 26 Aug 2023 11:22:01 +0100 Date: Sat, 26 Aug 2023 11:22:01 +0100 Message-ID: <86cyzaf6ie.wl-maz@kernel.org> From: Marc Zyngier To: Sam Edwards Cc: wens@csie.org, Andre Przywara , u-boot@lists.denx.de, Jagan Teki Subject: Re: [PATCH] sunxi: psci: remove redundant initialization from psci_arch_init In-Reply-To: <69909b61-f57e-fc91-43a5-0f4bd23609c9@gmail.com> References: <20230531201520.15479-1-CFSworks@gmail.com> <20230814213854.408962d5@slackpad.lan> <69909b61-f57e-fc91-43a5-0f4bd23609c9@gmail.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: cfsworks@gmail.com, wens@csie.org, andre.przywara@arm.com, u-boot@lists.denx.de, jagan@amarulasolutions.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Fri, 25 Aug 2023 19:05:32 +0100, Sam Edwards wrote: > > On 8/25/23 00:20, Chen-Yu Tsai wrote: > > Hi Chen-Yu, > > > IIRC the GIC manual says that the secure bit is set or cleared to select > > which bank of registers is accessed. > > Which secure bit are we talking about here? Do we mean the > *configured* secure bit (SCR.NS, what the code is attempting to clear) > or the *effective* secure bit (AWPROT[1], et al)? The distinction is > important in monitor mode (where this function runs) since there (and > only there) the CPU core ignores the configured setting and runs in > the secure world unconditionally. > > I'm guessing it's most likely the latter since the former isn't > exposed outside of the CPU core, unless the GIC has some special > signal going to it... The GIC definitely has the NS bit routed to it. Otherwise, the secure configuration would just be an utter joke. Just try it. > > > And I suppose it is here to be more robust. > > ...but if it is the former (i.e. SCR.NS is significant in this > function) the code should be retained, but moved *before* the GIC > register accesses, and the old value of SCR.NS should be restored > *after*. > > Either way: I don't think this line should be kept in its current > form, because it's written in a way that strongly suggests that we > want to run in secure mode after exiting monitor mode, which is flatly > not the case. Well, history is unfortunately against you on that front. Running on the secure side definitely was a requirement when this code was initially written, as the AW BSP *required* to run on the secure side. If that requirement is no more, great. But I don't think you can decide that unilaterally. M. -- Without deviation from the norm, progress is not possible.