[U-Boot] Fwd: [PATCH v3 00/13] ARMv7: add PSCI support to u-boot

[Marc Zyngier <marc.zyngier@arm.com>]

On Thu, Apr 17 2014 at 09:01:07 PM, Jon Loeliger <loeliger@gmail.com> wrote:
> [ Drat.  I meant to send this to the U-Boot list, not just Albert.  --jdl]
>
> ---------- Forwarded message ----------
> From: Jon Loeliger <loeliger@gmail.com>
> Date: Thu, Apr 17, 2014 at 11:36 AM
> Subject: Re: [U-Boot] [PATCH v3 00/13] ARMv7: add PSCI support to u-boot
> To: Albert ARIBAUD <albert.u.boot@aribaud.net>
>
>
> On Thu, Apr 17, 2014 at 3:34 AM, Albert ARIBAUD
> <albert.u.boot@aribaud.net> wrote:
>> Hi Marc,
>>
>
>> So yes, I am willing to review them -- and I suspect others are, as
>> well. Nobody commented the V3 series on the U-Boot list -- save for
>> Jon's comment about the series needing a rebase -- which could mean no
>> one here is unhappy with them...
>
> So, not *unhappy* with them, but definitely some review is needed.

That's an understatement. I wouldn't expect such infrastructure patches
to go in without a good discussion about the approach I've taken here.

> Also, there are aspects of the implementation that will need to be
> generalized a bit.  For example, the sunxi code uses a magic register
> in its implementation that allows a core to come out of reset at a known
> (ie, given) non-0 address.  My A9 core has CPUs coming out of reset
> at a fixed address of 0.  That means my "secure text" must be at 0,
> and it must have a "secure vector" with a "secure reset" laid down at 0.
> Ultimately, this means that a small modification (adding a secure vector
> text section) to the LDS file will be needed to ensure that it is placed at 0
> within the secure text section itself.

Yup, there is certainly some flexibility to be added to accomodate for
all the various cases, depending on how secondary CPUs are released.

Patches are most welcome! ;-)

> No, I don't have all this working quite yet. :-)

Looking forward to seeing the result!

	M.
-- 
Jazz is not dead. It just smells funny.