[U-Boot] [PATCH v2] DW SPI: Allow to overload the management of the external CS

[U-Boot] [PATCH v2] DW SPI: Allow to overload the management of the external CS

[Gregory CLEMENT]

On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..

By declaring the external_cs_manage function as weak, it is possible to
manage the CS at platform level and then using the appropriate registers.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
Changelog:
v1 -> v2
- Fix ocelot name

 drivers/spi/designware_spi.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index d8b73ea326..1f47ea24c8 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -334,7 +334,13 @@ static int poll_transfer(struct dw_spi_priv *priv)
 	return 0;
 }
 
-static void external_cs_manage(struct udevice *dev, bool on)
+/*
+ * We define external_cs_manage function as 'weak' as some targets
+ * (like MSCC Ocelot) don't control the external CS pin using a GPIO
+ * controller. These SoCs use specific registers to control by
+ * software the SPI pins (and especially the CS).
+ */
+__weak void external_cs_manage(struct udevice *dev, bool on)
 {
 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
 	struct dw_spi_priv *priv = dev_get_priv(dev->parent);
-- 
2.19.1

[U-Boot] [PATCH v2] DW SPI: Allow to overload the management of the external CS

[Gregory CLEMENT]

Hi Jagan,
 
 On mar., oct. 09 2018, Gregory CLEMENT <gregory.clement@bootlin.com> wrote:

> On some platforms, as the Ocelot ones, when wanting to control the CS
> through software, it is not possible to do it through the GPIO
> controller. Indeed, this signal is managed through a dedicated range of
> registers inside the SoC..
>
> By declaring the external_cs_manage function as weak, it is possible to
> manage the CS at platform level and then using the appropriate registers.
>

I sent this v2 nearly 2 months ago and didn't have any objection about
it. So, Could you merge this patch please?

Thanks!

> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Changelog:
> v1 -> v2
> - Fix ocelot name
>
>  drivers/spi/designware_spi.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
> index d8b73ea326..1f47ea24c8 100644
> --- a/drivers/spi/designware_spi.c
> +++ b/drivers/spi/designware_spi.c
> @@ -334,7 +334,13 @@ static int poll_transfer(struct dw_spi_priv *priv)
>  	return 0;
>  }
>  
> -static void external_cs_manage(struct udevice *dev, bool on)
> +/*
> + * We define external_cs_manage function as 'weak' as some targets
> + * (like MSCC Ocelot) don't control the external CS pin using a GPIO
> + * controller. These SoCs use specific registers to control by
> + * software the SPI pins (and especially the CS).
> + */
> +__weak void external_cs_manage(struct udevice *dev, bool on)
>  {
>  #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
>  	struct dw_spi_priv *priv = dev_get_priv(dev->parent);
> -- 
> 2.19.1
>

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com