From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 3/4] MIPS: mscc: ocelot: add switch reset support
Date: Wed, 16 Jan 2019 15:37:09 +0100 [thread overview]
Message-ID: <87d0owpt2i.fsf@FE-laptop> (raw)
In-Reply-To: <9080daa6-5294-6c58-2a5f-f66f893e4a04@gmail.com> (Daniel Schwierzeck's message of "Wed, 16 Jan 2019 14:59:48 +0100")
Hi Daniel,
On mer., janv. 16 2019, Daniel Schwierzeck <daniel.schwierzeck@gmail.com> wrote:
> Am 16.01.19 um 14:07 schrieb Gregory CLEMENT:
>> On some ocelots platform a workaround is needed in order to be able to
>> reset the switch without resetting the DDR.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
>> ---
>> board/mscc/ocelot/ocelot.c | 26 ++++++++++++++++++++++++++
>> 1 file changed, 26 insertions(+)
>>
>> diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
>> index 0f7a532158..77ebe8ae26 100644
>> --- a/board/mscc/ocelot/ocelot.c
>> +++ b/board/mscc/ocelot/ocelot.c
>> @@ -10,6 +10,7 @@
>> #include <environment.h>
>> #include <spi.h>
>> #include <led.h>
>> +#include <wait_bit.h>
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -18,6 +19,31 @@ enum {
>> BOARD_TYPE_PCB123,
>> };
>>
>> +void mscc_switch_reset(bool enter)
>> +{
>> + u32 reg, count = 0;
>> +
>> + /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
>> + mscc_gpio_set_alternate(19, 2);
>> +
>> + debug("applying SwC reset\n");
>> +
>> + writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
>> + writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
>> +
>> + if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
>> + PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
>> + pr_err("Tiemout while waiting for switch reset\n");
>> +
>> + /*
>> + * Reset GPIO19 mode back as regular GPIO, output, high (DDR
>> + * not reset) (Order is important)
>> + */
>> + setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
>> + writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
>> + mscc_gpio_set_alternate(19, 0);
>
> have you thought about or maybe planned a reset controller driver?
Actually, here it is not a reset driver, it is just the workaround part
of the stop() function in the network driver. It is not about resetting
the whole platform, for this feature a driver already has been submited.
Gregory
>
>> +}
>> +
>> void board_debug_uart_init(void)
>> {
>> /* too early for the pinctrl driver, so configure the UART pins here */
>>
>
> --
> - Daniel
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
next prev parent reply other threads:[~2019-01-16 14:37 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-16 13:07 [U-Boot] [PATCH v2 0/4] Add network support for Ocelots SoCs Gregory CLEMENT
2019-01-16 13:07 ` [U-Boot] [PATCH v2 1/4] MIPS: mscc: ocelot: Add ethernet nodes for Ocelot Gregory CLEMENT
2019-01-16 13:07 ` [U-Boot] [PATCH v2 2/4] net: add MSCC Ocelot switch support Gregory CLEMENT
2019-01-16 13:56 ` Daniel Schwierzeck
2019-01-16 14:21 ` Gregory CLEMENT
2019-01-16 14:43 ` Daniel Schwierzeck
2019-01-16 13:07 ` [U-Boot] [PATCH v2 3/4] MIPS: mscc: ocelot: add switch reset support Gregory CLEMENT
2019-01-16 13:59 ` Daniel Schwierzeck
2019-01-16 14:37 ` Gregory CLEMENT [this message]
2019-01-16 15:34 ` Daniel Schwierzeck
2019-01-16 13:07 ` [U-Boot] [PATCH v2 4/4] configs: mscc_ocelot: add network support Gregory CLEMENT
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