From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gregory CLEMENT Date: Wed, 16 Jan 2019 15:37:09 +0100 Subject: [U-Boot] [PATCH v2 3/4] MIPS: mscc: ocelot: add switch reset support In-Reply-To: <9080daa6-5294-6c58-2a5f-f66f893e4a04@gmail.com> (Daniel Schwierzeck's message of "Wed, 16 Jan 2019 14:59:48 +0100") References: <20190116130743.20539-1-gregory.clement@bootlin.com> <20190116130743.20539-4-gregory.clement@bootlin.com> <9080daa6-5294-6c58-2a5f-f66f893e4a04@gmail.com> Message-ID: <87d0owpt2i.fsf@FE-laptop> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Daniel, On mer., janv. 16 2019, Daniel Schwierzeck wrote: > Am 16.01.19 um 14:07 schrieb Gregory CLEMENT: >> On some ocelots platform a workaround is needed in order to be able to >> reset the switch without resetting the DDR. >> >> Signed-off-by: Gregory CLEMENT >> --- >> board/mscc/ocelot/ocelot.c | 26 ++++++++++++++++++++++++++ >> 1 file changed, 26 insertions(+) >> >> diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c >> index 0f7a532158..77ebe8ae26 100644 >> --- a/board/mscc/ocelot/ocelot.c >> +++ b/board/mscc/ocelot/ocelot.c >> @@ -10,6 +10,7 @@ >> #include >> #include >> #include >> +#include >> >> DECLARE_GLOBAL_DATA_PTR; >> >> @@ -18,6 +19,31 @@ enum { >> BOARD_TYPE_PCB123, >> }; >> >> +void mscc_switch_reset(bool enter) >> +{ >> + u32 reg, count = 0; >> + >> + /* Nasty workaround to avoid GPIO19 (DDR!) being reset */ >> + mscc_gpio_set_alternate(19, 2); >> + >> + debug("applying SwC reset\n"); >> + >> + writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); >> + writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); >> + >> + if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST, >> + PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false)) >> + pr_err("Tiemout while waiting for switch reset\n"); >> + >> + /* >> + * Reset GPIO19 mode back as regular GPIO, output, high (DDR >> + * not reset) (Order is important) >> + */ >> + setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); >> + writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); >> + mscc_gpio_set_alternate(19, 0); > > have you thought about or maybe planned a reset controller driver? Actually, here it is not a reset driver, it is just the workaround part of the stop() function in the network driver. It is not about resetting the whole platform, for this feature a driver already has been submited. Gregory > >> +} >> + >> void board_debug_uart_init(void) >> { >> /* too early for the pinctrl driver, so configure the UART pins here */ >> > > -- > - Daniel -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com