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From: Baruch Siach <baruch@tkos.co.il>
To: u-boot@lists.denx.de
Subject: [U-Boot] Marvell DDR training custom ODT configuration
Date: Thu, 28 Feb 2019 11:45:16 +0200	[thread overview]
Message-ID: <87imx45jrn.fsf@tarshish> (raw)

Hi Chris,

Currently the value of g_odt_config is hard coded in Marvell SoC
platform headers. Some SolidRun A388 SOMs need a custom value. These
SOMs use both DDR chip-selects, but ODT0 alone is connected to both
chips. For that to work we need to set g_odt_config to 0x30000, that is,
ODT0 is configured for both CS0 and CS1.

How can we do that in a clean way so as to not interfere too much with
your periodic code syncs from Marvell's DDR training source tree?

Thanks,
baruch

--
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -

             reply	other threads:[~2019-02-28  9:45 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-28  9:45 Baruch Siach [this message]
2019-02-28 18:56 ` [U-Boot] Marvell DDR training custom ODT configuration Chris Packham
2019-02-28 21:41 ` Chris Packham
2019-03-03  8:11   ` Baruch Siach

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