From mboxrd@z Thu Jan 1 00:00:00 1970 From: Felipe Balbi Date: Mon, 16 Oct 2017 16:55:03 +0300 Subject: [U-Boot] [PATCH v2] usb: dwc3: Allocate and flush dwc->ep0_trb in a cache aligned manner In-Reply-To: <72a54562-4437-a008-37bc-f11b2440aecc@denx.de> References: <1508131315-23549-1-git-send-email-faiz_abbas@ti.com> <72a54562-4437-a008-37bc-f11b2440aecc@denx.de> Message-ID: <87inffkxjc.fsf@linux.intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, Marek Vasut writes: > On 10/16/2017 07:21 AM, Faiz Abbas wrote: >> A flush of the cache is required before any outbound DMA access can >> take place. The minimum size that can be flushed from the cache is >> one cache line size. Therefore, any buffer allocated for DMA should >> be in multiples of cache line size. >> >> Thus, allocate memory for ep0_trb in multiples of cache line size. >> >> Also, when local variable trb is assigned to dwc->ep0_trb[1] and used >> to flush cache, it leads to cache misaligned messages as only the base >> address dwc->ep0_trb is cache aligned. >> >> Therefore, flush cache using ep0_trb_addr which is always cache aligned. >> >> Signed-off-by: Faiz Abbas > > SGTM, Felipe, can you review this please ? is cache maintenance done correctly in u-boot? Isn't the whole idea of a coherent memory area that is is non-cacheable, non-bufferable memory? Also, why isn't the API itself guaranteeing alignment requirements? -- balbi -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 832 bytes Desc: not available URL: