[PATCH v2 0/8] Add support for Qualcomm SA8155-ADP board

[PATCH v2 0/8] Add support for Qualcomm SA8155-ADP board

[Volodymyr Babchuk]

This patch series adds support for Qualcomm SA8155-ADP development
board. Main motivation for this series is to allow running
virtualization software on this board and U-Boot is a good way to
break Qualcomm's boot chain at EL2 with more convenient ways for
uploading and running the code. With this patches applied it is
possible to upload and run Xen on this board. KVM probably should work
too.

I added myself as a maintainer for this board, but my abilities to
maintain it are quite limited as I have no access to Qualcomm
documentation. I used mostly Linux drivers as the source for
device-specific information, like register addresses and offsets.
If anyone wants to maintain this, I will gladly agree.

This is the second version of the series. It is now rebased onto
qcom-next branch.


Changes in v2:
 - New patch in v2
 - Clear loopback bit explicitly
 - Reworked qcom_cc_bind() function
 - Added timeout to qcom_power_set()
 - Minor fixes in register names and formatting
 - Renamed GPLL7_MAIN to just GPLL7 (while I like idea to use Linux
   naming convention, such rework needs to be done in a separate
   commit)
 - Removed unnecessary include
 - Fixed GDSCR register values for couple of devices
 - Enable GPLL7 only when RGMII clock is enabled
 - Rebased onto qcom-next branch
 - Removed unnecessary files thanks to generic qualcomm board support
 - Enabled CONFIG_REMAKE_ELF (this removes one extra step in the
   readme)

Volodymyr Babchuk (8):
  qcom: board: validate fdt before trying to use it
  clk: qcom: clear div mask before assigning a new divider
  net: dw_eth_qos: add support for Qualcomm SM8150 SoC
  clk: qcom: add support for power domains uclass
  clk: qcom: add driver for SM8150 SoC
  pinctrl: qcom: pass pin number to get_function_mux callback
  pinctrl: qcom: add driver for SM8150 SoC
  board: add support for Qualcomm SA8155P-ADP board

 arch/arm/dts/sa8155p-adp-u-boot.dtsi   |  30 ++
 arch/arm/mach-snapdragon/board.c       |   5 +-
 board/qualcomm/sa8155p-adp/MAINTAINERS |   5 +
 configs/sa8155p_adp_defconfig          |  35 ++
 doc/board/qualcomm/index.rst           |   1 +
 doc/board/qualcomm/sa8155p-adp.rst     |  87 ++++
 drivers/clk/qcom/Kconfig               |   8 +
 drivers/clk/qcom/Makefile              |   1 +
 drivers/clk/qcom/clock-qcom.c          | 131 +++++-
 drivers/clk/qcom/clock-qcom.h          |   7 +
 drivers/clk/qcom/clock-sm8150.c        | 237 ++++++++++
 drivers/net/dwc_eth_qos.c              |   4 +
 drivers/net/dwc_eth_qos.h              |   2 +
 drivers/net/dwc_eth_qos_qcom.c         |  46 +-
 drivers/pinctrl/qcom/Kconfig           |   7 +
 drivers/pinctrl/qcom/Makefile          |   1 +
 drivers/pinctrl/qcom/pinctrl-apq8016.c |   3 +-
 drivers/pinctrl/qcom/pinctrl-apq8096.c |   3 +-
 drivers/pinctrl/qcom/pinctrl-ipq4019.c |   3 +-
 drivers/pinctrl/qcom/pinctrl-qcom.c    |   4 +-
 drivers/pinctrl/qcom/pinctrl-qcom.h    |   3 +-
 drivers/pinctrl/qcom/pinctrl-qcs404.c  |   3 +-
 drivers/pinctrl/qcom/pinctrl-sdm845.c  |   3 +-
 drivers/pinctrl/qcom/pinctrl-sm8150.c  | 589 +++++++++++++++++++++++++
 24 files changed, 1186 insertions(+), 32 deletions(-)
 create mode 100644 arch/arm/dts/sa8155p-adp-u-boot.dtsi
 create mode 100644 board/qualcomm/sa8155p-adp/MAINTAINERS
 create mode 100644 configs/sa8155p_adp_defconfig
 create mode 100644 doc/board/qualcomm/sa8155p-adp.rst
 create mode 100644 drivers/clk/qcom/clock-sm8150.c
 create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c

-- 
2.43.0

[PATCH v2 3/8] net: dw_eth_qos: add support for Qualcomm SM8150 SoC

[Volodymyr Babchuk]

Add support for Qualcomm SM8150 SoC to the EQOS driver. SM8150 has two
main differences from already supported QCS404: it has another RGMII
configuration registers set and it does require RGMII loopback to
be disabled.

To support different variants of QCOM SoC we had to add two new fields
to the eqos_priv struct: eqos_qcom_rgmii_regs and
qcom_enable_loopback.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

---

Changes in v2:
 - Clear loopback bit explicitly

 drivers/net/dwc_eth_qos.c      |  4 +++
 drivers/net/dwc_eth_qos.h      |  2 ++
 drivers/net/dwc_eth_qos_qcom.c | 46 +++++++++++++++++++++++++++-------
 3 files changed, 43 insertions(+), 9 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9b3bce1dc8..882b854697 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1700,6 +1700,10 @@ static const struct udevice_id eqos_ids[] = {
 		.compatible = "qcom,qcs404-ethqos",
 		.data = (ulong)&eqos_qcom_config
 	},
+	{
+		.compatible = "qcom,sm8150-ethqos",
+		.data = (ulong)&eqos_qcom_config
+	},
 #endif
 #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
 	{
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index e3222e1e17..216e1afe53 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -255,6 +255,7 @@ struct eqos_priv {
 	struct eqos_dma_regs *dma_regs;
 	struct eqos_tegra186_regs *tegra186_regs;
 	void *eqos_qcom_rgmii_regs;
+	struct dwmac_rgmii_regs *eqos_qcom_por;
 	struct reset_ctl reset_ctl;
 	struct gpio_desc phy_reset_gpio;
 	struct clk clk_master_bus;
@@ -277,6 +278,7 @@ struct eqos_priv {
 	bool started;
 	bool reg_access_ok;
 	bool clk_ck_enabled;
+	bool qcom_enable_loopback;
 	unsigned int tx_fifo_sz, rx_fifo_sz;
 	u32 reset_delays[3];
 };
diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c
index 8178138fc6..ee8420c71d 100644
--- a/drivers/net/dwc_eth_qos_qcom.c
+++ b/drivers/net/dwc_eth_qos_qcom.c
@@ -95,6 +95,15 @@ static struct dwmac_rgmii_regs emac_v2_3_0_por = {
 	.io_macro_config2 = 0x00002060
 };
 
+static struct dwmac_rgmii_regs emac_v2_1_0_por = {
+	.io_macro_config = 0x40C01343,
+	.sdcc_hc_dll_config = 0x2004642C,
+	.sdcc_hc_ddr_config = 0x00000000,
+	.sdcc_hc_dll_config2 = 0x00200000,
+	.sdcc_usr_ctl = 0x00010800,
+	.io_macro_config2 = 0x00002060
+};
+
 static void ethqos_set_func_clk_en(struct dwmac_rgmii_regs *regs)
 {
 	setbits_le32(&regs->io_macro_config, RGMII_CONFIG_FUNC_CLK_EN);
@@ -172,6 +181,10 @@ static int ethqos_rgmii_macro_init(struct udevice *dev,
 				   struct dwmac_rgmii_regs *regs,
 				   unsigned long speed)
 {
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	uint32_t loopback =
+		eqos->qcom_enable_loopback ? RGMII_CONFIG_LOOPBACK_EN : 0;
+
 	/* Disable loopback mode */
 	clrbits_le32(&regs->io_macro_config2,
 		     RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN);
@@ -202,7 +215,8 @@ static int ethqos_rgmii_macro_init(struct udevice *dev,
 				SDCC_DDR_CONFIG_PRG_RCLK_DLY, 57);
 		setbits_le32(&regs->sdcc_hc_ddr_config, SDCC_DDR_CONFIG_PRG_DLY_EN);
 
-		setbits_le32(&regs->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
+		clrsetbits_le32(&regs->io_macro_config,
+				RGMII_CONFIG_LOOPBACK_EN, loopback);
 		break;
 
 	case SPEED_100:
@@ -233,7 +247,8 @@ static int ethqos_rgmii_macro_init(struct udevice *dev,
 		setbits_le32(&regs->sdcc_hc_ddr_config,
 			     SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN);
 
-		setbits_le32(&regs->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
+		clrsetbits_le32(&regs->io_macro_config,
+				RGMII_CONFIG_LOOPBACK_EN, loopback);
 		break;
 
 	case SPEED_10:
@@ -265,7 +280,8 @@ static int ethqos_rgmii_macro_init(struct udevice *dev,
 		setbits_le32(&regs->sdcc_hc_ddr_config,
 			     SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN);
 
-		setbits_le32(&regs->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
+		clrsetbits_le32(&regs->io_macro_config,
+				RGMII_CONFIG_LOOPBACK_EN, loopback);
 		break;
 
 	default:
@@ -281,14 +297,15 @@ static int ethqos_configure(struct udevice *dev,
 			    unsigned long speed)
 {
 	unsigned int retry = 1000;
+	struct eqos_priv *eqos = dev_get_priv(dev);
 
 	/* Reset to POR values and enable clk */
-	writel(emac_v2_3_0_por.io_macro_config, &regs->io_macro_config);
-	writel(emac_v2_3_0_por.sdcc_hc_dll_config, &regs->sdcc_hc_dll_config);
-	writel(emac_v2_3_0_por.sdcc_hc_ddr_config, &regs->sdcc_hc_ddr_config);
-	writel(emac_v2_3_0_por.sdcc_hc_dll_config2, &regs->sdcc_hc_dll_config2);
-	writel(emac_v2_3_0_por.sdcc_usr_ctl, &regs->sdcc_usr_ctl);
-	writel(emac_v2_3_0_por.io_macro_config2, &regs->io_macro_config2);
+	writel(eqos->eqos_qcom_por->io_macro_config, &regs->io_macro_config);
+	writel(eqos->eqos_qcom_por->sdcc_hc_dll_config, &regs->sdcc_hc_dll_config);
+	writel(eqos->eqos_qcom_por->sdcc_hc_ddr_config, &regs->sdcc_hc_ddr_config);
+	writel(eqos->eqos_qcom_por->sdcc_hc_dll_config2, &regs->sdcc_hc_dll_config2);
+	writel(eqos->eqos_qcom_por->sdcc_usr_ctl, &regs->sdcc_usr_ctl);
+	writel(eqos->eqos_qcom_por->io_macro_config2, &regs->io_macro_config2);
 
 	ethqos_set_func_clk_en(regs);
 
@@ -565,6 +582,17 @@ static int eqos_probe_resources_qcom(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	if (device_is_compatible(dev, "qcom,qcs404-ethqos")) {
+		eqos->eqos_qcom_por = &emac_v2_3_0_por;
+		eqos->qcom_enable_loopback = true;
+	} else if (device_is_compatible(dev, "qcom,sm8150-ethqos")) {
+		eqos->eqos_qcom_por = &emac_v2_1_0_por;
+		eqos->qcom_enable_loopback = false;
+	} else {
+		pr_err("Unknown QCOM ethernet device\n");
+		return -EINVAL;
+	}
+
 	debug("%s: OK\n", __func__);
 	return 0;
 }
-- 
2.43.0

Re: [PATCH v2 3/8] net: dw_eth_qos: add support for Qualcomm SM8150 SoC

[Sumit Garg]

On Wed, 6 Mar 2024 at 06:23, Volodymyr Babchuk
<Volodymyr_Babchuk@epam.com> wrote:
>
> Add support for Qualcomm SM8150 SoC to the EQOS driver. SM8150 has two
> main differences from already supported QCS404: it has another RGMII
> configuration registers set and it does require RGMII loopback to
> be disabled.
>
> To support different variants of QCOM SoC we had to add two new fields
> to the eqos_priv struct: eqos_qcom_rgmii_regs and
> qcom_enable_loopback.
>
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>
> ---
>
> Changes in v2:
>  - Clear loopback bit explicitly
>
>  drivers/net/dwc_eth_qos.c      |  4 +++
>  drivers/net/dwc_eth_qos.h      |  2 ++
>  drivers/net/dwc_eth_qos_qcom.c | 46 +++++++++++++++++++++++++++-------
>  3 files changed, 43 insertions(+), 9 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index 9b3bce1dc8..882b854697 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -1700,6 +1700,10 @@ static const struct udevice_id eqos_ids[] = {
>                 .compatible = "qcom,qcs404-ethqos",
>                 .data = (ulong)&eqos_qcom_config
>         },
> +       {
> +               .compatible = "qcom,sm8150-ethqos",
> +               .data = (ulong)&eqos_qcom_config
> +       },
>  #endif
>  #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE)
>         {
> diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
> index e3222e1e17..216e1afe53 100644
> --- a/drivers/net/dwc_eth_qos.h
> +++ b/drivers/net/dwc_eth_qos.h
> @@ -255,6 +255,7 @@ struct eqos_priv {
>         struct eqos_dma_regs *dma_regs;
>         struct eqos_tegra186_regs *tegra186_regs;
>         void *eqos_qcom_rgmii_regs;
> +       struct dwmac_rgmii_regs *eqos_qcom_por;
>         struct reset_ctl reset_ctl;
>         struct gpio_desc phy_reset_gpio;
>         struct clk clk_master_bus;
> @@ -277,6 +278,7 @@ struct eqos_priv {
>         bool started;
>         bool reg_access_ok;
>         bool clk_ck_enabled;
> +       bool qcom_enable_loopback;
>         unsigned int tx_fifo_sz, rx_fifo_sz;
>         u32 reset_delays[3];
>  };
> diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c
> index 8178138fc6..ee8420c71d 100644
> --- a/drivers/net/dwc_eth_qos_qcom.c
> +++ b/drivers/net/dwc_eth_qos_qcom.c
> @@ -95,6 +95,15 @@ static struct dwmac_rgmii_regs emac_v2_3_0_por = {
>         .io_macro_config2 = 0x00002060
>  };
>
> +static struct dwmac_rgmii_regs emac_v2_1_0_por = {
> +       .io_macro_config = 0x40C01343,
> +       .sdcc_hc_dll_config = 0x2004642C,
> +       .sdcc_hc_ddr_config = 0x00000000,
> +       .sdcc_hc_dll_config2 = 0x00200000,
> +       .sdcc_usr_ctl = 0x00010800,
> +       .io_macro_config2 = 0x00002060
> +};
> +
>  static void ethqos_set_func_clk_en(struct dwmac_rgmii_regs *regs)
>  {
>         setbits_le32(&regs->io_macro_config, RGMII_CONFIG_FUNC_CLK_EN);
> @@ -172,6 +181,10 @@ static int ethqos_rgmii_macro_init(struct udevice *dev,
>                                    struct dwmac_rgmii_regs *regs,
>                                    unsigned long speed)
>  {
> +       struct eqos_priv *eqos = dev_get_priv(dev);
> +       uint32_t loopback =
> +               eqos->qcom_enable_loopback ? RGMII_CONFIG_LOOPBACK_EN : 0;
> +
>         /* Disable loopback mode */
>         clrbits_le32(&regs->io_macro_config2,
>                      RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN);
> @@ -202,7 +215,8 @@ static int ethqos_rgmii_macro_init(struct udevice *dev,
>                                 SDCC_DDR_CONFIG_PRG_RCLK_DLY, 57);
>                 setbits_le32(&regs->sdcc_hc_ddr_config, SDCC_DDR_CONFIG_PRG_DLY_EN);
>
> -               setbits_le32(&regs->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
> +               clrsetbits_le32(&regs->io_macro_config,
> +                               RGMII_CONFIG_LOOPBACK_EN, loopback);
>                 break;
>
>         case SPEED_100:
> @@ -233,7 +247,8 @@ static int ethqos_rgmii_macro_init(struct udevice *dev,
>                 setbits_le32(&regs->sdcc_hc_ddr_config,
>                              SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN);
>
> -               setbits_le32(&regs->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
> +               clrsetbits_le32(&regs->io_macro_config,
> +                               RGMII_CONFIG_LOOPBACK_EN, loopback);
>                 break;
>
>         case SPEED_10:
> @@ -265,7 +280,8 @@ static int ethqos_rgmii_macro_init(struct udevice *dev,
>                 setbits_le32(&regs->sdcc_hc_ddr_config,
>                              SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN);
>
> -               setbits_le32(&regs->io_macro_config, RGMII_CONFIG_LOOPBACK_EN);
> +               clrsetbits_le32(&regs->io_macro_config,
> +                               RGMII_CONFIG_LOOPBACK_EN, loopback);
>                 break;
>
>         default:
> @@ -281,14 +297,15 @@ static int ethqos_configure(struct udevice *dev,
>                             unsigned long speed)
>  {
>         unsigned int retry = 1000;
> +       struct eqos_priv *eqos = dev_get_priv(dev);
>
>         /* Reset to POR values and enable clk */
> -       writel(emac_v2_3_0_por.io_macro_config, &regs->io_macro_config);
> -       writel(emac_v2_3_0_por.sdcc_hc_dll_config, &regs->sdcc_hc_dll_config);
> -       writel(emac_v2_3_0_por.sdcc_hc_ddr_config, &regs->sdcc_hc_ddr_config);
> -       writel(emac_v2_3_0_por.sdcc_hc_dll_config2, &regs->sdcc_hc_dll_config2);
> -       writel(emac_v2_3_0_por.sdcc_usr_ctl, &regs->sdcc_usr_ctl);
> -       writel(emac_v2_3_0_por.io_macro_config2, &regs->io_macro_config2);
> +       writel(eqos->eqos_qcom_por->io_macro_config, &regs->io_macro_config);
> +       writel(eqos->eqos_qcom_por->sdcc_hc_dll_config, &regs->sdcc_hc_dll_config);
> +       writel(eqos->eqos_qcom_por->sdcc_hc_ddr_config, &regs->sdcc_hc_ddr_config);
> +       writel(eqos->eqos_qcom_por->sdcc_hc_dll_config2, &regs->sdcc_hc_dll_config2);
> +       writel(eqos->eqos_qcom_por->sdcc_usr_ctl, &regs->sdcc_usr_ctl);
> +       writel(eqos->eqos_qcom_por->io_macro_config2, &regs->io_macro_config2);
>
>         ethqos_set_func_clk_en(regs);
>
> @@ -565,6 +582,17 @@ static int eqos_probe_resources_qcom(struct udevice *dev)
>                 return -EINVAL;
>         }
>
> +       if (device_is_compatible(dev, "qcom,qcs404-ethqos")) {
> +               eqos->eqos_qcom_por = &emac_v2_3_0_por;
> +               eqos->qcom_enable_loopback = true;
> +       } else if (device_is_compatible(dev, "qcom,sm8150-ethqos")) {
> +               eqos->eqos_qcom_por = &emac_v2_1_0_por;
> +               eqos->qcom_enable_loopback = false;
> +       } else {
> +               pr_err("Unknown QCOM ethernet device\n");
> +               return -EINVAL;
> +       }
> +
>         debug("%s: OK\n", __func__);
>         return 0;
>  }
> --
> 2.43.0

[PATCH v2 2/8] clk: qcom: clear div mask before assigning a new divider

[Volodymyr Babchuk]

The current behaviour does a bitwise OR of the previous and new
divider values, this is wrong as some bits maybe be set already. We
need to clear all the divider bits before applying new ones.

This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>

---

Changes in v2:
 - Reworded the commit message
 - Added Caleb's R-b tag

 drivers/clk/qcom/clock-qcom.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 7c683e5192..729d190c54 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -117,7 +117,8 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
 
 	/* setup src select and divider */
 	cfg  = readl(base + regs->cfg_rcgr);
-	cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK);
+	cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK |
+		 CFG_SRC_DIV_MASK);
 	cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */
 
 	if (div)
-- 
2.43.0

Re: [PATCH v2 2/8] clk: qcom: clear div mask before assigning a new divider

[Sumit Garg]

On Wed, 6 Mar 2024 at 06:23, Volodymyr Babchuk
<Volodymyr_Babchuk@epam.com> wrote:
>
> The current behaviour does a bitwise OR of the previous and new
> divider values, this is wrong as some bits maybe be set already. We
> need to clear all the divider bits before applying new ones.
>
> This fixes potential issue with 1Gbit ethernet on SA8155P-ADP boards.
>
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
>
> ---
>
> Changes in v2:
>  - Reworded the commit message
>  - Added Caleb's R-b tag
>
>  drivers/clk/qcom/clock-qcom.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index 7c683e5192..729d190c54 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -117,7 +117,8 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
>
>         /* setup src select and divider */
>         cfg  = readl(base + regs->cfg_rcgr);
> -       cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK);
> +       cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK |
> +                CFG_SRC_DIV_MASK);
>         cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */
>
>         if (div)
> --
> 2.43.0

[PATCH v2 1/8] qcom: board: validate fdt before trying to use it

[Volodymyr Babchuk]

There are cases when previous bootloader stage leaves some seemingly
valid value in r0, which in fact does not point to valid FDT
blob. This behavior was encountered when trying to boot U-Boot as
"hyp" loader on SA8155P-ADP.

To be sure that we really got the pointer to a device tree we need to
validate it with fdt_valid() function.

Note: This approach is not 100% fool-proof, as get_prev_bl_fdt_addr()
theoretically can return a pointer to a region that is not physically
mapped and we will get data abort exception when "fdt_valid" will try
to access it. But at this early boot stage we don't know where RAM is
anyways so there is little we can do.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

---

Changes in v2:
 - New patch in v2

 arch/arm/mach-snapdragon/board.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index f12f5791a1..10eec47ada 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -24,6 +24,7 @@
 #include <linux/sizes.h>
 #include <lmb.h>
 #include <malloc.h>
+#include <fdt_support.h>
 #include <usb.h>
 #include <sort.h>
 
@@ -93,7 +94,9 @@ void *board_fdt_blob_setup(int *err)
 	 * try and use the FDT built into U-Boot if there is one...
 	 * This avoids having a hard dependency on the previous stage bootloader
 	 */
-	if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K))) {
+
+	if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K) ||
+					       !fdt_valid((void *)&fdt))) {
 		debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt);
 		return (void *)gd->fdt_blob;
 	}
-- 
2.43.0

Re: [PATCH v2 1/8] qcom: board: validate fdt before trying to use it

[Sumit Garg]

On Wed, 6 Mar 2024 at 06:23, Volodymyr Babchuk
<Volodymyr_Babchuk@epam.com> wrote:
>
> There are cases when previous bootloader stage leaves some seemingly
> valid value in r0, which in fact does not point to valid FDT
> blob. This behavior was encountered when trying to boot U-Boot as
> "hyp" loader on SA8155P-ADP.
>
> To be sure that we really got the pointer to a device tree we need to
> validate it with fdt_valid() function.
>
> Note: This approach is not 100% fool-proof, as get_prev_bl_fdt_addr()
> theoretically can return a pointer to a region that is not physically
> mapped and we will get data abort exception when "fdt_valid" will try
> to access it. But at this early boot stage we don't know where RAM is
> anyways so there is little we can do.
>

I suppose this approach allows us to reuse the same U-Boot binary when
booted in EL2 more or when loaded by ABL. So I am fine with this
approach.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>
> ---
>
> Changes in v2:
>  - New patch in v2
>
>  arch/arm/mach-snapdragon/board.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> index f12f5791a1..10eec47ada 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -24,6 +24,7 @@
>  #include <linux/sizes.h>
>  #include <lmb.h>
>  #include <malloc.h>
> +#include <fdt_support.h>
>  #include <usb.h>
>  #include <sort.h>
>
> @@ -93,7 +94,9 @@ void *board_fdt_blob_setup(int *err)
>          * try and use the FDT built into U-Boot if there is one...
>          * This avoids having a hard dependency on the previous stage bootloader
>          */
> -       if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K))) {
> +
> +       if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K) ||
> +                                              !fdt_valid((void *)&fdt))) {
>                 debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt);
>                 return (void *)gd->fdt_blob;
>         }
> --
> 2.43.0

Re: [PATCH v2 1/8] qcom: board: validate fdt before trying to use it

[Caleb Connolly]

On 06/03/2024 00:52, Volodymyr Babchuk wrote:
> There are cases when previous bootloader stage leaves some seemingly
> valid value in r0, which in fact does not point to valid FDT
> blob. This behavior was encountered when trying to boot U-Boot as
> "hyp" loader on SA8155P-ADP.
> 
> To be sure that we really got the pointer to a device tree we need to
> validate it with fdt_valid() function.

Thanks for this!
> 
> Note: This approach is not 100% fool-proof, as get_prev_bl_fdt_addr()
> theoretically can return a pointer to a region that is not physically
> mapped and we will get data abort exception when "fdt_valid" will try
> to access it. But at this early boot stage we don't know where RAM is
> anyways so there is little we can do.

IME this hasn't been an issue in practise, but yes it is a risk.
> 
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> 
> ---
> 
> Changes in v2:
>  - New patch in v2
> 
>  arch/arm/mach-snapdragon/board.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> index f12f5791a1..10eec47ada 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -24,6 +24,7 @@
>  #include <linux/sizes.h>
>  #include <lmb.h>
>  #include <malloc.h>
> +#include <fdt_support.h>
>  #include <usb.h>
>  #include <sort.h>
>  
> @@ -93,7 +94,9 @@ void *board_fdt_blob_setup(int *err)
>  	 * try and use the FDT built into U-Boot if there is one...
>  	 * This avoids having a hard dependency on the previous stage bootloader
>  	 */
> -	if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K))) {
> +
> +	if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K) ||
> +					       !fdt_valid((void *)&fdt))) {
Please use fdt_check_header() here, fdt_valid() prints a bunch of stuff
using printf() which isn't really useful here.
>  		debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt);
>  		return (void *)gd->fdt_blob;
>  	}

-- 
// Caleb (they/them)

[PATCH v2 4/8] clk: qcom: add support for power domains uclass

[Volodymyr Babchuk]

Now sub-drivers for particular SoCs can register them as power domain
drivers. This is needed for upcoming SM8150 support, because it needs
to power up the Ethernet module.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

---

Changes in v2:
 - Reworked qcom_cc_bind() function
 - Added timeout to qcom_power_set()
 - Minor fixes in register names and formatting

 drivers/clk/qcom/clock-qcom.c | 128 ++++++++++++++++++++++++++++++----
 drivers/clk/qcom/clock-qcom.h |   6 ++
 2 files changed, 121 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 729d190c54..c3f8d96183 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -23,6 +23,7 @@
 #include <linux/delay.h>
 #include <linux/bitops.h>
 #include <reset-uclass.h>
+#include <power-domain-uclass.h>
 
 #include "clock-qcom.h"
 
@@ -30,6 +31,13 @@
 #define CBCR_BRANCH_ENABLE_BIT  BIT(0)
 #define CBCR_BRANCH_OFF_BIT     BIT(31)
 
+#define GDSC_SW_COLLAPSE_MASK		BIT(0)
+#define GDSC_POWER_DOWN_COMPLETE	BIT(15)
+#define GDSC_POWER_UP_COMPLETE		BIT(16)
+#define GDSC_PWR_ON_MASK		BIT(31)
+#define CFG_GDSCR_OFFSET		0x4
+#define GDSC_STATUS_POLL_TIMEOUT_US	1500
+
 /* Enable clock controlled by CBC soft macro */
 void clk_enable_cbc(phys_addr_t cbcr)
 {
@@ -223,7 +231,7 @@ U_BOOT_DRIVER(qcom_clk) = {
 int qcom_cc_bind(struct udevice *parent)
 {
 	struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent);
-	struct udevice *clkdev, *rstdev;
+	struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev;
 	struct driver *drv;
 	int ret;
 
@@ -238,20 +246,41 @@ int qcom_cc_bind(struct udevice *parent)
 	if (ret)
 		return ret;
 
-	/* Bail out early if resets are not specified for this platform */
-	if (!data->resets)
-		return ret;
+	if (data->resets) {
+		/* Get a handle to the common reset handler */
+		drv = lists_driver_lookup_name("qcom_reset");
+		if (!drv) {
+			ret = -ENOENT;
+			goto unbind_clkdev;
+		}
+
+		/* Register the reset controller */
+		ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
+						   dev_ofnode(parent), &rstdev);
+		if (ret)
+			goto unbind_clkdev;
+	}
 
-	/* Get a handle to the common reset handler */
-	drv = lists_driver_lookup_name("qcom_reset");
-	if (!drv)
-		return -ENOENT;
+	if (data->power_domains) {
+		/* Get a handle to the common power domain handler */
+		drv = lists_driver_lookup_name("qcom_power");
+		if (!drv) {
+			ret = -ENOENT;
+			goto unbind_rstdev;
+		}
+		/* Register the power domain controller */
+		ret = device_bind_with_driver_data(parent, drv, "qcom_power", (ulong)data,
+						   dev_ofnode(parent), &pwrdev);
+		if (ret)
+			goto unbind_rstdev;
+	}
 
-	/* Register the reset controller */
-	ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
-					   dev_ofnode(parent), &rstdev);
-	if (ret)
-		device_unbind(clkdev);
+	return 0;
+
+unbind_rstdev:
+	device_unbind(rstdev);
+unbind_clkdev:
+	device_unbind(clkdev);
 
 	return ret;
 }
@@ -306,3 +335,76 @@ U_BOOT_DRIVER(qcom_reset) = {
 	.ops = &qcom_reset_ops,
 	.probe = qcom_reset_probe,
 };
+
+static int qcom_power_set(struct power_domain *pwr, bool on)
+{
+	struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev);
+	void __iomem *base = dev_get_priv(pwr->dev);
+	unsigned long timeout;
+	const struct qcom_power_map *map;
+	u32 value;
+
+	if (pwr->id >= data->num_power_domains)
+		return -ENODEV;
+
+	map = &data->power_domains[pwr->id];
+
+	if (!map->reg)
+		return -ENODEV;
+
+	value = readl(base + map->reg);
+
+	if (on)
+		value &= ~GDSC_SW_COLLAPSE_MASK;
+	else
+		value |= GDSC_SW_COLLAPSE_MASK;
+
+	writel(value, base + map->reg);
+
+	timeout = timer_get_us() + GDSC_STATUS_POLL_TIMEOUT_US;
+	/* Wait for power on */
+	while (timeout > timer_get_us()) {
+		value = readl(base + map->reg + CFG_GDSCR_OFFSET);
+		if (on) {
+			if ((value & GDSC_POWER_UP_COMPLETE) ||
+			    (value & GDSC_PWR_ON_MASK))
+				return 0;
+		} else {
+			if (value & GDSC_POWER_DOWN_COMPLETE ||
+			    !(value & GDSC_PWR_ON_MASK))
+				return 0;
+		}
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int qcom_power_on(struct power_domain *pwr)
+{
+	return qcom_power_set(pwr, true);
+}
+
+static int qcom_power_off(struct power_domain *pwr)
+{
+	return qcom_power_set(pwr, false);
+}
+
+static const struct power_domain_ops qcom_power_ops = {
+	.on = qcom_power_on,
+	.off = qcom_power_off,
+};
+
+static int qcom_power_probe(struct udevice *dev)
+{
+	/* Set our priv pointer to the base address */
+	dev_set_priv(dev, (void *)dev_read_addr(dev));
+
+	return 0;
+}
+
+U_BOOT_DRIVER(qcom_power) = {
+	.name = "qcom_power",
+	.id = UCLASS_POWER_DOMAIN,
+	.ops = &qcom_power_ops,
+	.probe = qcom_power_probe,
+};
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 01088c1901..12a1eaec2b 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -59,9 +59,15 @@ struct qcom_reset_map {
 	u8 bit;
 };
 
+struct qcom_power_map {
+	unsigned int reg;
+};
+
 struct clk;
 
 struct msm_clk_data {
+	const struct qcom_power_map	*power_domains;
+	unsigned long			num_power_domains;
 	const struct qcom_reset_map	*resets;
 	unsigned long			num_resets;
 	const struct gate_clk		*clks;
-- 
2.43.0

Re: [PATCH v2 4/8] clk: qcom: add support for power domains uclass

[Sumit Garg]

On Wed, 6 Mar 2024 at 06:23, Volodymyr Babchuk
<Volodymyr_Babchuk@epam.com> wrote:
>
> Now sub-drivers for particular SoCs can register them as power domain
> drivers. This is needed for upcoming SM8150 support, because it needs
> to power up the Ethernet module.
>
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>
> ---
>
> Changes in v2:
>  - Reworked qcom_cc_bind() function
>  - Added timeout to qcom_power_set()
>  - Minor fixes in register names and formatting
>
>  drivers/clk/qcom/clock-qcom.c | 128 ++++++++++++++++++++++++++++++----
>  drivers/clk/qcom/clock-qcom.h |   6 ++
>  2 files changed, 121 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index 729d190c54..c3f8d96183 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -23,6 +23,7 @@
>  #include <linux/delay.h>
>  #include <linux/bitops.h>
>  #include <reset-uclass.h>
> +#include <power-domain-uclass.h>
>
>  #include "clock-qcom.h"
>
> @@ -30,6 +31,13 @@
>  #define CBCR_BRANCH_ENABLE_BIT  BIT(0)
>  #define CBCR_BRANCH_OFF_BIT     BIT(31)
>
> +#define GDSC_SW_COLLAPSE_MASK          BIT(0)
> +#define GDSC_POWER_DOWN_COMPLETE       BIT(15)
> +#define GDSC_POWER_UP_COMPLETE         BIT(16)
> +#define GDSC_PWR_ON_MASK               BIT(31)
> +#define CFG_GDSCR_OFFSET               0x4
> +#define GDSC_STATUS_POLL_TIMEOUT_US    1500
> +
>  /* Enable clock controlled by CBC soft macro */
>  void clk_enable_cbc(phys_addr_t cbcr)
>  {
> @@ -223,7 +231,7 @@ U_BOOT_DRIVER(qcom_clk) = {
>  int qcom_cc_bind(struct udevice *parent)
>  {
>         struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent);
> -       struct udevice *clkdev, *rstdev;
> +       struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev;
>         struct driver *drv;
>         int ret;
>
> @@ -238,20 +246,41 @@ int qcom_cc_bind(struct udevice *parent)
>         if (ret)
>                 return ret;
>
> -       /* Bail out early if resets are not specified for this platform */
> -       if (!data->resets)
> -               return ret;
> +       if (data->resets) {
> +               /* Get a handle to the common reset handler */
> +               drv = lists_driver_lookup_name("qcom_reset");
> +               if (!drv) {
> +                       ret = -ENOENT;
> +                       goto unbind_clkdev;
> +               }
> +
> +               /* Register the reset controller */
> +               ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
> +                                                  dev_ofnode(parent), &rstdev);
> +               if (ret)
> +                       goto unbind_clkdev;
> +       }
>
> -       /* Get a handle to the common reset handler */
> -       drv = lists_driver_lookup_name("qcom_reset");
> -       if (!drv)
> -               return -ENOENT;
> +       if (data->power_domains) {
> +               /* Get a handle to the common power domain handler */
> +               drv = lists_driver_lookup_name("qcom_power");
> +               if (!drv) {
> +                       ret = -ENOENT;
> +                       goto unbind_rstdev;
> +               }
> +               /* Register the power domain controller */
> +               ret = device_bind_with_driver_data(parent, drv, "qcom_power", (ulong)data,
> +                                                  dev_ofnode(parent), &pwrdev);
> +               if (ret)
> +                       goto unbind_rstdev;
> +       }
>
> -       /* Register the reset controller */
> -       ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
> -                                          dev_ofnode(parent), &rstdev);
> -       if (ret)
> -               device_unbind(clkdev);
> +       return 0;
> +
> +unbind_rstdev:
> +       device_unbind(rstdev);
> +unbind_clkdev:
> +       device_unbind(clkdev);
>
>         return ret;
>  }
> @@ -306,3 +335,76 @@ U_BOOT_DRIVER(qcom_reset) = {
>         .ops = &qcom_reset_ops,
>         .probe = qcom_reset_probe,
>  };
> +
> +static int qcom_power_set(struct power_domain *pwr, bool on)
> +{
> +       struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev);
> +       void __iomem *base = dev_get_priv(pwr->dev);
> +       unsigned long timeout;
> +       const struct qcom_power_map *map;
> +       u32 value;
> +
> +       if (pwr->id >= data->num_power_domains)
> +               return -ENODEV;
> +
> +       map = &data->power_domains[pwr->id];
> +
> +       if (!map->reg)
> +               return -ENODEV;
> +
> +       value = readl(base + map->reg);
> +
> +       if (on)
> +               value &= ~GDSC_SW_COLLAPSE_MASK;
> +       else
> +               value |= GDSC_SW_COLLAPSE_MASK;
> +
> +       writel(value, base + map->reg);
> +
> +       timeout = timer_get_us() + GDSC_STATUS_POLL_TIMEOUT_US;
> +       /* Wait for power on */
> +       while (timeout > timer_get_us()) {
> +               value = readl(base + map->reg + CFG_GDSCR_OFFSET);

You should be able to reuse readl_poll_timeout() here instead.

-Sumit

> +               if (on) {
> +                       if ((value & GDSC_POWER_UP_COMPLETE) ||
> +                           (value & GDSC_PWR_ON_MASK))
> +                               return 0;
> +               } else {
> +                       if (value & GDSC_POWER_DOWN_COMPLETE ||
> +                           !(value & GDSC_PWR_ON_MASK))
> +                               return 0;
> +               }
> +       }
> +
> +       return -ETIMEDOUT;
> +}
> +
> +static int qcom_power_on(struct power_domain *pwr)
> +{
> +       return qcom_power_set(pwr, true);
> +}
> +
> +static int qcom_power_off(struct power_domain *pwr)
> +{
> +       return qcom_power_set(pwr, false);
> +}
> +
> +static const struct power_domain_ops qcom_power_ops = {
> +       .on = qcom_power_on,
> +       .off = qcom_power_off,
> +};
> +
> +static int qcom_power_probe(struct udevice *dev)
> +{
> +       /* Set our priv pointer to the base address */
> +       dev_set_priv(dev, (void *)dev_read_addr(dev));
> +
> +       return 0;
> +}
> +
> +U_BOOT_DRIVER(qcom_power) = {
> +       .name = "qcom_power",
> +       .id = UCLASS_POWER_DOMAIN,
> +       .ops = &qcom_power_ops,
> +       .probe = qcom_power_probe,
> +};
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 01088c1901..12a1eaec2b 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -59,9 +59,15 @@ struct qcom_reset_map {
>         u8 bit;
>  };
>
> +struct qcom_power_map {
> +       unsigned int reg;
> +};
> +
>  struct clk;
>
>  struct msm_clk_data {
> +       const struct qcom_power_map     *power_domains;
> +       unsigned long                   num_power_domains;
>         const struct qcom_reset_map     *resets;
>         unsigned long                   num_resets;
>         const struct gate_clk           *clks;
> --
> 2.43.0

Re: [PATCH v2 4/8] clk: qcom: add support for power domains uclass

[Caleb Connolly]

Hi Volodymyr,

On 06/03/2024 00:53, Volodymyr Babchuk wrote:
> Now sub-drivers for particular SoCs can register them as power domain
> drivers. This is needed for upcoming SM8150 support, because it needs
> to power up the Ethernet module.
> 
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> 
> ---
> 
> Changes in v2:
>  - Reworked qcom_cc_bind() function
>  - Added timeout to qcom_power_set()
>  - Minor fixes in register names and formatting
> 
>  drivers/clk/qcom/clock-qcom.c | 128 ++++++++++++++++++++++++++++++----
>  drivers/clk/qcom/clock-qcom.h |   6 ++
>  2 files changed, 121 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index 729d190c54..c3f8d96183 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -23,6 +23,7 @@
>  #include <linux/delay.h>
>  #include <linux/bitops.h>
>  #include <reset-uclass.h>
> +#include <power-domain-uclass.h>

The Kconfig should reflect this, please make CLK_QCOM imply POWER_DOMAIN.

[...]

> +static int qcom_power_set(struct power_domain *pwr, bool on)
> +{
> +	struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev);
> +	void __iomem *base = dev_get_priv(pwr->dev);
> +	unsigned long timeout;
> +	const struct qcom_power_map *map;
> +	u32 value;
> +
> +	if (pwr->id >= data->num_power_domains)
> +		return -ENODEV;
> +
> +	map = &data->power_domains[pwr->id];
> +
> +	if (!map->reg)
> +		return -ENODEV;
> +
> +	value = readl(base + map->reg);
> +
> +	if (on)
> +		value &= ~GDSC_SW_COLLAPSE_MASK;
> +	else
> +		value |= GDSC_SW_COLLAPSE_MASK;
> +
> +	writel(value, base + map->reg);
> +
> +	timeout = timer_get_us() + GDSC_STATUS_POLL_TIMEOUT_US;
> +	/* Wait for power on */
> +	while (timeout > timer_get_us()) {
> +		value = readl(base + map->reg + CFG_GDSCR_OFFSET);
> +		if (on) {
> +			if ((value & GDSC_POWER_UP_COMPLETE) ||
> +			    (value & GDSC_PWR_ON_MASK))
> +				return 0;
> +		} else {
> +			if (value & GDSC_POWER_DOWN_COMPLETE ||
> +			    !(value & GDSC_PWR_ON_MASK))
> +				return 0;
> +		}
> +	}
> +
Usually this error condition is indicative of a driver bug somewhere -
that the GCC is misconfigured. We should follow Linux and print a noisy
"WARNING: GDSC %p stuck off/on" message here.
> +	return -ETIMEDOUT;
> +}
> +
> +static int qcom_power_on(struct power_domain *pwr)
> +{
> +	return qcom_power_set(pwr, true);
> +}
> +
> +static int qcom_power_off(struct power_domain *pwr)
> +{
> +	return qcom_power_set(pwr, false);
> +}
> +
> +static const struct power_domain_ops qcom_power_ops = {
> +	.on = qcom_power_on,
> +	.off = qcom_power_off,
> +};
> +
> +static int qcom_power_probe(struct udevice *dev)
> +{
> +	/* Set our priv pointer to the base address */
> +	dev_set_priv(dev, (void *)dev_read_addr(dev));
> +
> +	return 0;
> +}
> +
> +U_BOOT_DRIVER(qcom_power) = {
> +	.name = "qcom_power",
> +	.id = UCLASS_POWER_DOMAIN,
> +	.ops = &qcom_power_ops,
> +	.probe = qcom_power_probe,
> +};
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 01088c1901..12a1eaec2b 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -59,9 +59,15 @@ struct qcom_reset_map {
>  	u8 bit;
>  };
>  
> +struct qcom_power_map {
> +	unsigned int reg;
> +};
> +
>  struct clk;
>  
>  struct msm_clk_data {
> +	const struct qcom_power_map	*power_domains;
> +	unsigned long			num_power_domains;
>  	const struct qcom_reset_map	*resets;
>  	unsigned long			num_resets;
>  	const struct gate_clk		*clks;

-- 
// Caleb (they/them)

[PATCH v2 6/8] pinctrl: qcom: pass pin number to get_function_mux callback

[Volodymyr Babchuk]

This patch is the preparation for SM8150 support. This new SoC
depending on the particular pin can have different numbers for the
same function. For example "rgmii" function for GPIO4 has id=2 while
for GPIO59 it has id=1. So, to support this type of SoCs,
get_function_mux() callback needs to know for which pin the function
is requested.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>

---

Changes in v2:
 - Added Caleb's R-b tag

 drivers/pinctrl/qcom/pinctrl-apq8016.c | 3 ++-
 drivers/pinctrl/qcom/pinctrl-apq8096.c | 3 ++-
 drivers/pinctrl/qcom/pinctrl-ipq4019.c | 3 ++-
 drivers/pinctrl/qcom/pinctrl-qcom.c    | 4 ++--
 drivers/pinctrl/qcom/pinctrl-qcom.h    | 3 ++-
 drivers/pinctrl/qcom/pinctrl-qcs404.c  | 3 ++-
 drivers/pinctrl/qcom/pinctrl-sdm845.c  | 3 ++-
 7 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index db0e212468..a9a00f4b08 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -49,7 +49,8 @@ static const char *apq8016_get_pin_name(struct udevice *dev,
 	}
 }
 
-static unsigned int apq8016_get_function_mux(unsigned int selector)
+static unsigned int apq8016_get_function_mux(__maybe_unused unsigned int pin,
+					     unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c
index 880df8fe3c..9697cb5beb 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
@@ -44,7 +44,8 @@ static const char *apq8096_get_pin_name(struct udevice *dev,
 	}
 }
 
-static unsigned int apq8096_get_function_mux(unsigned int selector)
+static unsigned int apq8096_get_function_mux(__maybe_unused unsigned int pin,
+					     unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 74c04ab87c..4479230313 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -40,7 +40,8 @@ static const char *ipq4019_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int ipq4019_get_function_mux(unsigned int selector)
+static unsigned int ipq4019_get_function_mux(__maybe_unused unsigned int pin,
+					     unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
index ee0624df29..909e566acf 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -83,14 +83,14 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
 			  unsigned int func_selector)
 {
 	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+	u32 func = priv->data->get_function_mux(pin_selector, func_selector);
 
 	/* Always NOP for special pins, assume they're in the correct state */
 	if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
 		return 0;
 
 	clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
-			TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
-			priv->data->get_function_mux(func_selector) << 2);
+			TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2);
 	return 0;
 }
 
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h
index 07f2eae9ba..49b7bfbc00 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.h
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.h
@@ -18,7 +18,8 @@ struct msm_pinctrl_data {
 	int functions_count;
 	const char *(*get_function_name)(struct udevice *dev,
 					 unsigned int selector);
-	unsigned int (*get_function_mux)(unsigned int selector);
+	unsigned int (*get_function_mux)(unsigned int pin,
+					 unsigned int selector);
 	const char *(*get_pin_name)(struct udevice *dev,
 				    unsigned int selector);
 };
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
index 3a2d468599..4b7c670c90 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -94,7 +94,8 @@ static const char *qcs404_get_pin_name(struct udevice *dev,
 	}
 }
 
-static unsigned int qcs404_get_function_mux(unsigned int selector)
+static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin,
+					    unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 76bd8c4ef4..459a4329ec 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -70,7 +70,8 @@ static const char *sdm845_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int sdm845_get_function_mux(unsigned int selector)
+static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin,
+					    unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
-- 
2.43.0

Re: [PATCH v2 6/8] pinctrl: qcom: pass pin number to get_function_mux callback

[Sumit Garg]

On Wed, 6 Mar 2024 at 06:23, Volodymyr Babchuk
<Volodymyr_Babchuk@epam.com> wrote:
>
> This patch is the preparation for SM8150 support. This new SoC
> depending on the particular pin can have different numbers for the
> same function. For example "rgmii" function for GPIO4 has id=2 while
> for GPIO59 it has id=1. So, to support this type of SoCs,
> get_function_mux() callback needs to know for which pin the function
> is requested.
>
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
>
> ---
>
> Changes in v2:
>  - Added Caleb's R-b tag
>
>  drivers/pinctrl/qcom/pinctrl-apq8016.c | 3 ++-
>  drivers/pinctrl/qcom/pinctrl-apq8096.c | 3 ++-
>  drivers/pinctrl/qcom/pinctrl-ipq4019.c | 3 ++-
>  drivers/pinctrl/qcom/pinctrl-qcom.c    | 4 ++--
>  drivers/pinctrl/qcom/pinctrl-qcom.h    | 3 ++-
>  drivers/pinctrl/qcom/pinctrl-qcs404.c  | 3 ++-
>  drivers/pinctrl/qcom/pinctrl-sdm845.c  | 3 ++-
>  7 files changed, 14 insertions(+), 8 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> index db0e212468..a9a00f4b08 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
> @@ -49,7 +49,8 @@ static const char *apq8016_get_pin_name(struct udevice *dev,
>         }
>  }
>
> -static unsigned int apq8016_get_function_mux(unsigned int selector)
> +static unsigned int apq8016_get_function_mux(__maybe_unused unsigned int pin,
> +                                            unsigned int selector)
>  {
>         return msm_pinctrl_functions[selector].val;
>  }
> diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c
> index 880df8fe3c..9697cb5beb 100644
> --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
> +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
> @@ -44,7 +44,8 @@ static const char *apq8096_get_pin_name(struct udevice *dev,
>         }
>  }
>
> -static unsigned int apq8096_get_function_mux(unsigned int selector)
> +static unsigned int apq8096_get_function_mux(__maybe_unused unsigned int pin,
> +                                            unsigned int selector)
>  {
>         return msm_pinctrl_functions[selector].val;
>  }
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> index 74c04ab87c..4479230313 100644
> --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> @@ -40,7 +40,8 @@ static const char *ipq4019_get_pin_name(struct udevice *dev,
>         return pin_name;
>  }
>
> -static unsigned int ipq4019_get_function_mux(unsigned int selector)
> +static unsigned int ipq4019_get_function_mux(__maybe_unused unsigned int pin,
> +                                            unsigned int selector)
>  {
>         return msm_pinctrl_functions[selector].val;
>  }
> diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
> index ee0624df29..909e566acf 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qcom.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
> @@ -83,14 +83,14 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
>                           unsigned int func_selector)
>  {
>         struct msm_pinctrl_priv *priv = dev_get_priv(dev);
> +       u32 func = priv->data->get_function_mux(pin_selector, func_selector);
>
>         /* Always NOP for special pins, assume they're in the correct state */
>         if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
>                 return 0;
>
>         clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
> -                       TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
> -                       priv->data->get_function_mux(func_selector) << 2);
> +                       TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2);
>         return 0;
>  }
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h
> index 07f2eae9ba..49b7bfbc00 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qcom.h
> +++ b/drivers/pinctrl/qcom/pinctrl-qcom.h
> @@ -18,7 +18,8 @@ struct msm_pinctrl_data {
>         int functions_count;
>         const char *(*get_function_name)(struct udevice *dev,
>                                          unsigned int selector);
> -       unsigned int (*get_function_mux)(unsigned int selector);
> +       unsigned int (*get_function_mux)(unsigned int pin,
> +                                        unsigned int selector);
>         const char *(*get_pin_name)(struct udevice *dev,
>                                     unsigned int selector);
>  };
> diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
> index 3a2d468599..4b7c670c90 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
> @@ -94,7 +94,8 @@ static const char *qcs404_get_pin_name(struct udevice *dev,
>         }
>  }
>
> -static unsigned int qcs404_get_function_mux(unsigned int selector)
> +static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin,
> +                                           unsigned int selector)
>  {
>         return msm_pinctrl_functions[selector].val;
>  }
> diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
> index 76bd8c4ef4..459a4329ec 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
> @@ -70,7 +70,8 @@ static const char *sdm845_get_pin_name(struct udevice *dev,
>         return pin_name;
>  }
>
> -static unsigned int sdm845_get_function_mux(unsigned int selector)
> +static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin,
> +                                           unsigned int selector)
>  {
>         return msm_pinctrl_functions[selector].val;
>  }
> --
> 2.43.0

[PATCH v2 5/8] clk: qcom: add driver for SM8150 SoC

[Volodymyr Babchuk]

Add clock, reset and power domain driver for SM8150. Driver code is
based on the similar U-Boot drivers. All constants are taken from the
corresponding Linux driver.

This driver supports clock rate setting only for the debug UART and
RGMII/Ethernet modules, because this is all I can test right now.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

---

Changes in v2:
 - Renamed GPLL7_MAIN to just GPLL7 (while I like idea to use Linux
   naming convention, such rework needs to be done in a separate
   commit)
 - Removed unnecessary include
 - Fixed GDSCR register values for couple of devices
 - Enable GPLL7 only when RGMII clock is enabled

 drivers/clk/qcom/Kconfig        |   8 ++
 drivers/clk/qcom/Makefile       |   1 +
 drivers/clk/qcom/clock-qcom.h   |   1 +
 drivers/clk/qcom/clock-sm8150.c | 237 ++++++++++++++++++++++++++++++++
 4 files changed, 247 insertions(+)
 create mode 100644 drivers/clk/qcom/clock-sm8150.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0df0d1881a..18ccf6a45e 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -47,6 +47,14 @@ config CLK_QCOM_SDM845
 	  on the Snapdragon 845 SoC. This driver supports the clocks
 	  and resets exposed by the GCC hardware block.
 
+config CLK_QCOM_SM8150
+	bool "Qualcomm SM8150 GCC"
+	select CLK_QCOM
+	help
+	  Say Y here to enable support for the Global Clock Controller
+	  on the Snapdragon 8150 SoC. This driver supports the clocks
+	  and resets exposed by the GCC hardware block.
+
 endmenu
 
 endif
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index cb179fdac5..12c09ba19e 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
 obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
 obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
 obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
+obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 12a1eaec2b..dd40487e94 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -9,6 +9,7 @@
 
 #define CFG_CLK_SRC_CXO   (0 << 8)
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
+#define CFG_CLK_SRC_GPLL7 (3 << 8)
 #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
 #define CFG_CLK_SRC_MASK  (7 << 8)
 
diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c
new file mode 100644
index 0000000000..2592eef29b
--- /dev/null
+++ b/drivers/clk/qcom/clock-sm8150.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm SM8150
+ *
+ * Volodymyr Babchuk <volodymyr_babchuk@epam.com>
+ * Copyright (c) 2024 EPAM Systems.
+ *
+ * Based on U-Boot driver for SDM845. Constants are taken from the Linux driver.
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,gcc-sm8150.h>
+
+#include "clock-qcom.h"
+
+static struct pll_vote_clk gpll7_vote_clk = {
+	.status = 0x1a000,
+	.status_bit = BIT(31),
+	.ena_vote = 0x52000,
+	.vote_bit = BIT(7),
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+	F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+	F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+	F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+	F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+	F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+	F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+	F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+	F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+	F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
+	F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
+	F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
+	F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
+	F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
+	F(2500000, CFG_CLK_SRC_CXO, 1, 25, 192),
+	F(5000000, CFG_CLK_SRC_CXO, 1, 25, 96),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+	F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+	F(125000000, CFG_CLK_SRC_GPLL7, 4, 0, 0),
+	F(250000000, CFG_CLK_SRC_GPLL7, 2, 0, 0),
+	{ }
+};
+
+static const struct bcr_regs uart2_regs = {
+	.cfg_rcgr = 0x1814C,
+	.cmd_rcgr = 0x18148,
+	.M = 0x18150,
+	.N = 0x18154,
+	.D = 0x18158,
+};
+
+static const struct bcr_regs rgmii_regs = {
+	.cfg_rcgr = 0x6020,
+	.cmd_rcgr = 0x601C,
+	.M = 0x6024,
+	.N = 0x6028,
+	.D = 0x602C,
+};
+
+static ulong sm8150_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct freq_tbl *freq;
+
+	switch (clk->id) {
+	case GCC_QUPV3_WRAP1_S4_CLK: /* UART2 aka debug-uart */
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_EMAC_RGMII_CLK:
+		freq = qcom_find_freq(ftbl_gcc_emac_rgmii_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, &rgmii_regs,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+
+		return freq->freq;
+	default:
+		pr_err("Don't know how to set clk id %ld\n", clk->id);
+		return -EINVAL;
+	}
+}
+
+static const struct gate_clk sm8150_clks[] = {
+	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK,		0x5200c, 0x00000400),
+	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK,		0x5200c, 0x00000800),
+	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK,		0x5200c, 0x00001000),
+	GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK,		0x5200c, 0x00002000),
+	GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK,		0x5200c, 0x00004000),
+	GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK,		0x5200c, 0x00008000),
+	GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK,		0x5200c, 0x00400000),
+	GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK,		0x5200c, 0x00800000),
+	GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK,		0x5200c, 0x02000000),
+	GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK,		0x5200c, 0x04000000),
+	GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK,		0x5200c, 0x08000000),
+	GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK,		0x5200c, 0x00000040),
+	GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK,		0x5200c, 0x00000080),
+	GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK,		0x5200c, 0x00100000),
+	GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK,		0x5200c, 0x00200000),
+	GATE_CLK(GCC_SDCC2_AHB_CLK,			0x14008, 0x00000001),
+	GATE_CLK(GCC_SDCC2_APPS_CLK,			0x14004, 0x00000001),
+	GATE_CLK(GCC_SDCC4_AHB_CLK,			0x16008, 0x00000001),
+	GATE_CLK(GCC_SDCC4_APPS_CLK,			0x16004, 0x00000001),
+	GATE_CLK(GCC_UFS_CARD_AHB_CLK,			0x75010, 0x00000001),
+	GATE_CLK(GCC_UFS_CARD_AXI_CLK,			0x7500c, 0x00000001),
+	GATE_CLK(GCC_UFS_CARD_CLKREF_CLK,		0x8c004, 0x00000001),
+	GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK,		0x75058, 0x00000001),
+	GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK,		0x7508c, 0x00000001),
+	GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK,		0x75018, 0x00000001),
+	GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK,		0x750a8, 0x00000001),
+	GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK,		0x75014, 0x00000001),
+	GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK,		0x75054, 0x00000001),
+	GATE_CLK(GCC_UFS_MEM_CLKREF_CLK,		0x8c000, 0x00000001),
+	GATE_CLK(GCC_UFS_PHY_AHB_CLK,			0x77010, 0x00000001),
+	GATE_CLK(GCC_UFS_PHY_AXI_CLK,			0x7700c, 0x00000001),
+	GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK,		0x77058, 0x00000001),
+	GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK,		0x7708c, 0x00000001),
+	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK,		0x77018, 0x00000001),
+	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK,		0x770a8, 0x00000001),
+	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK,		0x77014, 0x00000001),
+	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK,		0x77054, 0x00000001),
+	GATE_CLK(GCC_USB30_PRIM_MASTER_CLK,		0x0f00c, 0x00000001),
+	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK,		0x0f014, 0x00000001),
+	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK,		0x0f010, 0x00000001),
+	GATE_CLK(GCC_USB30_SEC_MASTER_CLK,		0x1000c, 0x00000001),
+	GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK,		0x10014, 0x00000001),
+	GATE_CLK(GCC_USB30_SEC_SLEEP_CLK,		0x10010, 0x00000001),
+	GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK,		0x8c008, 0x00000001),
+	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK,		0x0f04c, 0x00000001),
+	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK,		0x0f050, 0x00000001),
+	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK,		0x0f054, 0x00000001),
+	GATE_CLK(GCC_USB3_SEC_CLKREF_CLK,		0x8c028, 0x00000001),
+	GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK,		0x1004c, 0x00000001),
+	GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK,		0x10054, 0x00000001),
+	GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK,		0x10050, 0x00000001),
+	GATE_CLK(GCC_EMAC_AXI_CLK,			0x06010, 0x00000001),
+	GATE_CLK(GCC_EMAC_SLV_AHB_CLK,			0x06014, 0x00000001),
+	GATE_CLK(GCC_EMAC_PTP_CLK,			0x06034, 0x00000001),
+	GATE_CLK(GCC_EMAC_RGMII_CLK,			0x06018, 0x00000001),
+};
+
+static int sm8150_clk_enable(struct clk *clk)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case GCC_EMAC_RGMII_CLK:
+		clk_enable_gpll0(priv->base, &gpll7_vote_clk);
+	};
+
+	qcom_gate_clk_en(priv, clk->id);
+
+	return 0;
+}
+
+static const struct qcom_reset_map sm8150_gcc_resets[] = {
+	[GCC_EMAC_BCR] = { 0x6000 },
+	[GCC_GPU_BCR] = { 0x71000 },
+	[GCC_MMSS_BCR] = { 0xb000 },
+	[GCC_NPU_BCR] = { 0x4d000 },
+	[GCC_PCIE_0_BCR] = { 0x6b000 },
+	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
+	[GCC_PCIE_1_BCR] = { 0x8d000 },
+	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
+	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
+	[GCC_PDM_BCR] = { 0x33000 },
+	[GCC_PRNG_BCR] = { 0x34000 },
+	[GCC_QSPI_BCR] = { 0x24008 },
+	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
+	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
+	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
+	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
+	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
+	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
+	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
+	[GCC_SDCC2_BCR] = { 0x14000 },
+	[GCC_SDCC4_BCR] = { 0x16000 },
+	[GCC_TSIF_BCR] = { 0x36000 },
+	[GCC_UFS_CARD_BCR] = { 0x75000 },
+	[GCC_UFS_PHY_BCR] = { 0x77000 },
+	[GCC_USB30_PRIM_BCR] = { 0xf000 },
+	[GCC_USB30_SEC_BCR] = { 0x10000 },
+	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static const struct qcom_power_map sm8150_gcc_power_domains[] = {
+	[EMAC_GDSC] = { 0x6004 },
+	[PCIE_0_GDSC] = { 0x6b004 },
+	[PCIE_1_GDSC] = { 0x8d004 },
+	[UFS_CARD_GDSC] = { 0x75004 },
+	[UFS_PHY_GDSC] = { 0x77004 },
+	[USB30_PRIM_GDSC] = { 0xf004 },
+	[USB30_SEC_GDSC] = { 0x10004 },
+};
+
+
+static struct msm_clk_data sm8150_clk_data = {
+	.resets = sm8150_gcc_resets,
+	.num_resets = ARRAY_SIZE(sm8150_gcc_resets),
+	.clks = sm8150_clks,
+	.num_clks = ARRAY_SIZE(sm8150_clks),
+	.power_domains = sm8150_gcc_power_domains,
+	.num_power_domains = ARRAY_SIZE(sm8150_gcc_power_domains),
+
+	.enable = sm8150_clk_enable,
+	.set_rate = sm8150_clk_set_rate,
+};
+
+static const struct udevice_id gcc_sm8150_of_match[] = {
+	{
+		.compatible = "qcom,gcc-sm8150",
+		.data = (ulong)&sm8150_clk_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(gcc_sm8150) = {
+	.name		= "gcc_sm8150",
+	.id		= UCLASS_NOP,
+	.of_match	= gcc_sm8150_of_match,
+	.bind		= qcom_cc_bind,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
-- 
2.43.0

Re: [PATCH v2 5/8] clk: qcom: add driver for SM8150 SoC

[Sumit Garg]

On Wed, 6 Mar 2024 at 06:23, Volodymyr Babchuk
<Volodymyr_Babchuk@epam.com> wrote:
>
> Add clock, reset and power domain driver for SM8150. Driver code is
> based on the similar U-Boot drivers. All constants are taken from the
> corresponding Linux driver.
>
> This driver supports clock rate setting only for the debug UART and
> RGMII/Ethernet modules, because this is all I can test right now.
>
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>
> ---
>
> Changes in v2:
>  - Renamed GPLL7_MAIN to just GPLL7 (while I like idea to use Linux
>    naming convention, such rework needs to be done in a separate
>    commit)
>  - Removed unnecessary include
>  - Fixed GDSCR register values for couple of devices
>  - Enable GPLL7 only when RGMII clock is enabled
>
>  drivers/clk/qcom/Kconfig        |   8 ++
>  drivers/clk/qcom/Makefile       |   1 +
>  drivers/clk/qcom/clock-qcom.h   |   1 +
>  drivers/clk/qcom/clock-sm8150.c | 237 ++++++++++++++++++++++++++++++++
>  4 files changed, 247 insertions(+)
>  create mode 100644 drivers/clk/qcom/clock-sm8150.c
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 0df0d1881a..18ccf6a45e 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -47,6 +47,14 @@ config CLK_QCOM_SDM845
>           on the Snapdragon 845 SoC. This driver supports the clocks
>           and resets exposed by the GCC hardware block.
>
> +config CLK_QCOM_SM8150
> +       bool "Qualcomm SM8150 GCC"
> +       select CLK_QCOM
> +       help
> +         Say Y here to enable support for the Global Clock Controller
> +         on the Snapdragon 8150 SoC. This driver supports the clocks
> +         and resets exposed by the GCC hardware block.
> +
>  endmenu
>
>  endif
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index cb179fdac5..12c09ba19e 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
>  obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
>  obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
>  obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
> +obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 12a1eaec2b..dd40487e94 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -9,6 +9,7 @@
>
>  #define CFG_CLK_SRC_CXO   (0 << 8)
>  #define CFG_CLK_SRC_GPLL0 (1 << 8)
> +#define CFG_CLK_SRC_GPLL7 (3 << 8)
>  #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
>  #define CFG_CLK_SRC_MASK  (7 << 8)
>
> diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c
> new file mode 100644
> index 0000000000..2592eef29b
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-sm8150.c
> @@ -0,0 +1,237 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Clock drivers for Qualcomm SM8150
> + *
> + * Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> + * Copyright (c) 2024 EPAM Systems.
> + *
> + * Based on U-Boot driver for SDM845. Constants are taken from the Linux driver.
> + */
> +
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <linux/bitops.h>
> +#include <dt-bindings/clock/qcom,gcc-sm8150.h>
> +
> +#include "clock-qcom.h"
> +
> +static struct pll_vote_clk gpll7_vote_clk = {
> +       .status = 0x1a000,
> +       .status_bit = BIT(31),
> +       .ena_vote = 0x52000,
> +       .vote_bit = BIT(7),
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
> +       F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
> +       F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
> +       F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> +       F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
> +       F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
> +       F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
> +       F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
> +       F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
> +       F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
> +       F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
> +       F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
> +       F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
> +       F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
> +       F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
> +       F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
> +       { }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
> +       F(2500000, CFG_CLK_SRC_CXO, 1, 25, 192),
> +       F(5000000, CFG_CLK_SRC_CXO, 1, 25, 96),
> +       F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> +       F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
> +       F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
> +       F(125000000, CFG_CLK_SRC_GPLL7, 4, 0, 0),
> +       F(250000000, CFG_CLK_SRC_GPLL7, 2, 0, 0),
> +       { }
> +};
> +
> +static const struct bcr_regs uart2_regs = {
> +       .cfg_rcgr = 0x1814C,
> +       .cmd_rcgr = 0x18148,
> +       .M = 0x18150,
> +       .N = 0x18154,
> +       .D = 0x18158,
> +};
> +
> +static const struct bcr_regs rgmii_regs = {
> +       .cfg_rcgr = 0x6020,
> +       .cmd_rcgr = 0x601C,
> +       .M = 0x6024,
> +       .N = 0x6028,
> +       .D = 0x602C,
> +};
> +
> +static ulong sm8150_clk_set_rate(struct clk *clk, ulong rate)
> +{
> +       struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +       const struct freq_tbl *freq;
> +
> +       switch (clk->id) {
> +       case GCC_QUPV3_WRAP1_S4_CLK: /* UART2 aka debug-uart */
> +               freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
> +               clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
> +                                    freq->pre_div, freq->m, freq->n, freq->src, 16);
> +               return freq->freq;
> +       case GCC_EMAC_RGMII_CLK:
> +               freq = qcom_find_freq(ftbl_gcc_emac_rgmii_clk_src, rate);
> +               clk_rcg_set_rate_mnd(priv->base, &rgmii_regs,
> +                                    freq->pre_div, freq->m, freq->n, freq->src, 8);
> +
> +               return freq->freq;
> +       default:
> +               pr_err("Don't know how to set clk id %ld\n", clk->id);
> +               return -EINVAL;
> +       }
> +}
> +
> +static const struct gate_clk sm8150_clks[] = {
> +       GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK,                0x5200c, 0x00000400),
> +       GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK,                0x5200c, 0x00000800),
> +       GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK,                0x5200c, 0x00001000),
> +       GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK,                0x5200c, 0x00002000),
> +       GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK,                0x5200c, 0x00004000),
> +       GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK,                0x5200c, 0x00008000),
> +       GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK,                0x5200c, 0x00400000),
> +       GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK,                0x5200c, 0x00800000),
> +       GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK,                0x5200c, 0x02000000),
> +       GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK,                0x5200c, 0x04000000),
> +       GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK,                0x5200c, 0x08000000),
> +       GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK,            0x5200c, 0x00000040),
> +       GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK,            0x5200c, 0x00000080),
> +       GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK,            0x5200c, 0x00100000),
> +       GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK,            0x5200c, 0x00200000),
> +       GATE_CLK(GCC_SDCC2_AHB_CLK,                     0x14008, 0x00000001),
> +       GATE_CLK(GCC_SDCC2_APPS_CLK,                    0x14004, 0x00000001),
> +       GATE_CLK(GCC_SDCC4_AHB_CLK,                     0x16008, 0x00000001),
> +       GATE_CLK(GCC_SDCC4_APPS_CLK,                    0x16004, 0x00000001),
> +       GATE_CLK(GCC_UFS_CARD_AHB_CLK,                  0x75010, 0x00000001),
> +       GATE_CLK(GCC_UFS_CARD_AXI_CLK,                  0x7500c, 0x00000001),
> +       GATE_CLK(GCC_UFS_CARD_CLKREF_CLK,               0x8c004, 0x00000001),
> +       GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK,             0x75058, 0x00000001),
> +       GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK,              0x7508c, 0x00000001),
> +       GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK,          0x75018, 0x00000001),
> +       GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK,          0x750a8, 0x00000001),
> +       GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK,          0x75014, 0x00000001),
> +       GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK,          0x75054, 0x00000001),
> +       GATE_CLK(GCC_UFS_MEM_CLKREF_CLK,                0x8c000, 0x00000001),
> +       GATE_CLK(GCC_UFS_PHY_AHB_CLK,                   0x77010, 0x00000001),
> +       GATE_CLK(GCC_UFS_PHY_AXI_CLK,                   0x7700c, 0x00000001),
> +       GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK,              0x77058, 0x00000001),
> +       GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK,               0x7708c, 0x00000001),
> +       GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK,           0x77018, 0x00000001),
> +       GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK,           0x770a8, 0x00000001),
> +       GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK,           0x77014, 0x00000001),
> +       GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK,           0x77054, 0x00000001),
> +       GATE_CLK(GCC_USB30_PRIM_MASTER_CLK,             0x0f00c, 0x00000001),
> +       GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK,          0x0f014, 0x00000001),
> +       GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK,              0x0f010, 0x00000001),
> +       GATE_CLK(GCC_USB30_SEC_MASTER_CLK,              0x1000c, 0x00000001),
> +       GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK,           0x10014, 0x00000001),
> +       GATE_CLK(GCC_USB30_SEC_SLEEP_CLK,               0x10010, 0x00000001),
> +       GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK,              0x8c008, 0x00000001),
> +       GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK,             0x0f04c, 0x00000001),
> +       GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK,         0x0f050, 0x00000001),
> +       GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK,            0x0f054, 0x00000001),
> +       GATE_CLK(GCC_USB3_SEC_CLKREF_CLK,               0x8c028, 0x00000001),
> +       GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK,              0x1004c, 0x00000001),
> +       GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK,             0x10054, 0x00000001),
> +       GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK,          0x10050, 0x00000001),
> +       GATE_CLK(GCC_EMAC_AXI_CLK,                      0x06010, 0x00000001),
> +       GATE_CLK(GCC_EMAC_SLV_AHB_CLK,                  0x06014, 0x00000001),
> +       GATE_CLK(GCC_EMAC_PTP_CLK,                      0x06034, 0x00000001),
> +       GATE_CLK(GCC_EMAC_RGMII_CLK,                    0x06018, 0x00000001),
> +};
> +
> +static int sm8150_clk_enable(struct clk *clk)
> +{
> +       struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> +       switch (clk->id) {
> +       case GCC_EMAC_RGMII_CLK:
> +               clk_enable_gpll0(priv->base, &gpll7_vote_clk);
> +       };
> +
> +       qcom_gate_clk_en(priv, clk->id);
> +
> +       return 0;
> +}
> +
> +static const struct qcom_reset_map sm8150_gcc_resets[] = {
> +       [GCC_EMAC_BCR] = { 0x6000 },
> +       [GCC_GPU_BCR] = { 0x71000 },
> +       [GCC_MMSS_BCR] = { 0xb000 },
> +       [GCC_NPU_BCR] = { 0x4d000 },
> +       [GCC_PCIE_0_BCR] = { 0x6b000 },
> +       [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
> +       [GCC_PCIE_1_BCR] = { 0x8d000 },
> +       [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
> +       [GCC_PCIE_PHY_BCR] = { 0x6f000 },
> +       [GCC_PDM_BCR] = { 0x33000 },
> +       [GCC_PRNG_BCR] = { 0x34000 },
> +       [GCC_QSPI_BCR] = { 0x24008 },
> +       [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
> +       [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
> +       [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
> +       [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
> +       [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
> +       [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
> +       [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
> +       [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
> +       [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
> +       [GCC_SDCC2_BCR] = { 0x14000 },
> +       [GCC_SDCC4_BCR] = { 0x16000 },
> +       [GCC_TSIF_BCR] = { 0x36000 },
> +       [GCC_UFS_CARD_BCR] = { 0x75000 },
> +       [GCC_UFS_PHY_BCR] = { 0x77000 },
> +       [GCC_USB30_PRIM_BCR] = { 0xf000 },
> +       [GCC_USB30_SEC_BCR] = { 0x10000 },
> +       [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
> +};
> +
> +static const struct qcom_power_map sm8150_gcc_power_domains[] = {
> +       [EMAC_GDSC] = { 0x6004 },
> +       [PCIE_0_GDSC] = { 0x6b004 },
> +       [PCIE_1_GDSC] = { 0x8d004 },
> +       [UFS_CARD_GDSC] = { 0x75004 },
> +       [UFS_PHY_GDSC] = { 0x77004 },
> +       [USB30_PRIM_GDSC] = { 0xf004 },
> +       [USB30_SEC_GDSC] = { 0x10004 },
> +};
> +
> +
> +static struct msm_clk_data sm8150_clk_data = {
> +       .resets = sm8150_gcc_resets,
> +       .num_resets = ARRAY_SIZE(sm8150_gcc_resets),
> +       .clks = sm8150_clks,
> +       .num_clks = ARRAY_SIZE(sm8150_clks),
> +       .power_domains = sm8150_gcc_power_domains,
> +       .num_power_domains = ARRAY_SIZE(sm8150_gcc_power_domains),
> +
> +       .enable = sm8150_clk_enable,
> +       .set_rate = sm8150_clk_set_rate,
> +};
> +
> +static const struct udevice_id gcc_sm8150_of_match[] = {
> +       {
> +               .compatible = "qcom,gcc-sm8150",
> +               .data = (ulong)&sm8150_clk_data,
> +       },
> +       { }
> +};
> +
> +U_BOOT_DRIVER(gcc_sm8150) = {
> +       .name           = "gcc_sm8150",
> +       .id             = UCLASS_NOP,
> +       .of_match       = gcc_sm8150_of_match,
> +       .bind           = qcom_cc_bind,
> +       .flags          = DM_FLAG_PRE_RELOC,
> +};
> --
> 2.43.0

Re: [PATCH v2 5/8] clk: qcom: add driver for SM8150 SoC

[Caleb Connolly]

On 06/03/2024 00:53, Volodymyr Babchuk wrote:
> Add clock, reset and power domain driver for SM8150. Driver code is
> based on the similar U-Boot drivers. All constants are taken from the
> corresponding Linux driver.
> 
> This driver supports clock rate setting only for the debug UART and
> RGMII/Ethernet modules, because this is all I can test right now.
> 
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

Thanks for working on this!

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
> 
> ---
> 
> Changes in v2:
>  - Renamed GPLL7_MAIN to just GPLL7 (while I like idea to use Linux
>    naming convention, such rework needs to be done in a separate
>    commit)
>  - Removed unnecessary include
>  - Fixed GDSCR register values for couple of devices
>  - Enable GPLL7 only when RGMII clock is enabled
> 
>  drivers/clk/qcom/Kconfig        |   8 ++
>  drivers/clk/qcom/Makefile       |   1 +
>  drivers/clk/qcom/clock-qcom.h   |   1 +
>  drivers/clk/qcom/clock-sm8150.c | 237 ++++++++++++++++++++++++++++++++
>  4 files changed, 247 insertions(+)
>  create mode 100644 drivers/clk/qcom/clock-sm8150.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 0df0d1881a..18ccf6a45e 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -47,6 +47,14 @@ config CLK_QCOM_SDM845
>  	  on the Snapdragon 845 SoC. This driver supports the clocks
>  	  and resets exposed by the GCC hardware block.
>  
> +config CLK_QCOM_SM8150
> +	bool "Qualcomm SM8150 GCC"
> +	select CLK_QCOM
> +	help
> +	  Say Y here to enable support for the Global Clock Controller
> +	  on the Snapdragon 8150 SoC. This driver supports the clocks
> +	  and resets exposed by the GCC hardware block.
> +
>  endmenu
>  
>  endif
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index cb179fdac5..12c09ba19e 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
>  obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
>  obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
>  obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
> +obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 12a1eaec2b..dd40487e94 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -9,6 +9,7 @@
>  
>  #define CFG_CLK_SRC_CXO   (0 << 8)
>  #define CFG_CLK_SRC_GPLL0 (1 << 8)
> +#define CFG_CLK_SRC_GPLL7 (3 << 8)
>  #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
>  #define CFG_CLK_SRC_MASK  (7 << 8)
>  
> diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c
> new file mode 100644
> index 0000000000..2592eef29b
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-sm8150.c
> @@ -0,0 +1,237 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Clock drivers for Qualcomm SM8150
> + *
> + * Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> + * Copyright (c) 2024 EPAM Systems.
> + *
> + * Based on U-Boot driver for SDM845. Constants are taken from the Linux driver.
> + */
> +
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <asm/io.h>
> +#include <linux/bitops.h>
> +#include <dt-bindings/clock/qcom,gcc-sm8150.h>
> +
> +#include "clock-qcom.h"
> +
> +static struct pll_vote_clk gpll7_vote_clk = {
> +	.status = 0x1a000,
> +	.status_bit = BIT(31),
> +	.ena_vote = 0x52000,
> +	.vote_bit = BIT(7),
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
> +	F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
> +	F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
> +	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> +	F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
> +	F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
> +	F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
> +	F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
> +	F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
> +	F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
> +	F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
> +	F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
> +	F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
> +	F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
> +	F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
> +	F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
> +	{ }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
> +	F(2500000, CFG_CLK_SRC_CXO, 1, 25, 192),
> +	F(5000000, CFG_CLK_SRC_CXO, 1, 25, 96),
> +	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
> +	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
> +	F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
> +	F(125000000, CFG_CLK_SRC_GPLL7, 4, 0, 0),
> +	F(250000000, CFG_CLK_SRC_GPLL7, 2, 0, 0),
> +	{ }
> +};
> +
> +static const struct bcr_regs uart2_regs = {
> +	.cfg_rcgr = 0x1814C,
> +	.cmd_rcgr = 0x18148,
> +	.M = 0x18150,
> +	.N = 0x18154,
> +	.D = 0x18158,
> +};
> +
> +static const struct bcr_regs rgmii_regs = {
> +	.cfg_rcgr = 0x6020,
> +	.cmd_rcgr = 0x601C,
> +	.M = 0x6024,
> +	.N = 0x6028,
> +	.D = 0x602C,
> +};
> +
> +static ulong sm8150_clk_set_rate(struct clk *clk, ulong rate)
> +{
> +	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +	const struct freq_tbl *freq;
> +
> +	switch (clk->id) {
> +	case GCC_QUPV3_WRAP1_S4_CLK: /* UART2 aka debug-uart */
> +		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
> +		clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
> +				     freq->pre_div, freq->m, freq->n, freq->src, 16);
> +		return freq->freq;
> +	case GCC_EMAC_RGMII_CLK:
> +		freq = qcom_find_freq(ftbl_gcc_emac_rgmii_clk_src, rate);
> +		clk_rcg_set_rate_mnd(priv->base, &rgmii_regs,
> +				     freq->pre_div, freq->m, freq->n, freq->src, 8);
> +
> +		return freq->freq;
> +	default:
> +		pr_err("Don't know how to set clk id %ld\n", clk->id);
> +		return -EINVAL;
> +	}
> +}
> +
> +static const struct gate_clk sm8150_clks[] = {
> +	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK,		0x5200c, 0x00000400),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK,		0x5200c, 0x00000800),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK,		0x5200c, 0x00001000),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK,		0x5200c, 0x00002000),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK,		0x5200c, 0x00004000),
> +	GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK,		0x5200c, 0x00008000),
> +	GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK,		0x5200c, 0x00400000),
> +	GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK,		0x5200c, 0x00800000),
> +	GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK,		0x5200c, 0x02000000),
> +	GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK,		0x5200c, 0x04000000),
> +	GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK,		0x5200c, 0x08000000),
> +	GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK,		0x5200c, 0x00000040),
> +	GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK,		0x5200c, 0x00000080),
> +	GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK,		0x5200c, 0x00100000),
> +	GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK,		0x5200c, 0x00200000),
> +	GATE_CLK(GCC_SDCC2_AHB_CLK,			0x14008, 0x00000001),
> +	GATE_CLK(GCC_SDCC2_APPS_CLK,			0x14004, 0x00000001),
> +	GATE_CLK(GCC_SDCC4_AHB_CLK,			0x16008, 0x00000001),
> +	GATE_CLK(GCC_SDCC4_APPS_CLK,			0x16004, 0x00000001),
> +	GATE_CLK(GCC_UFS_CARD_AHB_CLK,			0x75010, 0x00000001),
> +	GATE_CLK(GCC_UFS_CARD_AXI_CLK,			0x7500c, 0x00000001),
> +	GATE_CLK(GCC_UFS_CARD_CLKREF_CLK,		0x8c004, 0x00000001),
> +	GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK,		0x75058, 0x00000001),
> +	GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK,		0x7508c, 0x00000001),
> +	GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK,		0x75018, 0x00000001),
> +	GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK,		0x750a8, 0x00000001),
> +	GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK,		0x75014, 0x00000001),
> +	GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK,		0x75054, 0x00000001),
> +	GATE_CLK(GCC_UFS_MEM_CLKREF_CLK,		0x8c000, 0x00000001),
> +	GATE_CLK(GCC_UFS_PHY_AHB_CLK,			0x77010, 0x00000001),
> +	GATE_CLK(GCC_UFS_PHY_AXI_CLK,			0x7700c, 0x00000001),
> +	GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK,		0x77058, 0x00000001),
> +	GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK,		0x7708c, 0x00000001),
> +	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK,		0x77018, 0x00000001),
> +	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK,		0x770a8, 0x00000001),
> +	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK,		0x77014, 0x00000001),
> +	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK,		0x77054, 0x00000001),
> +	GATE_CLK(GCC_USB30_PRIM_MASTER_CLK,		0x0f00c, 0x00000001),
> +	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK,		0x0f014, 0x00000001),
> +	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK,		0x0f010, 0x00000001),
> +	GATE_CLK(GCC_USB30_SEC_MASTER_CLK,		0x1000c, 0x00000001),
> +	GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK,		0x10014, 0x00000001),
> +	GATE_CLK(GCC_USB30_SEC_SLEEP_CLK,		0x10010, 0x00000001),
> +	GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK,		0x8c008, 0x00000001),
> +	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK,		0x0f04c, 0x00000001),
> +	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK,		0x0f050, 0x00000001),
> +	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK,		0x0f054, 0x00000001),
> +	GATE_CLK(GCC_USB3_SEC_CLKREF_CLK,		0x8c028, 0x00000001),
> +	GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK,		0x1004c, 0x00000001),
> +	GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK,		0x10054, 0x00000001),
> +	GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK,		0x10050, 0x00000001),
> +	GATE_CLK(GCC_EMAC_AXI_CLK,			0x06010, 0x00000001),
> +	GATE_CLK(GCC_EMAC_SLV_AHB_CLK,			0x06014, 0x00000001),
> +	GATE_CLK(GCC_EMAC_PTP_CLK,			0x06034, 0x00000001),
> +	GATE_CLK(GCC_EMAC_RGMII_CLK,			0x06018, 0x00000001),
> +};
> +
> +static int sm8150_clk_enable(struct clk *clk)
> +{
> +	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> +	switch (clk->id) {
> +	case GCC_EMAC_RGMII_CLK:
> +		clk_enable_gpll0(priv->base, &gpll7_vote_clk);
> +	};
> +
> +	qcom_gate_clk_en(priv, clk->id);
> +
> +	return 0;
> +}
> +
> +static const struct qcom_reset_map sm8150_gcc_resets[] = {
> +	[GCC_EMAC_BCR] = { 0x6000 },
> +	[GCC_GPU_BCR] = { 0x71000 },
> +	[GCC_MMSS_BCR] = { 0xb000 },
> +	[GCC_NPU_BCR] = { 0x4d000 },
> +	[GCC_PCIE_0_BCR] = { 0x6b000 },
> +	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
> +	[GCC_PCIE_1_BCR] = { 0x8d000 },
> +	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
> +	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
> +	[GCC_PDM_BCR] = { 0x33000 },
> +	[GCC_PRNG_BCR] = { 0x34000 },
> +	[GCC_QSPI_BCR] = { 0x24008 },
> +	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
> +	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
> +	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
> +	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
> +	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
> +	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
> +	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
> +	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
> +	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
> +	[GCC_SDCC2_BCR] = { 0x14000 },
> +	[GCC_SDCC4_BCR] = { 0x16000 },
> +	[GCC_TSIF_BCR] = { 0x36000 },
> +	[GCC_UFS_CARD_BCR] = { 0x75000 },
> +	[GCC_UFS_PHY_BCR] = { 0x77000 },
> +	[GCC_USB30_PRIM_BCR] = { 0xf000 },
> +	[GCC_USB30_SEC_BCR] = { 0x10000 },
> +	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
> +};
> +
> +static const struct qcom_power_map sm8150_gcc_power_domains[] = {
> +	[EMAC_GDSC] = { 0x6004 },
> +	[PCIE_0_GDSC] = { 0x6b004 },
> +	[PCIE_1_GDSC] = { 0x8d004 },
> +	[UFS_CARD_GDSC] = { 0x75004 },
> +	[UFS_PHY_GDSC] = { 0x77004 },
> +	[USB30_PRIM_GDSC] = { 0xf004 },
> +	[USB30_SEC_GDSC] = { 0x10004 },
> +};
> +
> +
> +static struct msm_clk_data sm8150_clk_data = {
> +	.resets = sm8150_gcc_resets,
> +	.num_resets = ARRAY_SIZE(sm8150_gcc_resets),
> +	.clks = sm8150_clks,
> +	.num_clks = ARRAY_SIZE(sm8150_clks),
> +	.power_domains = sm8150_gcc_power_domains,
> +	.num_power_domains = ARRAY_SIZE(sm8150_gcc_power_domains),
> +
> +	.enable = sm8150_clk_enable,
> +	.set_rate = sm8150_clk_set_rate,
> +};
> +
> +static const struct udevice_id gcc_sm8150_of_match[] = {
> +	{
> +		.compatible = "qcom,gcc-sm8150",
> +		.data = (ulong)&sm8150_clk_data,
> +	},
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(gcc_sm8150) = {
> +	.name		= "gcc_sm8150",
> +	.id		= UCLASS_NOP,
> +	.of_match	= gcc_sm8150_of_match,
> +	.bind		= qcom_cc_bind,
> +	.flags		= DM_FLAG_PRE_RELOC,
> +};

-- 
// Caleb (they/them)

Re: [PATCH v2 5/8] clk: qcom: add driver for SM8150 SoC

[Julius Lehmann]

Sorry to bump this thread, but any chance on getting this patch (5/8 
clk) and (7/8 pinctrl) merged? I do have an SM8150 device myself (Xiaomi 
Mi Pad 5) and would benefit from clk and pinctrl drivers. From the 
reviews it seems not much work would be required.

Kind regards
Julius

[PATCH v2 7/8] pinctrl: qcom: add driver for SM8150 SoC

[Volodymyr Babchuk]

Add pinctrl and GPIO driver for SM8150. Driver code is based on the
similar U-Boot drivers. All constants are taken from the corresponding
Linux driver. This drivers differs from the similar U-Boot drivers,
because SM8150 SoC have different function IDs for the same functions
on different pins.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
---

(no changes since v1)

 drivers/pinctrl/qcom/Kconfig          |   7 +
 drivers/pinctrl/qcom/Makefile         |   1 +
 drivers/pinctrl/qcom/pinctrl-sm8150.c | 589 ++++++++++++++++++++++++++
 3 files changed, 597 insertions(+)
 create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 2fe6398147..290cefca47 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -41,6 +41,13 @@ config PINCTRL_QCOM_SDM845
 	  Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
 	  as well as the associated GPIO driver.
 
+config PINCTRL_QCOM_SM8150
+	bool "Qualcomm SM8150 GCC"
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC,
+	  as well as the associated GPIO driver.
+
 endmenu
 
 endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 6d9aca6d7b..3c7be4a685 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
 obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
 obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
 obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
+obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
new file mode 100644
index 0000000000..a6c14d7254
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c
@@ -0,0 +1,589 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Qualcomm SM8150 pinctrl and GPIO driver
+ *
+ * Volodymyr Babchuk <volodymyr_babchuk@epam.com>
+ * Copyright (c) 2024 EPAM Systems.
+ *
+ * Based on similar U-Boot drivers. Constants were taken from the Linux driver
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define WEST	0x00100000
+#define EAST	0x00500000
+#define NORTH	0x00900000
+#define SOUTH	0x00D00000
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+enum sm8150_functions {
+	msm_mux_adsp_ext,
+	msm_mux_agera_pll,
+	msm_mux_aoss_cti,
+	msm_mux_atest_char,
+	msm_mux_atest_char0,
+	msm_mux_atest_char1,
+	msm_mux_atest_char2,
+	msm_mux_atest_char3,
+	msm_mux_atest_usb1,
+	msm_mux_atest_usb2,
+	msm_mux_atest_usb10,
+	msm_mux_atest_usb11,
+	msm_mux_atest_usb12,
+	msm_mux_atest_usb13,
+	msm_mux_atest_usb20,
+	msm_mux_atest_usb21,
+	msm_mux_atest_usb22,
+	msm_mux_atest_usb23,
+	msm_mux_audio_ref,
+	msm_mux_btfm_slimbus,
+	msm_mux_cam_mclk,
+	msm_mux_cci_async,
+	msm_mux_cci_i2c,
+	msm_mux_cci_timer0,
+	msm_mux_cci_timer1,
+	msm_mux_cci_timer2,
+	msm_mux_cci_timer3,
+	msm_mux_cci_timer4,
+	msm_mux_cri_trng,
+	msm_mux_cri_trng0,
+	msm_mux_cri_trng1,
+	msm_mux_dbg_out,
+	msm_mux_ddr_bist,
+	msm_mux_ddr_pxi0,
+	msm_mux_ddr_pxi1,
+	msm_mux_ddr_pxi2,
+	msm_mux_ddr_pxi3,
+	msm_mux_edp_hot,
+	msm_mux_edp_lcd,
+	msm_mux_emac_phy,
+	msm_mux_emac_pps,
+	msm_mux_gcc_gp1,
+	msm_mux_gcc_gp2,
+	msm_mux_gcc_gp3,
+	msm_mux_gpio,
+	msm_mux_jitter_bist,
+	msm_mux_hs1_mi2s,
+	msm_mux_hs2_mi2s,
+	msm_mux_hs3_mi2s,
+	msm_mux_lpass_slimbus,
+	msm_mux_mdp_vsync,
+	msm_mux_mdp_vsync0,
+	msm_mux_mdp_vsync1,
+	msm_mux_mdp_vsync2,
+	msm_mux_mdp_vsync3,
+	msm_mux_mss_lte,
+	msm_mux_m_voc,
+	msm_mux_nav_pps,
+	msm_mux_pa_indicator,
+	msm_mux_pci_e0,
+	msm_mux_pci_e1,
+	msm_mux_phase_flag,
+	msm_mux_pll_bist,
+	msm_mux_pll_bypassnl,
+	msm_mux_pll_reset,
+	msm_mux_pri_mi2s,
+	msm_mux_pri_mi2s_ws,
+	msm_mux_prng_rosc,
+	msm_mux_qdss,
+	msm_mux_qdss_cti,
+	msm_mux_qlink_enable,
+	msm_mux_qlink_request,
+	msm_mux_qspi0,
+	msm_mux_qspi1,
+	msm_mux_qspi2,
+	msm_mux_qspi3,
+	msm_mux_qspi_clk,
+	msm_mux_qspi_cs,
+	msm_mux_qua_mi2s,
+	msm_mux_qup0,
+	msm_mux_qup1,
+	msm_mux_qup2,
+	msm_mux_qup3,
+	msm_mux_qup4,
+	msm_mux_qup5,
+	msm_mux_qup6,
+	msm_mux_qup7,
+	msm_mux_qup8,
+	msm_mux_qup9,
+	msm_mux_qup10,
+	msm_mux_qup11,
+	msm_mux_qup12,
+	msm_mux_qup13,
+	msm_mux_qup14,
+	msm_mux_qup15,
+	msm_mux_qup16,
+	msm_mux_qup17,
+	msm_mux_qup18,
+	msm_mux_qup19,
+	msm_mux_qup_l4,
+	msm_mux_qup_l5,
+	msm_mux_qup_l6,
+	msm_mux_rgmii,
+	msm_mux_sdc4,
+	msm_mux_sd_write,
+	msm_mux_sec_mi2s,
+	msm_mux_spkr_i2s,
+	msm_mux_sp_cmu,
+	msm_mux_ter_mi2s,
+	msm_mux_tgu_ch0,
+	msm_mux_tgu_ch2,
+	msm_mux_tgu_ch1,
+	msm_mux_tgu_ch3,
+	msm_mux_tsense_pwm1,
+	msm_mux_tsense_pwm2,
+	msm_mux_tsif1,
+	msm_mux_tsif2,
+	msm_mux_uim1,
+	msm_mux_uim2,
+	msm_mux_uim_batt,
+	msm_mux_usb2phy_ac,
+	msm_mux_usb_phy,
+	msm_mux_vfr_1,
+	msm_mux_vsense_trigger,
+	msm_mux_wlan1_adc1,
+	msm_mux_wlan1_adc0,
+	msm_mux_wlan2_adc1,
+	msm_mux_wlan2_adc0,
+	msm_mux_wmss_reset,
+	msm_mux__,
+};
+
+#define MSM_PIN_FUNCTION(fname)				\
+	[msm_mux_##fname] = {#fname, msm_mux_##fname}
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	MSM_PIN_FUNCTION(adsp_ext),
+	MSM_PIN_FUNCTION(agera_pll),
+	MSM_PIN_FUNCTION(aoss_cti),
+	MSM_PIN_FUNCTION(ddr_pxi2),
+	MSM_PIN_FUNCTION(atest_char),
+	MSM_PIN_FUNCTION(atest_char0),
+	MSM_PIN_FUNCTION(atest_char1),
+	MSM_PIN_FUNCTION(atest_char2),
+	MSM_PIN_FUNCTION(atest_char3),
+	MSM_PIN_FUNCTION(audio_ref),
+	MSM_PIN_FUNCTION(atest_usb1),
+	MSM_PIN_FUNCTION(atest_usb2),
+	MSM_PIN_FUNCTION(atest_usb10),
+	MSM_PIN_FUNCTION(atest_usb11),
+	MSM_PIN_FUNCTION(atest_usb12),
+	MSM_PIN_FUNCTION(atest_usb13),
+	MSM_PIN_FUNCTION(atest_usb20),
+	MSM_PIN_FUNCTION(atest_usb21),
+	MSM_PIN_FUNCTION(atest_usb22),
+	MSM_PIN_FUNCTION(atest_usb23),
+	MSM_PIN_FUNCTION(btfm_slimbus),
+	MSM_PIN_FUNCTION(cam_mclk),
+	MSM_PIN_FUNCTION(cci_async),
+	MSM_PIN_FUNCTION(cci_i2c),
+	MSM_PIN_FUNCTION(cci_timer0),
+	MSM_PIN_FUNCTION(cci_timer1),
+	MSM_PIN_FUNCTION(cci_timer2),
+	MSM_PIN_FUNCTION(cci_timer3),
+	MSM_PIN_FUNCTION(cci_timer4),
+	MSM_PIN_FUNCTION(cri_trng),
+	MSM_PIN_FUNCTION(cri_trng0),
+	MSM_PIN_FUNCTION(cri_trng1),
+	MSM_PIN_FUNCTION(dbg_out),
+	MSM_PIN_FUNCTION(ddr_bist),
+	MSM_PIN_FUNCTION(ddr_pxi0),
+	MSM_PIN_FUNCTION(ddr_pxi1),
+	MSM_PIN_FUNCTION(ddr_pxi3),
+	MSM_PIN_FUNCTION(edp_hot),
+	MSM_PIN_FUNCTION(edp_lcd),
+	MSM_PIN_FUNCTION(emac_phy),
+	MSM_PIN_FUNCTION(emac_pps),
+	MSM_PIN_FUNCTION(gcc_gp1),
+	MSM_PIN_FUNCTION(gcc_gp2),
+	MSM_PIN_FUNCTION(gcc_gp3),
+	MSM_PIN_FUNCTION(gpio),
+	MSM_PIN_FUNCTION(hs1_mi2s),
+	MSM_PIN_FUNCTION(hs2_mi2s),
+	MSM_PIN_FUNCTION(hs3_mi2s),
+	MSM_PIN_FUNCTION(jitter_bist),
+	MSM_PIN_FUNCTION(lpass_slimbus),
+	MSM_PIN_FUNCTION(mdp_vsync),
+	MSM_PIN_FUNCTION(mdp_vsync0),
+	MSM_PIN_FUNCTION(mdp_vsync1),
+	MSM_PIN_FUNCTION(mdp_vsync2),
+	MSM_PIN_FUNCTION(mdp_vsync3),
+	MSM_PIN_FUNCTION(mss_lte),
+	MSM_PIN_FUNCTION(m_voc),
+	MSM_PIN_FUNCTION(nav_pps),
+	MSM_PIN_FUNCTION(pa_indicator),
+	MSM_PIN_FUNCTION(pci_e0),
+	MSM_PIN_FUNCTION(phase_flag),
+	MSM_PIN_FUNCTION(pll_bypassnl),
+	MSM_PIN_FUNCTION(pll_bist),
+	MSM_PIN_FUNCTION(pci_e1),
+	MSM_PIN_FUNCTION(pll_reset),
+	MSM_PIN_FUNCTION(pri_mi2s),
+	MSM_PIN_FUNCTION(pri_mi2s_ws),
+	MSM_PIN_FUNCTION(prng_rosc),
+	MSM_PIN_FUNCTION(qdss),
+	MSM_PIN_FUNCTION(qdss_cti),
+	MSM_PIN_FUNCTION(qlink_request),
+	MSM_PIN_FUNCTION(qlink_enable),
+	MSM_PIN_FUNCTION(qspi0),
+	MSM_PIN_FUNCTION(qspi1),
+	MSM_PIN_FUNCTION(qspi2),
+	MSM_PIN_FUNCTION(qspi3),
+	MSM_PIN_FUNCTION(qspi_clk),
+	MSM_PIN_FUNCTION(qspi_cs),
+	MSM_PIN_FUNCTION(qua_mi2s),
+	MSM_PIN_FUNCTION(qup0),
+	MSM_PIN_FUNCTION(qup1),
+	MSM_PIN_FUNCTION(qup2),
+	MSM_PIN_FUNCTION(qup3),
+	MSM_PIN_FUNCTION(qup4),
+	MSM_PIN_FUNCTION(qup5),
+	MSM_PIN_FUNCTION(qup6),
+	MSM_PIN_FUNCTION(qup7),
+	MSM_PIN_FUNCTION(qup8),
+	MSM_PIN_FUNCTION(qup9),
+	MSM_PIN_FUNCTION(qup10),
+	MSM_PIN_FUNCTION(qup11),
+	MSM_PIN_FUNCTION(qup12),
+	MSM_PIN_FUNCTION(qup13),
+	MSM_PIN_FUNCTION(qup14),
+	MSM_PIN_FUNCTION(qup15),
+	MSM_PIN_FUNCTION(qup16),
+	MSM_PIN_FUNCTION(qup17),
+	MSM_PIN_FUNCTION(qup18),
+	MSM_PIN_FUNCTION(qup19),
+	MSM_PIN_FUNCTION(qup_l4),
+	MSM_PIN_FUNCTION(qup_l5),
+	MSM_PIN_FUNCTION(qup_l6),
+	MSM_PIN_FUNCTION(rgmii),
+	MSM_PIN_FUNCTION(sdc4),
+	MSM_PIN_FUNCTION(sd_write),
+	MSM_PIN_FUNCTION(sec_mi2s),
+	MSM_PIN_FUNCTION(spkr_i2s),
+	MSM_PIN_FUNCTION(sp_cmu),
+	MSM_PIN_FUNCTION(ter_mi2s),
+	MSM_PIN_FUNCTION(tgu_ch0),
+	MSM_PIN_FUNCTION(tgu_ch1),
+	MSM_PIN_FUNCTION(tgu_ch2),
+	MSM_PIN_FUNCTION(tgu_ch3),
+	MSM_PIN_FUNCTION(tsense_pwm1),
+	MSM_PIN_FUNCTION(tsense_pwm2),
+	MSM_PIN_FUNCTION(tsif1),
+	MSM_PIN_FUNCTION(tsif2),
+	MSM_PIN_FUNCTION(uim1),
+	MSM_PIN_FUNCTION(uim2),
+	MSM_PIN_FUNCTION(uim_batt),
+	MSM_PIN_FUNCTION(usb2phy_ac),
+	MSM_PIN_FUNCTION(usb_phy),
+	MSM_PIN_FUNCTION(vfr_1),
+	MSM_PIN_FUNCTION(vsense_trigger),
+	MSM_PIN_FUNCTION(wlan1_adc0),
+	MSM_PIN_FUNCTION(wlan1_adc1),
+	MSM_PIN_FUNCTION(wlan2_adc0),
+	MSM_PIN_FUNCTION(wlan2_adc1),
+	MSM_PIN_FUNCTION(wmss_reset),
+};
+
+static const unsigned int sm8150_pin_offsets[] = {
+	[0]   = SOUTH, [1]   = SOUTH, [2]   = SOUTH, [3]   = SOUTH,
+	[4]   = SOUTH, [5]   = SOUTH, [6]   = SOUTH, [7]   = SOUTH,
+	[8]   = NORTH, [9]   = NORTH, [10]  = NORTH, [11]  = NORTH,
+	[12]  = NORTH, [13]  = NORTH, [14]  = NORTH, [15]  = NORTH,
+	[16]  = NORTH, [17]  = NORTH, [18]  = NORTH, [19]  = NORTH,
+	[20]  = NORTH, [21]  = EAST,  [22]  = EAST,  [23]  = EAST,
+	[24]  = EAST,  [25]  = EAST,  [26]  = EAST,  [27]  = EAST,
+	[28]  = EAST,  [29]  = EAST,  [30]  = EAST,  [31]  = NORTH,
+	[32]  = NORTH, [33]  = NORTH, [34]  = NORTH, [35]  = NORTH,
+	[36]  = NORTH, [37]  = NORTH, [38]  = SOUTH, [39]  = NORTH,
+	[40]  = NORTH, [41]  = NORTH, [42]  = NORTH, [43]  = EAST,
+	[44]  = EAST,  [45]  = EAST,  [46]  = EAST,  [47]  = EAST,
+	[48]  = EAST,  [49]  = EAST,  [50]  = EAST,  [51]  = SOUTH,
+	[52]  = SOUTH, [53]  = SOUTH, [54]  = SOUTH, [55]  = SOUTH,
+	[56]  = SOUTH, [57]  = SOUTH, [58]  = SOUTH, [59]  = SOUTH,
+	[60]  = SOUTH, [61]  = SOUTH, [62]  = SOUTH, [63]  = SOUTH,
+	[64]  = SOUTH, [65]  = SOUTH, [66]  = SOUTH, [67]  = SOUTH,
+	[68]  = SOUTH, [69]  = SOUTH, [70]  = SOUTH, [71]  = SOUTH,
+	[72]  = SOUTH, [73]  = SOUTH, [74]  = SOUTH, [75]  = SOUTH,
+	[76]  = SOUTH, [77]  = SOUTH, [78]  = SOUTH, [79]  = SOUTH,
+	[80]  = SOUTH, [81]  = SOUTH, [82]  = SOUTH, [83]  = NORTH,
+	[84]  = NORTH, [85]  = NORTH, [86]  = NORTH, [87]  = EAST,
+	[88]  = NORTH, [89]  = NORTH, [90]  = NORTH, [91]  = NORTH,
+	[92]  = NORTH, [93]  = NORTH, [94]  = NORTH, [95]  = NORTH,
+	[96]  = NORTH, [97]  = NORTH, [98]  = SOUTH, [99]  = SOUTH,
+	[100] = SOUTH, [101] = SOUTH, [102] = NORTH, [103] = NORTH,
+	[104] = NORTH, [105] = WEST,  [106] = WEST,  [107] = WEST,
+	[108] = WEST,  [109] = WEST,  [110] = WEST,  [111] = WEST,
+	[112] = WEST,  [113] = WEST,  [114] = SOUTH, [115] = SOUTH,
+	[116] = SOUTH, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH,
+	[120] = SOUTH, [121] = SOUTH, [122] = SOUTH, [123] = SOUTH,
+	[124] = SOUTH, [125] = WEST,  [126] = SOUTH, [127] = SOUTH,
+	[128] = SOUTH, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH,
+	[132] = SOUTH, [133] = SOUTH, [134] = SOUTH, [135] = SOUTH,
+	[136] = SOUTH, [137] = SOUTH, [138] = SOUTH, [139] = SOUTH,
+	[140] = SOUTH, [141] = SOUTH, [142] = SOUTH, [143] = SOUTH,
+	[144] = SOUTH, [145] = SOUTH, [146] = SOUTH, [147] = SOUTH,
+	[148] = SOUTH, [149] = SOUTH, [150] = SOUTH, [151] = SOUTH,
+	[152] = SOUTH, [153] = SOUTH, [154] = SOUTH, [155] = WEST,
+	[156] = WEST,  [157] = WEST,  [158] = WEST,  [159] = WEST,
+	[160] = WEST,  [161] = WEST,  [162] = WEST,  [163] = WEST,
+	[164] = WEST,  [165] = WEST,  [166] = WEST,  [167] = WEST,
+	[168] = WEST,  [169] = NORTH, [170] = NORTH, [171] = NORTH
+};
+
+typedef unsigned int msm_pin_function[10];
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
+	[id] = {        msm_mux_gpio, /* gpio mode */	\
+			msm_mux_##f1,			\
+			msm_mux_##f2,			\
+			msm_mux_##f3,			\
+			msm_mux_##f4,			\
+			msm_mux_##f5,			\
+			msm_mux_##f6,			\
+			msm_mux_##f7,			\
+			msm_mux_##f8,			\
+			msm_mux_##f9			\
+	}
+
+static const msm_pin_function sm8150_pin_functions[] = {
+	PINGROUP(0, qup0,  _, _, _, _, _, _, _, _),
+	PINGROUP(1, qup0, _, _, _, _, _, _, _, _),
+	PINGROUP(2, qup0, _, _, _, _, _, _, _, _),
+	PINGROUP(3, qup0, _, _, _, _, _, _, _, _),
+	PINGROUP(4, qup6, rgmii, _, _, _, _, _, _, _),
+	PINGROUP(5, qup6, rgmii, _, _, _, _, _, _, _),
+	PINGROUP(6, qup6, rgmii, qup_l6, _, _, _, _, _, _),
+	PINGROUP(7, qup6, rgmii, qup_l5, _, _, _, _, _, _),
+	PINGROUP(8, mdp_vsync, _, _, _, _, _, _, _, _),
+	PINGROUP(9, mdp_vsync, edp_lcd, qup10, _, _, _, _, _, _),
+	PINGROUP(10, mdp_vsync, m_voc, edp_hot, qup10, _, _, _, _, _),
+	PINGROUP(11, qup10, _, _, _, _, _, _, _, _),
+	PINGROUP(12, qup10, _, _, _, _, _, _, _, _),
+	PINGROUP(13, cam_mclk, qdss, _, _, _, _, _, _, _),
+	PINGROUP(14, cam_mclk, qdss, _, _, _, _, _, _, _),
+	PINGROUP(15, cam_mclk, qdss, _, _, _, _, _, _, _),
+	PINGROUP(16, cam_mclk, qdss, _, _, _, _, _, _, _),
+	PINGROUP(17, cci_i2c, qdss, _, _, _, _, _, _, _),
+	PINGROUP(18, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
+	PINGROUP(19, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
+	PINGROUP(20, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
+	PINGROUP(21, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _),
+	PINGROUP(22, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _),
+	PINGROUP(23, cci_timer2, qup18, qdss, _, _, _, _, _, _),
+	PINGROUP(24, cci_timer3, cci_async, qup18, qdss, _, _, _, _, _),
+	PINGROUP(25, cci_timer4, cci_async, qup18, qdss, _, _, _, _, _),
+	PINGROUP(26, cci_async, qup18, qdss, _, _, _, _, _, _),
+	PINGROUP(27, qup15, _, qdss, _, _, _, _, _, _),
+	PINGROUP(28, qup15, qdss, _, _, _, _, _, _, _),
+	PINGROUP(29, qup15, qdss, _, _, _, _, _, _, _),
+	PINGROUP(30, qup15, qdss, _, _, _, _, _, _, _),
+	PINGROUP(31, cci_i2c, qdss, _, _, _, _, _, _, _),
+	PINGROUP(32, cci_i2c, qdss, _, _, _, _, _, _, _),
+	PINGROUP(33, cci_i2c, qup_l5, qdss, _, _, _, _, _, _),
+	PINGROUP(34, cci_i2c, qup_l6, _, _, _, _, _, _, _),
+	PINGROUP(35, pci_e0, _, _, _, _, _, _, _, _),
+	PINGROUP(36, pci_e0, _, _, _, _, _, _, _, _),
+	PINGROUP(37, qup_l4, agera_pll, _, _, _, _, _, _, _),
+	PINGROUP(38, usb_phy, _, _, _, _, _, _, _, _),
+	PINGROUP(39, qup9, qdss, _, _, _, _, _, _, _),
+	PINGROUP(40, qup9, qdss, _, _, _, _, _, _, _),
+	PINGROUP(41, qup9, qdss, _, _, _, _, _, _, _),
+	PINGROUP(42, qup9, qdss, _, _, _, _, _, _, _),
+	PINGROUP(43, qup13, _, _, _, _, _, _, _, _),
+	PINGROUP(44, qup13, _, _, _, _, _, _, _, _),
+	PINGROUP(45, qup13, qdss_cti, _, _, _, _, _, _, _),
+	PINGROUP(46, qup13, qdss_cti, _, _, _, _, _, _, _),
+	PINGROUP(47, qup14, qdss, _, _, _, _, _, _, _),
+	PINGROUP(48, qup14, qdss, _, _, _, _, _, _, _),
+	PINGROUP(49, qup14, _, qdss_cti, _, _, _, _, _, _),
+	PINGROUP(50, qup14, qdss_cti, _, _, _, _, _, _, _),
+	PINGROUP(51, qup4, _, _, _, _, _, _, _, _),
+	PINGROUP(52, qup4, _, _, _, _, _, _, _, _),
+	PINGROUP(53, qup4, _, _, _, _, _, _, _, _),
+	PINGROUP(54, qup4, _, _, _, _, _, _, _, _),
+	PINGROUP(55, qup17, qup19, phase_flag, _, _, _, _, _, _),
+	PINGROUP(56, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
+	PINGROUP(57, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
+	PINGROUP(58, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
+	PINGROUP(59, rgmii, qup_l4, phase_flag, _, atest_char, _, _, _, _),
+	PINGROUP(60, _, nav_pps, nav_pps, atest_usb2, _, _, _, _, _),
+	PINGROUP(61, qlink_request, _, _, _, _, _, _, _, _),
+	PINGROUP(62, qlink_enable, _, _, _, _, _, _, _, _),
+	PINGROUP(63, wmss_reset, atest_usb23, _, _, _, _, _, _, _),
+	PINGROUP(64, _, phase_flag, _, _, _, _, _, _, _),
+	PINGROUP(65, _, _, _, _, _, _, _, _, _),
+	PINGROUP(66, _, _, _, _, _, _, _, _, _),
+	PINGROUP(67, _, _, _, _, _, _, _, _, _),
+	PINGROUP(68, _, pa_indicator, phase_flag, _, _, _, _, _, _),
+	PINGROUP(69, mss_lte, _, _, _, _, _, _, _, _),
+	PINGROUP(70, mss_lte, _, _, _, _, _, _, _, _),
+	PINGROUP(71, _, _, _, _, _, _, _, _, _),
+	PINGROUP(72, _, _, _, _, _, _, _, _, _),
+	PINGROUP(73, _, _, _, _, _, _, _, _, _),
+	PINGROUP(74, _, _, _, _, _, _, _, _, _),
+	PINGROUP(75, _, _, _, _, _, _, _, _, _),
+	PINGROUP(76, _, _, _, nav_pps, nav_pps, phase_flag, _, _, _),
+	PINGROUP(77, _, _, _, nav_pps, nav_pps, _, _, _, _),
+	PINGROUP(78, _, _, _, _, _, _, _, _, _),
+	PINGROUP(79, _, _, phase_flag, _, _, _, _, _, _),
+	PINGROUP(80, _, _, phase_flag, _, _, _, _, _, _),
+	PINGROUP(81, _, _, _, nav_pps, nav_pps, qup_l4, mdp_vsync, emac_pps, _),
+	PINGROUP(82, _, _, _, nav_pps, nav_pps, qup_l5, mdp_vsync, _, _),
+	PINGROUP(83, qup12, qup16, _, qdss, _, _, _, _, _),
+	PINGROUP(84, qup12, qup16, _, _, _, _, _, _, _),
+	PINGROUP(85, qup12, qup16, _, _, _, _, _, _, _),
+	PINGROUP(86, qup12, qup16, _, _, _, _, _, _, _),
+	PINGROUP(87, _, _, _, _, _, _, _, _, _),
+	PINGROUP(88, tsif1, qup8, qspi_cs, tgu_ch3, _, _, _, _, _),
+	PINGROUP(89, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2,
+		 mdp_vsync3, tgu_ch0, _),
+	PINGROUP(90, tsif1, qup8, qspi1, sdc4, phase_flag, tgu_ch1, _, _,
+		 wlan1_adc1),
+	PINGROUP(91, tsif1, qup8, qspi2, sdc4, vfr_1, phase_flag, tgu_ch2,
+		 _, _),
+	PINGROUP(92, tsif2, qup11, qspi_clk, sdc4, phase_flag, _, wlan2_adc1,
+		 _, _),
+	PINGROUP(93, tsif2, qup11, qspi3, sdc4, phase_flag, _, wlan2_adc0,
+		 _, _),
+	PINGROUP(94, tsif2, qup11, qspi_cs, sdc4, phase_flag, _, _, _, _),
+	PINGROUP(95, tsif2, qup11, sdc4, qup_l4, _, _, _, _, _),
+	PINGROUP(96, tsif2, qup_l5, phase_flag, _, _, _, _, _, _),
+	PINGROUP(97, sd_write, tsif1, qup_l6, _, _, _, _, _, _),
+	PINGROUP(98, qup7, ddr_bist, ddr_pxi3, _, _, _, _, _, _),
+	PINGROUP(99, qup7, ddr_bist, atest_usb13, ddr_pxi1, _, _, _, _, _),
+	PINGROUP(100, qup7, pll_bypassnl, atest_usb12, ddr_pxi1, _, _, _, _, _),
+	PINGROUP(101, qup7, pll_reset, ddr_pxi3, _, _, _, _, _, _),
+	PINGROUP(102, pci_e1, _, _, _, _, _, _, _, _),
+	PINGROUP(103, pci_e1, _, _, _, _, _, _, _, _),
+	PINGROUP(104, _, _, _, _, _, _, _, _, _),
+	PINGROUP(105, uim2, _, _, _, _, _, _, _, _),
+	PINGROUP(106, uim2, _, _, _, _, _, _, _, _),
+	PINGROUP(107, uim2, _, _, _, _, _, _, _, _),
+	PINGROUP(108, uim2, _, _, _, _, _, _, _, _),
+	PINGROUP(109, uim1, _, _, _, _, _, _, _, _),
+	PINGROUP(110, uim1, _, _, _, _, _, _, _, _),
+	PINGROUP(111, uim1, _, _, _, _, _, _, _, _),
+	PINGROUP(112, uim1, _, _, _, _, _, _, _, _),
+	PINGROUP(113, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _),
+	PINGROUP(114, qup1, rgmii, phase_flag, _, _, _, _, _, _),
+	PINGROUP(115, qup1, rgmii, phase_flag, adsp_ext, _, _, _, _, _),
+	PINGROUP(116, qup1, rgmii, phase_flag, _, _, _, _, _, _),
+	PINGROUP(117, qup1, rgmii, phase_flag, _, qdss, _, _, _, _),
+	PINGROUP(118, rgmii, phase_flag, _, qdss, _, _, _, _, _),
+	PINGROUP(119, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
+	PINGROUP(120, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
+	PINGROUP(121, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
+	PINGROUP(122, qup5, rgmii, phase_flag, _, _, _, _, _, _),
+	PINGROUP(123, usb2phy_ac, qup_l6, atest_usb22, _, _, _, _, _, _),
+	PINGROUP(124, emac_phy, _, _, _, _, _, _, _, _),
+	PINGROUP(125, hs3_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(126, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
+	PINGROUP(127, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
+	PINGROUP(128, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
+	PINGROUP(129, sec_mi2s, qup2, jitter_bist, atest_usb21, _, _, _, _, _),
+	PINGROUP(130, sec_mi2s, pll_bist, atest_usb20, atest_char0,
+		 _, _, _, _, _),
+	PINGROUP(131, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
+	PINGROUP(132, ter_mi2s, _, qdss, _, _, _, _, _, _),
+	PINGROUP(133, ter_mi2s, qdss, atest_char1, _, _, _, _, _, _),
+	PINGROUP(134, ter_mi2s, qdss, atest_char2, _, _, _, _, _, _),
+	PINGROUP(135, ter_mi2s, atest_char3, _, _, _, _, _, _, _),
+	PINGROUP(136, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _),
+	PINGROUP(137, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _),
+	PINGROUP(138, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _),
+	PINGROUP(139, qua_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(140, qua_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(141, qua_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(142, qua_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(143, pri_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(144, pri_mi2s, qup3, phase_flag, _, ddr_pxi0, _, _, _, _),
+	PINGROUP(145, pri_mi2s_ws, qup3, phase_flag, ddr_bist, _,
+		 vsense_trigger, atest_usb1, ddr_pxi0, _),
+	PINGROUP(146, pri_mi2s, qup3, ddr_bist, atest_usb11, ddr_pxi2,
+		 _, _, _, _),
+	PINGROUP(147, pri_mi2s, qup3, dbg_out, atest_usb10, ddr_pxi2,
+		 _, _, _, _),
+	PINGROUP(148, spkr_i2s, audio_ref, _, _, _, _, _, _, _),
+	PINGROUP(149, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
+	PINGROUP(150, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2,
+		 _, _, _, _, _),
+	PINGROUP(151, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
+	PINGROUP(152, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
+	PINGROUP(153, btfm_slimbus, _, _, _, _, _, _, _, _),
+	PINGROUP(154, btfm_slimbus, _, _, _, _, _, _, _, _),
+	PINGROUP(155, hs1_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(156, hs1_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(157, hs1_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(158, hs1_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(159, hs1_mi2s, cri_trng0, _, _, _, _, _, _, _),
+	PINGROUP(160, hs2_mi2s, cri_trng1, _, _, _, _, _, _, _),
+	PINGROUP(161, hs2_mi2s, cri_trng, _, _, _, _, _, _, _),
+	PINGROUP(162, hs2_mi2s, sp_cmu, _, _, _, _, _, _, _),
+	PINGROUP(163, hs2_mi2s, prng_rosc, _, _, _, _, _, _, _),
+	PINGROUP(164, hs2_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(165, hs3_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(166, hs3_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(167, hs3_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(168, hs3_mi2s, _, _, _, _, _, _, _, _),
+	PINGROUP(169, _, _, _, _, _, _, _, _, _),
+	PINGROUP(170, _, _, _, _, _, _, _, _, _),
+	PINGROUP(171, _, _, _, _, _, _, _, _, _),
+	PINGROUP(172, _, _, _, _, _, _, _, _, _),
+	PINGROUP(173, _, _, _, _, _, _, _, _, _),
+	PINGROUP(174, _, _, _, _, _, _, _, _, _),
+};
+
+static const char *sm8150_get_function_name(struct udevice *dev,
+					    unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sm8150_get_pin_name(struct udevice *dev,
+				       unsigned int selector)
+{
+	snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+	return pin_name;
+}
+
+static unsigned int sm8150_get_function_mux(unsigned int pin,
+					    unsigned int selector)
+{
+	unsigned int i;
+	const msm_pin_function *func = sm8150_pin_functions + pin;
+
+	for (i = 0; i < 10; i++)
+		if ((*func)[i] == selector)
+			return i;
+
+	pr_err("Can't find requested function for pin %u pin\n", pin);
+	return 0;
+}
+
+static struct msm_pinctrl_data sm8150_data = {
+	.pin_data = {
+		.pin_offsets = sm8150_pin_offsets,
+		.pin_count = ARRAY_SIZE(sm8150_pin_offsets),
+	},
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = sm8150_get_function_name,
+	.get_function_mux = sm8150_get_function_mux,
+	.get_pin_name = sm8150_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{ .compatible = "qcom,sm8150-pinctrl", .data = (ulong)&sm8150_data },
+	{ /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_sm8150) = {
+	.name		= "pinctrl_sm8150",
+	.id		= UCLASS_NOP,
+	.of_match	= msm_pinctrl_ids,
+	.ops		= &msm_pinctrl_ops,
+	.bind		= msm_pinctrl_bind,
+};
-- 
2.43.0

Re: [PATCH v2 7/8] pinctrl: qcom: add driver for SM8150 SoC

[Caleb Connolly]

On 06/03/2024 00:53, Volodymyr Babchuk wrote:
> Add pinctrl and GPIO driver for SM8150. Driver code is based on the
> similar U-Boot drivers. All constants are taken from the corresponding
> Linux driver. This drivers differs from the similar U-Boot drivers,
> because SM8150 SoC have different function IDs for the same functions
> on different pins.
> 
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
With the tile offsets fixed as mentioned on the other patch

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
> 
> (no changes since v1)
> 
>  drivers/pinctrl/qcom/Kconfig          |   7 +
>  drivers/pinctrl/qcom/Makefile         |   1 +
>  drivers/pinctrl/qcom/pinctrl-sm8150.c | 589 ++++++++++++++++++++++++++
>  3 files changed, 597 insertions(+)
>  create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8150.c
> 
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 2fe6398147..290cefca47 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -41,6 +41,13 @@ config PINCTRL_QCOM_SDM845
>  	  Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
>  	  as well as the associated GPIO driver.
>  
> +config PINCTRL_QCOM_SM8150
> +	bool "Qualcomm SM8150 GCC"
> +	select PINCTRL_QCOM
> +	help
> +	  Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC,
> +	  as well as the associated GPIO driver.
> +
>  endmenu
>  
>  endif
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index 6d9aca6d7b..3c7be4a685 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
>  obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
>  obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
>  obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
> +obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
> new file mode 100644
> index 0000000000..a6c14d7254
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c
> @@ -0,0 +1,589 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Qualcomm SM8150 pinctrl and GPIO driver
> + *
> + * Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> + * Copyright (c) 2024 EPAM Systems.
> + *
> + * Based on similar U-Boot drivers. Constants were taken from the Linux driver
> + */
> +
> +#include <dm.h>
> +
> +#include "pinctrl-qcom.h"
> +
> +#define WEST	0x00100000
> +#define EAST	0x00500000
> +#define NORTH	0x00900000
> +#define SOUTH	0x00D00000
> +
> +#define MAX_PIN_NAME_LEN 32
> +static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
> +
> +enum sm8150_functions {
> +	msm_mux_adsp_ext,
> +	msm_mux_agera_pll,
> +	msm_mux_aoss_cti,
> +	msm_mux_atest_char,
> +	msm_mux_atest_char0,
> +	msm_mux_atest_char1,
> +	msm_mux_atest_char2,
> +	msm_mux_atest_char3,
> +	msm_mux_atest_usb1,
> +	msm_mux_atest_usb2,
> +	msm_mux_atest_usb10,
> +	msm_mux_atest_usb11,
> +	msm_mux_atest_usb12,
> +	msm_mux_atest_usb13,
> +	msm_mux_atest_usb20,
> +	msm_mux_atest_usb21,
> +	msm_mux_atest_usb22,
> +	msm_mux_atest_usb23,
> +	msm_mux_audio_ref,
> +	msm_mux_btfm_slimbus,
> +	msm_mux_cam_mclk,
> +	msm_mux_cci_async,
> +	msm_mux_cci_i2c,
> +	msm_mux_cci_timer0,
> +	msm_mux_cci_timer1,
> +	msm_mux_cci_timer2,
> +	msm_mux_cci_timer3,
> +	msm_mux_cci_timer4,
> +	msm_mux_cri_trng,
> +	msm_mux_cri_trng0,
> +	msm_mux_cri_trng1,
> +	msm_mux_dbg_out,
> +	msm_mux_ddr_bist,
> +	msm_mux_ddr_pxi0,
> +	msm_mux_ddr_pxi1,
> +	msm_mux_ddr_pxi2,
> +	msm_mux_ddr_pxi3,
> +	msm_mux_edp_hot,
> +	msm_mux_edp_lcd,
> +	msm_mux_emac_phy,
> +	msm_mux_emac_pps,
> +	msm_mux_gcc_gp1,
> +	msm_mux_gcc_gp2,
> +	msm_mux_gcc_gp3,
> +	msm_mux_gpio,
> +	msm_mux_jitter_bist,
> +	msm_mux_hs1_mi2s,
> +	msm_mux_hs2_mi2s,
> +	msm_mux_hs3_mi2s,
> +	msm_mux_lpass_slimbus,
> +	msm_mux_mdp_vsync,
> +	msm_mux_mdp_vsync0,
> +	msm_mux_mdp_vsync1,
> +	msm_mux_mdp_vsync2,
> +	msm_mux_mdp_vsync3,
> +	msm_mux_mss_lte,
> +	msm_mux_m_voc,
> +	msm_mux_nav_pps,
> +	msm_mux_pa_indicator,
> +	msm_mux_pci_e0,
> +	msm_mux_pci_e1,
> +	msm_mux_phase_flag,
> +	msm_mux_pll_bist,
> +	msm_mux_pll_bypassnl,
> +	msm_mux_pll_reset,
> +	msm_mux_pri_mi2s,
> +	msm_mux_pri_mi2s_ws,
> +	msm_mux_prng_rosc,
> +	msm_mux_qdss,
> +	msm_mux_qdss_cti,
> +	msm_mux_qlink_enable,
> +	msm_mux_qlink_request,
> +	msm_mux_qspi0,
> +	msm_mux_qspi1,
> +	msm_mux_qspi2,
> +	msm_mux_qspi3,
> +	msm_mux_qspi_clk,
> +	msm_mux_qspi_cs,
> +	msm_mux_qua_mi2s,
> +	msm_mux_qup0,
> +	msm_mux_qup1,
> +	msm_mux_qup2,
> +	msm_mux_qup3,
> +	msm_mux_qup4,
> +	msm_mux_qup5,
> +	msm_mux_qup6,
> +	msm_mux_qup7,
> +	msm_mux_qup8,
> +	msm_mux_qup9,
> +	msm_mux_qup10,
> +	msm_mux_qup11,
> +	msm_mux_qup12,
> +	msm_mux_qup13,
> +	msm_mux_qup14,
> +	msm_mux_qup15,
> +	msm_mux_qup16,
> +	msm_mux_qup17,
> +	msm_mux_qup18,
> +	msm_mux_qup19,
> +	msm_mux_qup_l4,
> +	msm_mux_qup_l5,
> +	msm_mux_qup_l6,
> +	msm_mux_rgmii,
> +	msm_mux_sdc4,
> +	msm_mux_sd_write,
> +	msm_mux_sec_mi2s,
> +	msm_mux_spkr_i2s,
> +	msm_mux_sp_cmu,
> +	msm_mux_ter_mi2s,
> +	msm_mux_tgu_ch0,
> +	msm_mux_tgu_ch2,
> +	msm_mux_tgu_ch1,
> +	msm_mux_tgu_ch3,
> +	msm_mux_tsense_pwm1,
> +	msm_mux_tsense_pwm2,
> +	msm_mux_tsif1,
> +	msm_mux_tsif2,
> +	msm_mux_uim1,
> +	msm_mux_uim2,
> +	msm_mux_uim_batt,
> +	msm_mux_usb2phy_ac,
> +	msm_mux_usb_phy,
> +	msm_mux_vfr_1,
> +	msm_mux_vsense_trigger,
> +	msm_mux_wlan1_adc1,
> +	msm_mux_wlan1_adc0,
> +	msm_mux_wlan2_adc1,
> +	msm_mux_wlan2_adc0,
> +	msm_mux_wmss_reset,
> +	msm_mux__,
> +};
> +
> +#define MSM_PIN_FUNCTION(fname)				\
> +	[msm_mux_##fname] = {#fname, msm_mux_##fname}
> +
> +static const struct pinctrl_function msm_pinctrl_functions[] = {
> +	MSM_PIN_FUNCTION(adsp_ext),
> +	MSM_PIN_FUNCTION(agera_pll),
> +	MSM_PIN_FUNCTION(aoss_cti),
> +	MSM_PIN_FUNCTION(ddr_pxi2),
> +	MSM_PIN_FUNCTION(atest_char),
> +	MSM_PIN_FUNCTION(atest_char0),
> +	MSM_PIN_FUNCTION(atest_char1),
> +	MSM_PIN_FUNCTION(atest_char2),
> +	MSM_PIN_FUNCTION(atest_char3),
> +	MSM_PIN_FUNCTION(audio_ref),
> +	MSM_PIN_FUNCTION(atest_usb1),
> +	MSM_PIN_FUNCTION(atest_usb2),
> +	MSM_PIN_FUNCTION(atest_usb10),
> +	MSM_PIN_FUNCTION(atest_usb11),
> +	MSM_PIN_FUNCTION(atest_usb12),
> +	MSM_PIN_FUNCTION(atest_usb13),
> +	MSM_PIN_FUNCTION(atest_usb20),
> +	MSM_PIN_FUNCTION(atest_usb21),
> +	MSM_PIN_FUNCTION(atest_usb22),
> +	MSM_PIN_FUNCTION(atest_usb23),
> +	MSM_PIN_FUNCTION(btfm_slimbus),
> +	MSM_PIN_FUNCTION(cam_mclk),
> +	MSM_PIN_FUNCTION(cci_async),
> +	MSM_PIN_FUNCTION(cci_i2c),
> +	MSM_PIN_FUNCTION(cci_timer0),
> +	MSM_PIN_FUNCTION(cci_timer1),
> +	MSM_PIN_FUNCTION(cci_timer2),
> +	MSM_PIN_FUNCTION(cci_timer3),
> +	MSM_PIN_FUNCTION(cci_timer4),
> +	MSM_PIN_FUNCTION(cri_trng),
> +	MSM_PIN_FUNCTION(cri_trng0),
> +	MSM_PIN_FUNCTION(cri_trng1),
> +	MSM_PIN_FUNCTION(dbg_out),
> +	MSM_PIN_FUNCTION(ddr_bist),
> +	MSM_PIN_FUNCTION(ddr_pxi0),
> +	MSM_PIN_FUNCTION(ddr_pxi1),
> +	MSM_PIN_FUNCTION(ddr_pxi3),
> +	MSM_PIN_FUNCTION(edp_hot),
> +	MSM_PIN_FUNCTION(edp_lcd),
> +	MSM_PIN_FUNCTION(emac_phy),
> +	MSM_PIN_FUNCTION(emac_pps),
> +	MSM_PIN_FUNCTION(gcc_gp1),
> +	MSM_PIN_FUNCTION(gcc_gp2),
> +	MSM_PIN_FUNCTION(gcc_gp3),
> +	MSM_PIN_FUNCTION(gpio),
> +	MSM_PIN_FUNCTION(hs1_mi2s),
> +	MSM_PIN_FUNCTION(hs2_mi2s),
> +	MSM_PIN_FUNCTION(hs3_mi2s),
> +	MSM_PIN_FUNCTION(jitter_bist),
> +	MSM_PIN_FUNCTION(lpass_slimbus),
> +	MSM_PIN_FUNCTION(mdp_vsync),
> +	MSM_PIN_FUNCTION(mdp_vsync0),
> +	MSM_PIN_FUNCTION(mdp_vsync1),
> +	MSM_PIN_FUNCTION(mdp_vsync2),
> +	MSM_PIN_FUNCTION(mdp_vsync3),
> +	MSM_PIN_FUNCTION(mss_lte),
> +	MSM_PIN_FUNCTION(m_voc),
> +	MSM_PIN_FUNCTION(nav_pps),
> +	MSM_PIN_FUNCTION(pa_indicator),
> +	MSM_PIN_FUNCTION(pci_e0),
> +	MSM_PIN_FUNCTION(phase_flag),
> +	MSM_PIN_FUNCTION(pll_bypassnl),
> +	MSM_PIN_FUNCTION(pll_bist),
> +	MSM_PIN_FUNCTION(pci_e1),
> +	MSM_PIN_FUNCTION(pll_reset),
> +	MSM_PIN_FUNCTION(pri_mi2s),
> +	MSM_PIN_FUNCTION(pri_mi2s_ws),
> +	MSM_PIN_FUNCTION(prng_rosc),
> +	MSM_PIN_FUNCTION(qdss),
> +	MSM_PIN_FUNCTION(qdss_cti),
> +	MSM_PIN_FUNCTION(qlink_request),
> +	MSM_PIN_FUNCTION(qlink_enable),
> +	MSM_PIN_FUNCTION(qspi0),
> +	MSM_PIN_FUNCTION(qspi1),
> +	MSM_PIN_FUNCTION(qspi2),
> +	MSM_PIN_FUNCTION(qspi3),
> +	MSM_PIN_FUNCTION(qspi_clk),
> +	MSM_PIN_FUNCTION(qspi_cs),
> +	MSM_PIN_FUNCTION(qua_mi2s),
> +	MSM_PIN_FUNCTION(qup0),
> +	MSM_PIN_FUNCTION(qup1),
> +	MSM_PIN_FUNCTION(qup2),
> +	MSM_PIN_FUNCTION(qup3),
> +	MSM_PIN_FUNCTION(qup4),
> +	MSM_PIN_FUNCTION(qup5),
> +	MSM_PIN_FUNCTION(qup6),
> +	MSM_PIN_FUNCTION(qup7),
> +	MSM_PIN_FUNCTION(qup8),
> +	MSM_PIN_FUNCTION(qup9),
> +	MSM_PIN_FUNCTION(qup10),
> +	MSM_PIN_FUNCTION(qup11),
> +	MSM_PIN_FUNCTION(qup12),
> +	MSM_PIN_FUNCTION(qup13),
> +	MSM_PIN_FUNCTION(qup14),
> +	MSM_PIN_FUNCTION(qup15),
> +	MSM_PIN_FUNCTION(qup16),
> +	MSM_PIN_FUNCTION(qup17),
> +	MSM_PIN_FUNCTION(qup18),
> +	MSM_PIN_FUNCTION(qup19),
> +	MSM_PIN_FUNCTION(qup_l4),
> +	MSM_PIN_FUNCTION(qup_l5),
> +	MSM_PIN_FUNCTION(qup_l6),
> +	MSM_PIN_FUNCTION(rgmii),
> +	MSM_PIN_FUNCTION(sdc4),
> +	MSM_PIN_FUNCTION(sd_write),
> +	MSM_PIN_FUNCTION(sec_mi2s),
> +	MSM_PIN_FUNCTION(spkr_i2s),
> +	MSM_PIN_FUNCTION(sp_cmu),
> +	MSM_PIN_FUNCTION(ter_mi2s),
> +	MSM_PIN_FUNCTION(tgu_ch0),
> +	MSM_PIN_FUNCTION(tgu_ch1),
> +	MSM_PIN_FUNCTION(tgu_ch2),
> +	MSM_PIN_FUNCTION(tgu_ch3),
> +	MSM_PIN_FUNCTION(tsense_pwm1),
> +	MSM_PIN_FUNCTION(tsense_pwm2),
> +	MSM_PIN_FUNCTION(tsif1),
> +	MSM_PIN_FUNCTION(tsif2),
> +	MSM_PIN_FUNCTION(uim1),
> +	MSM_PIN_FUNCTION(uim2),
> +	MSM_PIN_FUNCTION(uim_batt),
> +	MSM_PIN_FUNCTION(usb2phy_ac),
> +	MSM_PIN_FUNCTION(usb_phy),
> +	MSM_PIN_FUNCTION(vfr_1),
> +	MSM_PIN_FUNCTION(vsense_trigger),
> +	MSM_PIN_FUNCTION(wlan1_adc0),
> +	MSM_PIN_FUNCTION(wlan1_adc1),
> +	MSM_PIN_FUNCTION(wlan2_adc0),
> +	MSM_PIN_FUNCTION(wlan2_adc1),
> +	MSM_PIN_FUNCTION(wmss_reset),
> +};
> +
> +static const unsigned int sm8150_pin_offsets[] = {
> +	[0]   = SOUTH, [1]   = SOUTH, [2]   = SOUTH, [3]   = SOUTH,
> +	[4]   = SOUTH, [5]   = SOUTH, [6]   = SOUTH, [7]   = SOUTH,
> +	[8]   = NORTH, [9]   = NORTH, [10]  = NORTH, [11]  = NORTH,
> +	[12]  = NORTH, [13]  = NORTH, [14]  = NORTH, [15]  = NORTH,
> +	[16]  = NORTH, [17]  = NORTH, [18]  = NORTH, [19]  = NORTH,
> +	[20]  = NORTH, [21]  = EAST,  [22]  = EAST,  [23]  = EAST,
> +	[24]  = EAST,  [25]  = EAST,  [26]  = EAST,  [27]  = EAST,
> +	[28]  = EAST,  [29]  = EAST,  [30]  = EAST,  [31]  = NORTH,
> +	[32]  = NORTH, [33]  = NORTH, [34]  = NORTH, [35]  = NORTH,
> +	[36]  = NORTH, [37]  = NORTH, [38]  = SOUTH, [39]  = NORTH,
> +	[40]  = NORTH, [41]  = NORTH, [42]  = NORTH, [43]  = EAST,
> +	[44]  = EAST,  [45]  = EAST,  [46]  = EAST,  [47]  = EAST,
> +	[48]  = EAST,  [49]  = EAST,  [50]  = EAST,  [51]  = SOUTH,
> +	[52]  = SOUTH, [53]  = SOUTH, [54]  = SOUTH, [55]  = SOUTH,
> +	[56]  = SOUTH, [57]  = SOUTH, [58]  = SOUTH, [59]  = SOUTH,
> +	[60]  = SOUTH, [61]  = SOUTH, [62]  = SOUTH, [63]  = SOUTH,
> +	[64]  = SOUTH, [65]  = SOUTH, [66]  = SOUTH, [67]  = SOUTH,
> +	[68]  = SOUTH, [69]  = SOUTH, [70]  = SOUTH, [71]  = SOUTH,
> +	[72]  = SOUTH, [73]  = SOUTH, [74]  = SOUTH, [75]  = SOUTH,
> +	[76]  = SOUTH, [77]  = SOUTH, [78]  = SOUTH, [79]  = SOUTH,
> +	[80]  = SOUTH, [81]  = SOUTH, [82]  = SOUTH, [83]  = NORTH,
> +	[84]  = NORTH, [85]  = NORTH, [86]  = NORTH, [87]  = EAST,
> +	[88]  = NORTH, [89]  = NORTH, [90]  = NORTH, [91]  = NORTH,
> +	[92]  = NORTH, [93]  = NORTH, [94]  = NORTH, [95]  = NORTH,
> +	[96]  = NORTH, [97]  = NORTH, [98]  = SOUTH, [99]  = SOUTH,
> +	[100] = SOUTH, [101] = SOUTH, [102] = NORTH, [103] = NORTH,
> +	[104] = NORTH, [105] = WEST,  [106] = WEST,  [107] = WEST,
> +	[108] = WEST,  [109] = WEST,  [110] = WEST,  [111] = WEST,
> +	[112] = WEST,  [113] = WEST,  [114] = SOUTH, [115] = SOUTH,
> +	[116] = SOUTH, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH,
> +	[120] = SOUTH, [121] = SOUTH, [122] = SOUTH, [123] = SOUTH,
> +	[124] = SOUTH, [125] = WEST,  [126] = SOUTH, [127] = SOUTH,
> +	[128] = SOUTH, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH,
> +	[132] = SOUTH, [133] = SOUTH, [134] = SOUTH, [135] = SOUTH,
> +	[136] = SOUTH, [137] = SOUTH, [138] = SOUTH, [139] = SOUTH,
> +	[140] = SOUTH, [141] = SOUTH, [142] = SOUTH, [143] = SOUTH,
> +	[144] = SOUTH, [145] = SOUTH, [146] = SOUTH, [147] = SOUTH,
> +	[148] = SOUTH, [149] = SOUTH, [150] = SOUTH, [151] = SOUTH,
> +	[152] = SOUTH, [153] = SOUTH, [154] = SOUTH, [155] = WEST,
> +	[156] = WEST,  [157] = WEST,  [158] = WEST,  [159] = WEST,
> +	[160] = WEST,  [161] = WEST,  [162] = WEST,  [163] = WEST,
> +	[164] = WEST,  [165] = WEST,  [166] = WEST,  [167] = WEST,
> +	[168] = WEST,  [169] = NORTH, [170] = NORTH, [171] = NORTH
> +};
> +
> +typedef unsigned int msm_pin_function[10];
> +
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
> +	[id] = {        msm_mux_gpio, /* gpio mode */	\
> +			msm_mux_##f1,			\
> +			msm_mux_##f2,			\
> +			msm_mux_##f3,			\
> +			msm_mux_##f4,			\
> +			msm_mux_##f5,			\
> +			msm_mux_##f6,			\
> +			msm_mux_##f7,			\
> +			msm_mux_##f8,			\
> +			msm_mux_##f9			\
> +	}
> +
> +static const msm_pin_function sm8150_pin_functions[] = {
> +	PINGROUP(0, qup0,  _, _, _, _, _, _, _, _),
> +	PINGROUP(1, qup0, _, _, _, _, _, _, _, _),
> +	PINGROUP(2, qup0, _, _, _, _, _, _, _, _),
> +	PINGROUP(3, qup0, _, _, _, _, _, _, _, _),
> +	PINGROUP(4, qup6, rgmii, _, _, _, _, _, _, _),
> +	PINGROUP(5, qup6, rgmii, _, _, _, _, _, _, _),
> +	PINGROUP(6, qup6, rgmii, qup_l6, _, _, _, _, _, _),
> +	PINGROUP(7, qup6, rgmii, qup_l5, _, _, _, _, _, _),
> +	PINGROUP(8, mdp_vsync, _, _, _, _, _, _, _, _),
> +	PINGROUP(9, mdp_vsync, edp_lcd, qup10, _, _, _, _, _, _),
> +	PINGROUP(10, mdp_vsync, m_voc, edp_hot, qup10, _, _, _, _, _),
> +	PINGROUP(11, qup10, _, _, _, _, _, _, _, _),
> +	PINGROUP(12, qup10, _, _, _, _, _, _, _, _),
> +	PINGROUP(13, cam_mclk, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(14, cam_mclk, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(15, cam_mclk, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(16, cam_mclk, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(17, cci_i2c, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(18, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
> +	PINGROUP(19, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
> +	PINGROUP(20, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
> +	PINGROUP(21, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _),
> +	PINGROUP(22, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _),
> +	PINGROUP(23, cci_timer2, qup18, qdss, _, _, _, _, _, _),
> +	PINGROUP(24, cci_timer3, cci_async, qup18, qdss, _, _, _, _, _),
> +	PINGROUP(25, cci_timer4, cci_async, qup18, qdss, _, _, _, _, _),
> +	PINGROUP(26, cci_async, qup18, qdss, _, _, _, _, _, _),
> +	PINGROUP(27, qup15, _, qdss, _, _, _, _, _, _),
> +	PINGROUP(28, qup15, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(29, qup15, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(30, qup15, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(31, cci_i2c, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(32, cci_i2c, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(33, cci_i2c, qup_l5, qdss, _, _, _, _, _, _),
> +	PINGROUP(34, cci_i2c, qup_l6, _, _, _, _, _, _, _),
> +	PINGROUP(35, pci_e0, _, _, _, _, _, _, _, _),
> +	PINGROUP(36, pci_e0, _, _, _, _, _, _, _, _),
> +	PINGROUP(37, qup_l4, agera_pll, _, _, _, _, _, _, _),
> +	PINGROUP(38, usb_phy, _, _, _, _, _, _, _, _),
> +	PINGROUP(39, qup9, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(40, qup9, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(41, qup9, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(42, qup9, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(43, qup13, _, _, _, _, _, _, _, _),
> +	PINGROUP(44, qup13, _, _, _, _, _, _, _, _),
> +	PINGROUP(45, qup13, qdss_cti, _, _, _, _, _, _, _),
> +	PINGROUP(46, qup13, qdss_cti, _, _, _, _, _, _, _),
> +	PINGROUP(47, qup14, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(48, qup14, qdss, _, _, _, _, _, _, _),
> +	PINGROUP(49, qup14, _, qdss_cti, _, _, _, _, _, _),
> +	PINGROUP(50, qup14, qdss_cti, _, _, _, _, _, _, _),
> +	PINGROUP(51, qup4, _, _, _, _, _, _, _, _),
> +	PINGROUP(52, qup4, _, _, _, _, _, _, _, _),
> +	PINGROUP(53, qup4, _, _, _, _, _, _, _, _),
> +	PINGROUP(54, qup4, _, _, _, _, _, _, _, _),
> +	PINGROUP(55, qup17, qup19, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(56, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
> +	PINGROUP(57, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
> +	PINGROUP(58, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
> +	PINGROUP(59, rgmii, qup_l4, phase_flag, _, atest_char, _, _, _, _),
> +	PINGROUP(60, _, nav_pps, nav_pps, atest_usb2, _, _, _, _, _),
> +	PINGROUP(61, qlink_request, _, _, _, _, _, _, _, _),
> +	PINGROUP(62, qlink_enable, _, _, _, _, _, _, _, _),
> +	PINGROUP(63, wmss_reset, atest_usb23, _, _, _, _, _, _, _),
> +	PINGROUP(64, _, phase_flag, _, _, _, _, _, _, _),
> +	PINGROUP(65, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(66, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(67, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(68, _, pa_indicator, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(69, mss_lte, _, _, _, _, _, _, _, _),
> +	PINGROUP(70, mss_lte, _, _, _, _, _, _, _, _),
> +	PINGROUP(71, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(72, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(73, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(74, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(75, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(76, _, _, _, nav_pps, nav_pps, phase_flag, _, _, _),
> +	PINGROUP(77, _, _, _, nav_pps, nav_pps, _, _, _, _),
> +	PINGROUP(78, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(79, _, _, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(80, _, _, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(81, _, _, _, nav_pps, nav_pps, qup_l4, mdp_vsync, emac_pps, _),
> +	PINGROUP(82, _, _, _, nav_pps, nav_pps, qup_l5, mdp_vsync, _, _),
> +	PINGROUP(83, qup12, qup16, _, qdss, _, _, _, _, _),
> +	PINGROUP(84, qup12, qup16, _, _, _, _, _, _, _),
> +	PINGROUP(85, qup12, qup16, _, _, _, _, _, _, _),
> +	PINGROUP(86, qup12, qup16, _, _, _, _, _, _, _),
> +	PINGROUP(87, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(88, tsif1, qup8, qspi_cs, tgu_ch3, _, _, _, _, _),
> +	PINGROUP(89, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2,
> +		 mdp_vsync3, tgu_ch0, _),
> +	PINGROUP(90, tsif1, qup8, qspi1, sdc4, phase_flag, tgu_ch1, _, _,
> +		 wlan1_adc1),
> +	PINGROUP(91, tsif1, qup8, qspi2, sdc4, vfr_1, phase_flag, tgu_ch2,
> +		 _, _),
> +	PINGROUP(92, tsif2, qup11, qspi_clk, sdc4, phase_flag, _, wlan2_adc1,
> +		 _, _),
> +	PINGROUP(93, tsif2, qup11, qspi3, sdc4, phase_flag, _, wlan2_adc0,
> +		 _, _),
> +	PINGROUP(94, tsif2, qup11, qspi_cs, sdc4, phase_flag, _, _, _, _),
> +	PINGROUP(95, tsif2, qup11, sdc4, qup_l4, _, _, _, _, _),
> +	PINGROUP(96, tsif2, qup_l5, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(97, sd_write, tsif1, qup_l6, _, _, _, _, _, _),
> +	PINGROUP(98, qup7, ddr_bist, ddr_pxi3, _, _, _, _, _, _),
> +	PINGROUP(99, qup7, ddr_bist, atest_usb13, ddr_pxi1, _, _, _, _, _),
> +	PINGROUP(100, qup7, pll_bypassnl, atest_usb12, ddr_pxi1, _, _, _, _, _),
> +	PINGROUP(101, qup7, pll_reset, ddr_pxi3, _, _, _, _, _, _),
> +	PINGROUP(102, pci_e1, _, _, _, _, _, _, _, _),
> +	PINGROUP(103, pci_e1, _, _, _, _, _, _, _, _),
> +	PINGROUP(104, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(105, uim2, _, _, _, _, _, _, _, _),
> +	PINGROUP(106, uim2, _, _, _, _, _, _, _, _),
> +	PINGROUP(107, uim2, _, _, _, _, _, _, _, _),
> +	PINGROUP(108, uim2, _, _, _, _, _, _, _, _),
> +	PINGROUP(109, uim1, _, _, _, _, _, _, _, _),
> +	PINGROUP(110, uim1, _, _, _, _, _, _, _, _),
> +	PINGROUP(111, uim1, _, _, _, _, _, _, _, _),
> +	PINGROUP(112, uim1, _, _, _, _, _, _, _, _),
> +	PINGROUP(113, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _),
> +	PINGROUP(114, qup1, rgmii, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(115, qup1, rgmii, phase_flag, adsp_ext, _, _, _, _, _),
> +	PINGROUP(116, qup1, rgmii, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(117, qup1, rgmii, phase_flag, _, qdss, _, _, _, _),
> +	PINGROUP(118, rgmii, phase_flag, _, qdss, _, _, _, _, _),
> +	PINGROUP(119, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
> +	PINGROUP(120, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
> +	PINGROUP(121, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
> +	PINGROUP(122, qup5, rgmii, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(123, usb2phy_ac, qup_l6, atest_usb22, _, _, _, _, _, _),
> +	PINGROUP(124, emac_phy, _, _, _, _, _, _, _, _),
> +	PINGROUP(125, hs3_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(126, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(127, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(128, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
> +	PINGROUP(129, sec_mi2s, qup2, jitter_bist, atest_usb21, _, _, _, _, _),
> +	PINGROUP(130, sec_mi2s, pll_bist, atest_usb20, atest_char0,
> +		 _, _, _, _, _),
> +	PINGROUP(131, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
> +	PINGROUP(132, ter_mi2s, _, qdss, _, _, _, _, _, _),
> +	PINGROUP(133, ter_mi2s, qdss, atest_char1, _, _, _, _, _, _),
> +	PINGROUP(134, ter_mi2s, qdss, atest_char2, _, _, _, _, _, _),
> +	PINGROUP(135, ter_mi2s, atest_char3, _, _, _, _, _, _, _),
> +	PINGROUP(136, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _),
> +	PINGROUP(137, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _),
> +	PINGROUP(138, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _),
> +	PINGROUP(139, qua_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(140, qua_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(141, qua_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(142, qua_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(143, pri_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(144, pri_mi2s, qup3, phase_flag, _, ddr_pxi0, _, _, _, _),
> +	PINGROUP(145, pri_mi2s_ws, qup3, phase_flag, ddr_bist, _,
> +		 vsense_trigger, atest_usb1, ddr_pxi0, _),
> +	PINGROUP(146, pri_mi2s, qup3, ddr_bist, atest_usb11, ddr_pxi2,
> +		 _, _, _, _),
> +	PINGROUP(147, pri_mi2s, qup3, dbg_out, atest_usb10, ddr_pxi2,
> +		 _, _, _, _),
> +	PINGROUP(148, spkr_i2s, audio_ref, _, _, _, _, _, _, _),
> +	PINGROUP(149, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
> +	PINGROUP(150, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2,
> +		 _, _, _, _, _),
> +	PINGROUP(151, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
> +	PINGROUP(152, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
> +	PINGROUP(153, btfm_slimbus, _, _, _, _, _, _, _, _),
> +	PINGROUP(154, btfm_slimbus, _, _, _, _, _, _, _, _),
> +	PINGROUP(155, hs1_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(156, hs1_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(157, hs1_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(158, hs1_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(159, hs1_mi2s, cri_trng0, _, _, _, _, _, _, _),
> +	PINGROUP(160, hs2_mi2s, cri_trng1, _, _, _, _, _, _, _),
> +	PINGROUP(161, hs2_mi2s, cri_trng, _, _, _, _, _, _, _),
> +	PINGROUP(162, hs2_mi2s, sp_cmu, _, _, _, _, _, _, _),
> +	PINGROUP(163, hs2_mi2s, prng_rosc, _, _, _, _, _, _, _),
> +	PINGROUP(164, hs2_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(165, hs3_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(166, hs3_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(167, hs3_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(168, hs3_mi2s, _, _, _, _, _, _, _, _),
> +	PINGROUP(169, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(170, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(171, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(172, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(173, _, _, _, _, _, _, _, _, _),
> +	PINGROUP(174, _, _, _, _, _, _, _, _, _),
> +};
> +
> +static const char *sm8150_get_function_name(struct udevice *dev,
> +					    unsigned int selector)
> +{
> +	return msm_pinctrl_functions[selector].name;
> +}
> +
> +static const char *sm8150_get_pin_name(struct udevice *dev,
> +				       unsigned int selector)
> +{
> +	snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
> +	return pin_name;
> +}
> +
> +static unsigned int sm8150_get_function_mux(unsigned int pin,
> +					    unsigned int selector)
> +{
> +	unsigned int i;
> +	const msm_pin_function *func = sm8150_pin_functions + pin;
> +
> +	for (i = 0; i < 10; i++)
> +		if ((*func)[i] == selector)
> +			return i;
> +
> +	pr_err("Can't find requested function for pin %u pin\n", pin);
> +	return 0;
> +}
> +
> +static struct msm_pinctrl_data sm8150_data = {
> +	.pin_data = {
> +		.pin_offsets = sm8150_pin_offsets,
> +		.pin_count = ARRAY_SIZE(sm8150_pin_offsets),
> +	},
> +	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
> +	.get_function_name = sm8150_get_function_name,
> +	.get_function_mux = sm8150_get_function_mux,
> +	.get_pin_name = sm8150_get_pin_name,
> +};
> +
> +static const struct udevice_id msm_pinctrl_ids[] = {
> +	{ .compatible = "qcom,sm8150-pinctrl", .data = (ulong)&sm8150_data },
> +	{ /* Sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_sm8150) = {
> +	.name		= "pinctrl_sm8150",
> +	.id		= UCLASS_NOP,
> +	.of_match	= msm_pinctrl_ids,
> +	.ops		= &msm_pinctrl_ops,
> +	.bind		= msm_pinctrl_bind,
> +};

-- 
// Caleb (they/them)

[PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Volodymyr Babchuk]

SA8155P Automotive Development Platform is Qualcomm SA8155-based board
for developers. The nice thing that it has unlocked loaders with test
keys support, which means that U-Boot for this platform can be
launched at earlier stages.

This patch adds basic board support with only serial port and
networking operation. I am using U-Boot to ease up Xen porting onto
this board, so I am mostly interesting in booting U-Boot in EL2. But
more conventional setup with Android boot image is supported as well.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

---

Changes in v2:
 - Rebased onto qcom-next branch
 - Removed unnecessary files thanks to generic qualcomm board support
 - Enabled CONFIG_REMAKE_ELF (this removes one extra step in the
   readme)

 arch/arm/dts/sa8155p-adp-u-boot.dtsi   | 30 +++++++++
 board/qualcomm/sa8155p-adp/MAINTAINERS |  5 ++
 configs/sa8155p_adp_defconfig          | 35 +++++++++++
 doc/board/qualcomm/index.rst           |  1 +
 doc/board/qualcomm/sa8155p-adp.rst     | 87 ++++++++++++++++++++++++++
 5 files changed, 158 insertions(+)
 create mode 100644 arch/arm/dts/sa8155p-adp-u-boot.dtsi
 create mode 100644 board/qualcomm/sa8155p-adp/MAINTAINERS
 create mode 100644 configs/sa8155p_adp_defconfig
 create mode 100644 doc/board/qualcomm/sa8155p-adp.rst

diff --git a/arch/arm/dts/sa8155p-adp-u-boot.dtsi b/arch/arm/dts/sa8155p-adp-u-boot.dtsi
new file mode 100644
index 0000000000..ffbf0933c7
--- /dev/null
+++ b/arch/arm/dts/sa8155p-adp-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Qualcomm SA8155P-ADP device tree fixups for U-BOot
+ *
+ * Volodymyr Babchuk <volodymyr_babchuk@epam.com>
+ * Copyright (c) 2024 EPAM Systems.
+ */
+
+/ {
+	/* Populate memory node with actual memory configuration */
+	memory@80000000 {
+		reg = <0x00 0x80000000 0x00 0x39900000>,
+		<0x02 0x0        0x1  0x7fd00000>,
+		<0x00 0xC0000000 0x1  0x40000000>;
+	};
+};
+
+&ethernet {
+	/* Ethernet driver tries to find reset by name */
+	reset-names = "emac";
+};
+
+&tlmm {
+	/* U-Boot pinctrl driver does not understand multiple tiles */
+	reg = <0x0 0x03000000 0x0 0x1000000>;
+	/delete-property/ reg-names;
+
+	/* U-Boot ethernet driver wants to drive reset as GPIO */
+	/delete-node/ phy-reset-pins;
+};
diff --git a/board/qualcomm/sa8155p-adp/MAINTAINERS b/board/qualcomm/sa8155p-adp/MAINTAINERS
new file mode 100644
index 0000000000..03fac84f51
--- /dev/null
+++ b/board/qualcomm/sa8155p-adp/MAINTAINERS
@@ -0,0 +1,5 @@
+Qualcomm SA8155P Automotive Development Platform
+M:	Volodymyr Babchuk <volodymyr_babchuk@epam.com>
+S:	Maintained
+F:	board/qualcomm/sa8155p-adp/
+F:	configs/sa8155p-adp_defconfig
diff --git a/configs/sa8155p_adp_defconfig b/configs/sa8155p_adp_defconfig
new file mode 100644
index 0000000000..b6969767f8
--- /dev/null
+++ b/configs/sa8155p_adp_defconfig
@@ -0,0 +1,35 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=19000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_TEXT_BASE=0x85710000
+CONFIG_DEFAULT_DEVICE_TREE="qcom/sa8155p-adp"
+CONFIG_IDENT_STRING="\nQualcomm SA8155P-ADP"
+CONFIG_SYS_LOAD_ADDR=0x85710000
+CONFIG_REMAKE_ELF=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CBSIZE=512
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_CLK_QCOM_SM8150=y
+CONFIG_MSM_GPIO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_QCOM=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_QCOM_SM8150=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MSM_GENI_SERIAL=y
+CONFIG_SPMI_MSM=y
+CONFIG_LMB_MAX_REGIONS=64
diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
index 4955274a39..268218b05f 100644
--- a/doc/board/qualcomm/index.rst
+++ b/doc/board/qualcomm/index.rst
@@ -7,5 +7,6 @@ Qualcomm
    :maxdepth: 2
 
    dragonboard410c
+   sa8155p-adp
    board
    debugging
diff --git a/doc/board/qualcomm/sa8155p-adp.rst b/doc/board/qualcomm/sa8155p-adp.rst
new file mode 100644
index 0000000000..66db512b52
--- /dev/null
+++ b/doc/board/qualcomm/sa8155p-adp.rst
@@ -0,0 +1,87 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+.. sectionauthor:: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
+
+SA8155P Automotive Development Platform
+=======================================
+
+About
+-----
+This document describes the information about SA8155P Automotive
+Development Platform aka SA8155P-ADP.
+
+Currently U-Boot can be booted either as Android boot image, or in EL2
+mode, instead of hypervisor image. In the latter case it is possible
+to use U-Boot to either boot Linux with KVM support or to boot Xen
+Hypervisor on this board.
+
+Supported HW modules
+^^^^^^^^^^^^^^^^^^^^
+Port for this board is in early development state. Right now U-Boot
+supports serial console and networking. No USB/fastboot or UFS support
+yet. So it is not possible to save environment variables as
+well. Nevertheless this is enough for development as user can download
+all required images via TFTP.
+
+Installation
+------------
+Build
+^^^^^
+Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
+
+	$ export CROSS_COMPILE=<aarch64 toolchain prefix>
+	$ make sa8155p_adp_defconfig
+	$ make
+
+This will build ``u-boot.bin`` in the configured output directory.
+
+Boot in EL1 mode instead of Android boot image
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Create a dummy ramdisk image:::
+
+	$ echo "This is not a ramdisk" > ramdisk.img
+
+Compress u-boot binary:::
+
+	$ gzip -c u-boot.bin > u-boot.bin.gz
+
+Append DTB again (binary we use already have DTB embedded in, but
+Android boot image format requires another DTB at the end of the
+archive):::
+
+	$ cat u-boot.bin.gz u-boot.dtb > u-boot.bin.gz-dtb
+
+Now we've got everything to build android boot image:::
+
+	$ mkbootimg --kernel u-boot.bin.gz-dtb \
+	--ramdisk ramdisk.img --pagesize 4096 \
+	--base 0x80000000 -o boot.img
+
+Finally you can flash new boot image with fastboot:::
+
+	$ fastboot flash boot boot.img
+
+Or just boot U-Boot without flashing anything:::
+
+	$ fastboot boot boot.img
+
+Boot in EL2 mode instead of Qualcomm's hypervisor stub
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+This approach ensures that U-Boot is booted in EL2 and it is possible
+to run virtualization software (like Xen or KVM) on the board. You
+must understand that this approach breaks Qualcomm's boot chain. You
+will not be able to call all subsequent loaders, so you will not be
+able to use fastboot for example. Use this approach only if you want
+to experiment with virtualization on SA8155P-ADP.
+
+U-Boot ELF file needs to be signed with test keys. `qtestsign
+<https://github.com/msm8916-mainline/qtestsign>`_ tool can be used ::
+
+	$ ../qtestsign/qtestsign.py -v6 hyp u-boot.elf
+
+Resulting ``u-boot-test-signed.mbn`` then can be written to the
+board. Easiest way is to use ``edl`` tool: ::
+
+	$ ../edl/edl w hyp_a u-boot-test-signed.mbn --memory=ufs --lun=4
+
+Be sure to backup existing hyp_a loader before flashing U-Boot.
-- 
2.43.0

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Sumit Garg]

Hi Volodymyr,

On Wed, 6 Mar 2024 at 06:23, Volodymyr Babchuk
<Volodymyr_Babchuk@epam.com> wrote:
>
> SA8155P Automotive Development Platform is Qualcomm SA8155-based board
> for developers. The nice thing that it has unlocked loaders with test
> keys support, which means that U-Boot for this platform can be
> launched at earlier stages.
>
> This patch adds basic board support with only serial port and
> networking operation. I am using U-Boot to ease up Xen porting onto
> this board, so I am mostly interesting in booting U-Boot in EL2. But
> more conventional setup with Android boot image is supported as well.
>
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>
> ---
>
> Changes in v2:
>  - Rebased onto qcom-next branch
>  - Removed unnecessary files thanks to generic qualcomm board support
>  - Enabled CONFIG_REMAKE_ELF (this removes one extra step in the
>    readme)

Thanks for the rebase.

>
>  arch/arm/dts/sa8155p-adp-u-boot.dtsi   | 30 +++++++++
>  board/qualcomm/sa8155p-adp/MAINTAINERS |  5 ++
>  configs/sa8155p_adp_defconfig          | 35 +++++++++++
>  doc/board/qualcomm/index.rst           |  1 +
>  doc/board/qualcomm/sa8155p-adp.rst     | 87 ++++++++++++++++++++++++++
>  5 files changed, 158 insertions(+)
>  create mode 100644 arch/arm/dts/sa8155p-adp-u-boot.dtsi
>  create mode 100644 board/qualcomm/sa8155p-adp/MAINTAINERS
>  create mode 100644 configs/sa8155p_adp_defconfig
>  create mode 100644 doc/board/qualcomm/sa8155p-adp.rst
>
> diff --git a/arch/arm/dts/sa8155p-adp-u-boot.dtsi b/arch/arm/dts/sa8155p-adp-u-boot.dtsi
> new file mode 100644
> index 0000000000..ffbf0933c7
> --- /dev/null
> +++ b/arch/arm/dts/sa8155p-adp-u-boot.dtsi
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Qualcomm SA8155P-ADP device tree fixups for U-BOot
> + *
> + * Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> + * Copyright (c) 2024 EPAM Systems.
> + */
> +
> +/ {
> +       /* Populate memory node with actual memory configuration */
> +       memory@80000000 {
> +               reg = <0x00 0x80000000 0x00 0x39900000>,
> +               <0x02 0x0        0x1  0x7fd00000>,
> +               <0x00 0xC0000000 0x1  0x40000000>;
> +       };
> +};
> +
> +&ethernet {
> +       /* Ethernet driver tries to find reset by name */
> +       reset-names = "emac";

This deserves to be pushed upstream in Linux kernel DT. In the
meantime we can carry it here.

> +};
> +
> +&tlmm {
> +       /* U-Boot pinctrl driver does not understand multiple tiles */
> +       reg = <0x0 0x03000000 0x0 0x1000000>;
> +       /delete-property/ reg-names;

This won't be needed if we can make the tiles offset in the pinctrl
driver compatible:

#define WEST   0x00000000
#define EAST   0x00400000
#define NORTH  0x00800000
#define SOUTH  0x00C00000

> +
> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
> +       /delete-node/ phy-reset-pins;

I suppose this is not needed as phy-reset-pins also configures the pin
as GPIO only.

> +};
> diff --git a/board/qualcomm/sa8155p-adp/MAINTAINERS b/board/qualcomm/sa8155p-adp/MAINTAINERS
> new file mode 100644
> index 0000000000..03fac84f51
> --- /dev/null
> +++ b/board/qualcomm/sa8155p-adp/MAINTAINERS
> @@ -0,0 +1,5 @@
> +Qualcomm SA8155P Automotive Development Platform
> +M:     Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> +S:     Maintained
> +F:     board/qualcomm/sa8155p-adp/
> +F:     configs/sa8155p-adp_defconfig
> diff --git a/configs/sa8155p_adp_defconfig b/configs/sa8155p_adp_defconfig
> new file mode 100644
> index 0000000000..b6969767f8
> --- /dev/null
> +++ b/configs/sa8155p_adp_defconfig
> @@ -0,0 +1,35 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=19000000
> +CONFIG_POSITION_INDEPENDENT=y
> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> +CONFIG_ARCH_SNAPDRAGON=y
> +CONFIG_TEXT_BASE=0x85710000

Being position independent shouldn't require a hardcoded U-Boot text
base. Can you try if we can get rid of this?

> +CONFIG_DEFAULT_DEVICE_TREE="qcom/sa8155p-adp"
> +CONFIG_IDENT_STRING="\nQualcomm SA8155P-ADP"
> +CONFIG_SYS_LOAD_ADDR=0x85710000

Ditto.

> +CONFIG_REMAKE_ELF=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_SYS_CBSIZE=512
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_HUSH_PARSER=y
> +CONFIG_OF_UPSTREAM=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_CLK=y
> +CONFIG_CLK_QCOM_SM8150=y
> +CONFIG_MSM_GPIO=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_PHY_MICREL_KSZ90X1=y
> +CONFIG_DM_MDIO=y
> +CONFIG_DM_ETH_PHY=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_QCOM=y
> +CONFIG_PHY=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCONF=y
> +CONFIG_PINCTRL_QCOM_SM8150=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_MSM_GENI_SERIAL=y
> +CONFIG_SPMI_MSM=y
> +CONFIG_LMB_MAX_REGIONS=64

Apart from above, I think this platform should be able to reuse
qcom_defconfig as you can find most of the config options there. Can
you try to reuse it?

> diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
> index 4955274a39..268218b05f 100644
> --- a/doc/board/qualcomm/index.rst
> +++ b/doc/board/qualcomm/index.rst
> @@ -7,5 +7,6 @@ Qualcomm
>     :maxdepth: 2
>
>     dragonboard410c
> +   sa8155p-adp
>     board
>     debugging
> diff --git a/doc/board/qualcomm/sa8155p-adp.rst b/doc/board/qualcomm/sa8155p-adp.rst
> new file mode 100644
> index 0000000000..66db512b52
> --- /dev/null
> +++ b/doc/board/qualcomm/sa8155p-adp.rst
> @@ -0,0 +1,87 @@
> +.. SPDX-License-Identifier: BSD-3-Clause
> +.. sectionauthor:: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> +
> +SA8155P Automotive Development Platform
> +=======================================
> +
> +About
> +-----
> +This document describes the information about SA8155P Automotive
> +Development Platform aka SA8155P-ADP.
> +
> +Currently U-Boot can be booted either as Android boot image, or in EL2
> +mode, instead of hypervisor image. In the latter case it is possible
> +to use U-Boot to either boot Linux with KVM support or to boot Xen
> +Hypervisor on this board.
> +
> +Supported HW modules
> +^^^^^^^^^^^^^^^^^^^^
> +Port for this board is in early development state. Right now U-Boot
> +supports serial console and networking. No USB/fastboot or UFS support
> +yet. So it is not possible to save environment variables as
> +well. Nevertheless this is enough for development as user can download
> +all required images via TFTP.
> +
> +Installation
> +------------
> +Build
> +^^^^^
> +Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
> +
> +       $ export CROSS_COMPILE=<aarch64 toolchain prefix>
> +       $ make sa8155p_adp_defconfig
> +       $ make
> +
> +This will build ``u-boot.bin`` in the configured output directory.
> +
> +Boot in EL1 mode instead of Android boot image
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +
> +Create a dummy ramdisk image:::
> +
> +       $ echo "This is not a ramdisk" > ramdisk.img
> +
> +Compress u-boot binary:::
> +
> +       $ gzip -c u-boot.bin > u-boot.bin.gz
> +
> +Append DTB again (binary we use already have DTB embedded in, but
> +Android boot image format requires another DTB at the end of the
> +archive):::
> +
> +       $ cat u-boot.bin.gz u-boot.dtb > u-boot.bin.gz-dtb
> +
> +Now we've got everything to build android boot image:::
> +
> +       $ mkbootimg --kernel u-boot.bin.gz-dtb \
> +       --ramdisk ramdisk.img --pagesize 4096 \
> +       --base 0x80000000 -o boot.img
> +
> +Finally you can flash new boot image with fastboot:::
> +
> +       $ fastboot flash boot boot.img
> +
> +Or just boot U-Boot without flashing anything:::
> +
> +       $ fastboot boot boot.img
> +
> +Boot in EL2 mode instead of Qualcomm's hypervisor stub
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +This approach ensures that U-Boot is booted in EL2 and it is possible
> +to run virtualization software (like Xen or KVM) on the board. You
> +must understand that this approach breaks Qualcomm's boot chain. You
> +will not be able to call all subsequent loaders, so you will not be
> +able to use fastboot for example. Use this approach only if you want
> +to experiment with virtualization on SA8155P-ADP.
> +
> +U-Boot ELF file needs to be signed with test keys. `qtestsign
> +<https://github.com/msm8916-mainline/qtestsign>`_ tool can be used ::
> +
> +       $ ../qtestsign/qtestsign.py -v6 hyp u-boot.elf
> +
> +Resulting ``u-boot-test-signed.mbn`` then can be written to the
> +board. Easiest way is to use ``edl`` tool: ::
> +
> +       $ ../edl/edl w hyp_a u-boot-test-signed.mbn --memory=ufs --lun=4
> +

Can you provide reference to the EDL tool and its usage so that people
can recover their board if it gets bricked?

-Sumit

> +Be sure to backup existing hyp_a loader before flashing U-Boot.
> --
> 2.43.0

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Volodymyr Babchuk]

Hi Sumit,

Sumit Garg <sumit.garg@linaro.org> writes:

> Hi Volodymyr,
>
> On Wed, 6 Mar 2024 at 06:23, Volodymyr Babchuk
> <Volodymyr_Babchuk@epam.com> wrote:
>>
>> SA8155P Automotive Development Platform is Qualcomm SA8155-based board
>> for developers. The nice thing that it has unlocked loaders with test
>> keys support, which means that U-Boot for this platform can be
>> launched at earlier stages.
>>
>> This patch adds basic board support with only serial port and
>> networking operation. I am using U-Boot to ease up Xen porting onto
>> this board, so I am mostly interesting in booting U-Boot in EL2. But
>> more conventional setup with Android boot image is supported as well.
>>
>> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>>
>> ---
>>
>> Changes in v2:
>>  - Rebased onto qcom-next branch
>>  - Removed unnecessary files thanks to generic qualcomm board support
>>  - Enabled CONFIG_REMAKE_ELF (this removes one extra step in the
>>    readme)
>
> Thanks for the rebase.

Thank you for the review.

>>
>>  arch/arm/dts/sa8155p-adp-u-boot.dtsi   | 30 +++++++++
>>  board/qualcomm/sa8155p-adp/MAINTAINERS |  5 ++
>>  configs/sa8155p_adp_defconfig          | 35 +++++++++++
>>  doc/board/qualcomm/index.rst           |  1 +
>>  doc/board/qualcomm/sa8155p-adp.rst     | 87 ++++++++++++++++++++++++++
>>  5 files changed, 158 insertions(+)
>>  create mode 100644 arch/arm/dts/sa8155p-adp-u-boot.dtsi
>>  create mode 100644 board/qualcomm/sa8155p-adp/MAINTAINERS
>>  create mode 100644 configs/sa8155p_adp_defconfig
>>  create mode 100644 doc/board/qualcomm/sa8155p-adp.rst
>>
>> diff --git a/arch/arm/dts/sa8155p-adp-u-boot.dtsi b/arch/arm/dts/sa8155p-adp-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..ffbf0933c7
>> --- /dev/null
>> +++ b/arch/arm/dts/sa8155p-adp-u-boot.dtsi
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Qualcomm SA8155P-ADP device tree fixups for U-BOot
>> + *
>> + * Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>> + * Copyright (c) 2024 EPAM Systems.
>> + */
>> +
>> +/ {
>> +       /* Populate memory node with actual memory configuration */
>> +       memory@80000000 {
>> +               reg = <0x00 0x80000000 0x00 0x39900000>,
>> +               <0x02 0x0        0x1  0x7fd00000>,
>> +               <0x00 0xC0000000 0x1  0x40000000>;
>> +       };
>> +};
>> +
>> +&ethernet {
>> +       /* Ethernet driver tries to find reset by name */
>> +       reset-names = "emac";
>
> This deserves to be pushed upstream in Linux kernel DT. In the
> meantime we can carry it here.
>
>> +};
>> +
>> +&tlmm {
>> +       /* U-Boot pinctrl driver does not understand multiple tiles */
>> +       reg = <0x0 0x03000000 0x0 0x1000000>;
>> +       /delete-property/ reg-names;
>
> This won't be needed if we can make the tiles offset in the pinctrl
> driver compatible:
>
> #define WEST   0x00000000
> #define EAST   0x00400000
> #define NORTH  0x00800000
> #define SOUTH  0x00C00000

Hmm, I assume that in this case pinctrl driver should map all the four
tiles independently? Are there guarantees in U-Boot that four separate
memory regions will be mapped into virtual memory with the same relative
positions? Linux clearly don't make such guarantees.

>> +
>> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
>> +       /delete-node/ phy-reset-pins;
>
> I suppose this is not needed as phy-reset-pins also configures the pin
> as GPIO only.
>
Well, yes. This also puzzles me up, but for some reason it stops working
if I leave this node intact. Looks like I need to look at this deeper
before posting the next version.

>> +};
>> diff --git a/board/qualcomm/sa8155p-adp/MAINTAINERS b/board/qualcomm/sa8155p-adp/MAINTAINERS
>> new file mode 100644
>> index 0000000000..03fac84f51
>> --- /dev/null
>> +++ b/board/qualcomm/sa8155p-adp/MAINTAINERS
>> @@ -0,0 +1,5 @@
>> +Qualcomm SA8155P Automotive Development Platform
>> +M:     Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>> +S:     Maintained
>> +F:     board/qualcomm/sa8155p-adp/
>> +F:     configs/sa8155p-adp_defconfig
>> diff --git a/configs/sa8155p_adp_defconfig b/configs/sa8155p_adp_defconfig
>> new file mode 100644
>> index 0000000000..b6969767f8
>> --- /dev/null
>> +++ b/configs/sa8155p_adp_defconfig
>> @@ -0,0 +1,35 @@
>> +CONFIG_ARM=y
>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>> +CONFIG_COUNTER_FREQUENCY=19000000
>> +CONFIG_POSITION_INDEPENDENT=y
>> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
>> +CONFIG_ARCH_SNAPDRAGON=y
>> +CONFIG_TEXT_BASE=0x85710000
>
> Being position independent shouldn't require a hardcoded U-Boot text
> base. Can you try if we can get rid of this?
>

Well, it is required if we want to load U-Boot instead of hyp.mbn. We
need correct addresses in the ELF file so Qualcomm loader will not
reject it right away.

>> +CONFIG_DEFAULT_DEVICE_TREE="qcom/sa8155p-adp"
>> +CONFIG_IDENT_STRING="\nQualcomm SA8155P-ADP"
>> +CONFIG_SYS_LOAD_ADDR=0x85710000
>
> Ditto.
>
>> +CONFIG_REMAKE_ELF=y
>> +CONFIG_BOOTDELAY=3
>> +CONFIG_SYS_CBSIZE=512
>> +# CONFIG_DISPLAY_CPUINFO is not set
>> +CONFIG_HUSH_PARSER=y
>> +CONFIG_OF_UPSTREAM=y
>> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>> +CONFIG_NET_RANDOM_ETHADDR=y
>> +CONFIG_CLK=y
>> +CONFIG_CLK_QCOM_SM8150=y
>> +CONFIG_MSM_GPIO=y
>> +CONFIG_PHY_MICREL=y
>> +CONFIG_PHY_MICREL_KSZ90X1=y
>> +CONFIG_DM_MDIO=y
>> +CONFIG_DM_ETH_PHY=y
>> +CONFIG_DWC_ETH_QOS=y
>> +CONFIG_DWC_ETH_QOS_QCOM=y
>> +CONFIG_PHY=y
>> +CONFIG_PINCTRL=y
>> +CONFIG_PINCONF=y
>> +CONFIG_PINCTRL_QCOM_SM8150=y
>> +CONFIG_POWER_DOMAIN=y
>> +CONFIG_MSM_GENI_SERIAL=y
>> +CONFIG_SPMI_MSM=y
>> +CONFIG_LMB_MAX_REGIONS=64
>
> Apart from above, I think this platform should be able to reuse
> qcom_defconfig as you can find most of the config options there. Can
> you try to reuse it?

Honestly, the whole reason I am porting U-Boot to this platform is
because I want to run Xen on it. And to run Xen, I need to run U-Boot in
EL2. And to do this I need u-boot.elf with "correct" load address and
entry point.

I am planning to publish and upstream Xen patches as well (once I finish
them). And it will be really nice if Xen users will be able use
mainline U-Boot to boot Xen.

>> diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
>> index 4955274a39..268218b05f 100644
>> --- a/doc/board/qualcomm/index.rst
>> +++ b/doc/board/qualcomm/index.rst
>> @@ -7,5 +7,6 @@ Qualcomm
>>     :maxdepth: 2
>>
>>     dragonboard410c
>> +   sa8155p-adp
>>     board
>>     debugging
>> diff --git a/doc/board/qualcomm/sa8155p-adp.rst b/doc/board/qualcomm/sa8155p-adp.rst
>> new file mode 100644
>> index 0000000000..66db512b52
>> --- /dev/null
>> +++ b/doc/board/qualcomm/sa8155p-adp.rst
>> @@ -0,0 +1,87 @@
>> +.. SPDX-License-Identifier: BSD-3-Clause
>> +.. sectionauthor:: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>> +
>> +SA8155P Automotive Development Platform
>> +=======================================
>> +
>> +About
>> +-----
>> +This document describes the information about SA8155P Automotive
>> +Development Platform aka SA8155P-ADP.
>> +
>> +Currently U-Boot can be booted either as Android boot image, or in EL2
>> +mode, instead of hypervisor image. In the latter case it is possible
>> +to use U-Boot to either boot Linux with KVM support or to boot Xen
>> +Hypervisor on this board.
>> +
>> +Supported HW modules
>> +^^^^^^^^^^^^^^^^^^^^
>> +Port for this board is in early development state. Right now U-Boot
>> +supports serial console and networking. No USB/fastboot or UFS support
>> +yet. So it is not possible to save environment variables as
>> +well. Nevertheless this is enough for development as user can download
>> +all required images via TFTP.
>> +
>> +Installation
>> +------------
>> +Build
>> +^^^^^
>> +Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
>> +
>> +       $ export CROSS_COMPILE=<aarch64 toolchain prefix>
>> +       $ make sa8155p_adp_defconfig
>> +       $ make
>> +
>> +This will build ``u-boot.bin`` in the configured output directory.
>> +
>> +Boot in EL1 mode instead of Android boot image
>> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>> +
>> +Create a dummy ramdisk image:::
>> +
>> +       $ echo "This is not a ramdisk" > ramdisk.img
>> +
>> +Compress u-boot binary:::
>> +
>> +       $ gzip -c u-boot.bin > u-boot.bin.gz
>> +
>> +Append DTB again (binary we use already have DTB embedded in, but
>> +Android boot image format requires another DTB at the end of the
>> +archive):::
>> +
>> +       $ cat u-boot.bin.gz u-boot.dtb > u-boot.bin.gz-dtb
>> +
>> +Now we've got everything to build android boot image:::
>> +
>> +       $ mkbootimg --kernel u-boot.bin.gz-dtb \
>> +       --ramdisk ramdisk.img --pagesize 4096 \
>> +       --base 0x80000000 -o boot.img
>> +
>> +Finally you can flash new boot image with fastboot:::
>> +
>> +       $ fastboot flash boot boot.img
>> +
>> +Or just boot U-Boot without flashing anything:::
>> +
>> +       $ fastboot boot boot.img
>> +
>> +Boot in EL2 mode instead of Qualcomm's hypervisor stub
>> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>> +This approach ensures that U-Boot is booted in EL2 and it is possible
>> +to run virtualization software (like Xen or KVM) on the board. You
>> +must understand that this approach breaks Qualcomm's boot chain. You
>> +will not be able to call all subsequent loaders, so you will not be
>> +able to use fastboot for example. Use this approach only if you want
>> +to experiment with virtualization on SA8155P-ADP.
>> +
>> +U-Boot ELF file needs to be signed with test keys. `qtestsign
>> +<https://urldefense.com/v3/__https://github.com/msm8916-mainline/qtestsign__;!!GF_29dbcQIUBPA!0UfvyQldjKBqYC9K5XA-YFiHToTTSqPC1Bik0hYoZFjtfVhrSIOdYKRg45Pu_frCx0I4Shei89pxPWV2V1fqTuquDoA$
>> [github[.]com]>`_ tool can be used ::
>> +
>> +       $ ../qtestsign/qtestsign.py -v6 hyp u-boot.elf
>> +
>> +Resulting ``u-boot-test-signed.mbn`` then can be written to the
>> +board. Easiest way is to use ``edl`` tool: ::
>> +
>> +       $ ../edl/edl w hyp_a u-boot-test-signed.mbn --memory=ufs --lun=4
>> +
>
> Can you provide reference to the EDL tool and its usage so that people
> can recover their board if it gets bricked?

Sure, I'll add the link in the next version.

-- 
WBR, Volodymyr

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Caleb Connolly]

On 06/03/2024 19:14, Volodymyr Babchuk wrote:
> 
> Hi Sumit,
> 
> Sumit Garg <sumit.garg@linaro.org> writes:
> 
>> Hi Volodymyr,
>>
>> On Wed, 6 Mar 2024 at 06:23, Volodymyr Babchuk
>> <Volodymyr_Babchuk@epam.com> wrote:
>>>
>>> SA8155P Automotive Development Platform is Qualcomm SA8155-based board
>>> for developers. The nice thing that it has unlocked loaders with test
>>> keys support, which means that U-Boot for this platform can be
>>> launched at earlier stages.
>>>
>>> This patch adds basic board support with only serial port and
>>> networking operation. I am using U-Boot to ease up Xen porting onto
>>> this board, so I am mostly interesting in booting U-Boot in EL2. But
>>> more conventional setup with Android boot image is supported as well.
>>>
>>> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>>>
>>> ---
>>>
>>> Changes in v2:
>>>  - Rebased onto qcom-next branch
>>>  - Removed unnecessary files thanks to generic qualcomm board support
>>>  - Enabled CONFIG_REMAKE_ELF (this removes one extra step in the
>>>    readme)
>>
>> Thanks for the rebase.
> 
> Thank you for the review.
> 
>>>
>>>  arch/arm/dts/sa8155p-adp-u-boot.dtsi   | 30 +++++++++
>>>  board/qualcomm/sa8155p-adp/MAINTAINERS |  5 ++
>>>  configs/sa8155p_adp_defconfig          | 35 +++++++++++
>>>  doc/board/qualcomm/index.rst           |  1 +
>>>  doc/board/qualcomm/sa8155p-adp.rst     | 87 ++++++++++++++++++++++++++
>>>  5 files changed, 158 insertions(+)
>>>  create mode 100644 arch/arm/dts/sa8155p-adp-u-boot.dtsi
>>>  create mode 100644 board/qualcomm/sa8155p-adp/MAINTAINERS
>>>  create mode 100644 configs/sa8155p_adp_defconfig
>>>  create mode 100644 doc/board/qualcomm/sa8155p-adp.rst
>>>
>>> diff --git a/arch/arm/dts/sa8155p-adp-u-boot.dtsi b/arch/arm/dts/sa8155p-adp-u-boot.dtsi
>>> new file mode 100644
>>> index 0000000000..ffbf0933c7
>>> --- /dev/null
>>> +++ b/arch/arm/dts/sa8155p-adp-u-boot.dtsi
>>> @@ -0,0 +1,30 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Qualcomm SA8155P-ADP device tree fixups for U-BOot
>>> + *
>>> + * Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>>> + * Copyright (c) 2024 EPAM Systems.
>>> + */
>>> +
>>> +/ {
>>> +       /* Populate memory node with actual memory configuration */
>>> +       memory@80000000 {
>>> +               reg = <0x00 0x80000000 0x00 0x39900000>,
>>> +               <0x02 0x0        0x1  0x7fd00000>,
>>> +               <0x00 0xC0000000 0x1  0x40000000>;
>>> +       };
>>> +};
>>> +
>>> +&ethernet {
>>> +       /* Ethernet driver tries to find reset by name */
>>> +       reset-names = "emac";
>>
>> This deserves to be pushed upstream in Linux kernel DT. In the
>> meantime we can carry it here.
>>
>>> +};
>>> +
>>> +&tlmm {
>>> +       /* U-Boot pinctrl driver does not understand multiple tiles */
>>> +       reg = <0x0 0x03000000 0x0 0x1000000>;
>>> +       /delete-property/ reg-names;
>>
>> This won't be needed if we can make the tiles offset in the pinctrl
>> driver compatible:
>>
>> #define WEST   0x00000000
>> #define EAST   0x00400000
>> #define NORTH  0x00800000
>> #define SOUTH  0x00C00000
> 
> Hmm, I assume that in this case pinctrl driver should map all the four
> tiles independently? Are there guarantees in U-Boot that four separate
> memory regions will be mapped into virtual memory with the same relative
> positions? Linux clearly don't make such guarantees.

U-Boot doesn't use virtual addresses on arm platforms, it only goes as
far as reading the address from DT, nothing else, so this is totally
fine and is how the other SoCs do it.
> 
>>> +
>>> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
>>> +       /delete-node/ phy-reset-pins;
>>
>> I suppose this is not needed as phy-reset-pins also configures the pin
>> as GPIO only.
>>
> Well, yes. This also puzzles me up, but for some reason it stops working
> if I leave this node intact. Looks like I need to look at this deeper
> before posting the next version.

Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
misbehave, can you check if this patch fixes it (there is a bug in the
line "return msm_gpio_direction_input(dev, gpio);", it should become
just "msm_gpio_direction_input(dev, gpio);").

I had the exact same issue with the gpio-regulator driver and this was
the solution I ended up going with.

https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787db0@linaro.org/
> 
>>> +};
>>> diff --git a/board/qualcomm/sa8155p-adp/MAINTAINERS b/board/qualcomm/sa8155p-adp/MAINTAINERS
>>> new file mode 100644
>>> index 0000000000..03fac84f51
>>> --- /dev/null
>>> +++ b/board/qualcomm/sa8155p-adp/MAINTAINERS
>>> @@ -0,0 +1,5 @@
>>> +Qualcomm SA8155P Automotive Development Platform
>>> +M:     Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>>> +S:     Maintained
>>> +F:     board/qualcomm/sa8155p-adp/
>>> +F:     configs/sa8155p-adp_defconfig
>>> diff --git a/configs/sa8155p_adp_defconfig b/configs/sa8155p_adp_defconfig
>>> new file mode 100644
>>> index 0000000000..b6969767f8
>>> --- /dev/null
>>> +++ b/configs/sa8155p_adp_defconfig
>>> @@ -0,0 +1,35 @@
>>> +CONFIG_ARM=y
>>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>>> +CONFIG_COUNTER_FREQUENCY=19000000
>>> +CONFIG_POSITION_INDEPENDENT=y
>>> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
>>> +CONFIG_ARCH_SNAPDRAGON=y
>>> +CONFIG_TEXT_BASE=0x85710000
>>
>> Being position independent shouldn't require a hardcoded U-Boot text
>> base. Can you try if we can get rid of this?
>>
> 
> Well, it is required if we want to load U-Boot instead of hyp.mbn. We
> need correct addresses in the ELF file so Qualcomm loader will not
> reject it right away.
> 
>>> +CONFIG_DEFAULT_DEVICE_TREE="qcom/sa8155p-adp"
>>> +CONFIG_IDENT_STRING="\nQualcomm SA8155P-ADP"
>>> +CONFIG_SYS_LOAD_ADDR=0x85710000
>>
>> Ditto.
>>
>>> +CONFIG_REMAKE_ELF=y
>>> +CONFIG_BOOTDELAY=3
>>> +CONFIG_SYS_CBSIZE=512
>>> +# CONFIG_DISPLAY_CPUINFO is not set
>>> +CONFIG_HUSH_PARSER=y
>>> +CONFIG_OF_UPSTREAM=y
>>> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>>> +CONFIG_NET_RANDOM_ETHADDR=y
>>> +CONFIG_CLK=y
>>> +CONFIG_CLK_QCOM_SM8150=y
>>> +CONFIG_MSM_GPIO=y
>>> +CONFIG_PHY_MICREL=y
>>> +CONFIG_PHY_MICREL_KSZ90X1=y
>>> +CONFIG_DM_MDIO=y
>>> +CONFIG_DM_ETH_PHY=y
>>> +CONFIG_DWC_ETH_QOS=y
>>> +CONFIG_DWC_ETH_QOS_QCOM=y
>>> +CONFIG_PHY=y
>>> +CONFIG_PINCTRL=y
>>> +CONFIG_PINCONF=y
>>> +CONFIG_PINCTRL_QCOM_SM8150=y
>>> +CONFIG_POWER_DOMAIN=y
>>> +CONFIG_MSM_GENI_SERIAL=y
>>> +CONFIG_SPMI_MSM=y
>>> +CONFIG_LMB_MAX_REGIONS=64
>>
>> Apart from above, I think this platform should be able to reuse
>> qcom_defconfig as you can find most of the config options there. Can
>> you try to reuse it?
> 
> Honestly, the whole reason I am porting U-Boot to this platform is
> because I want to run Xen on it. And to run Xen, I need to run U-Boot in
> EL2. And to do this I need u-boot.elf with "correct" load address and
> entry point.
> 
> I am planning to publish and upstream Xen patches as well (once I finish
> them). And it will be really nice if Xen users will be able use
> mainline U-Boot to boot Xen.

I would like to enable the SM8150 drivers in qcom_defconfig (for
chainloading and supporting other platforms). But I'm totally fine with
having a separate defconfig for this board with this configuration.
> 
>>> diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
>>> index 4955274a39..268218b05f 100644
>>> --- a/doc/board/qualcomm/index.rst
>>> +++ b/doc/board/qualcomm/index.rst
>>> @@ -7,5 +7,6 @@ Qualcomm
>>>     :maxdepth: 2
>>>
>>>     dragonboard410c
>>> +   sa8155p-adp
>>>     board
>>>     debugging
>>> diff --git a/doc/board/qualcomm/sa8155p-adp.rst b/doc/board/qualcomm/sa8155p-adp.rst
>>> new file mode 100644
>>> index 0000000000..66db512b52
>>> --- /dev/null
>>> +++ b/doc/board/qualcomm/sa8155p-adp.rst
>>> @@ -0,0 +1,87 @@
>>> +.. SPDX-License-Identifier: BSD-3-Clause
>>> +.. sectionauthor:: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>>> +
>>> +SA8155P Automotive Development Platform
>>> +=======================================
>>> +
>>> +About
>>> +-----
>>> +This document describes the information about SA8155P Automotive
>>> +Development Platform aka SA8155P-ADP.
>>> +
>>> +Currently U-Boot can be booted either as Android boot image, or in EL2
>>> +mode, instead of hypervisor image. In the latter case it is possible
>>> +to use U-Boot to either boot Linux with KVM support or to boot Xen
>>> +Hypervisor on this board.
>>> +
>>> +Supported HW modules
>>> +^^^^^^^^^^^^^^^^^^^^
>>> +Port for this board is in early development state. Right now U-Boot
>>> +supports serial console and networking. No USB/fastboot or UFS support
>>> +yet. So it is not possible to save environment variables as
>>> +well. Nevertheless this is enough for development as user can download
>>> +all required images via TFTP.
>>> +
>>> +Installation
>>> +------------
>>> +Build
>>> +^^^^^
>>> +Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
>>> +
>>> +       $ export CROSS_COMPILE=<aarch64 toolchain prefix>
>>> +       $ make sa8155p_adp_defconfig
>>> +       $ make
>>> +
>>> +This will build ``u-boot.bin`` in the configured output directory.
>>> +
>>> +Boot in EL1 mode instead of Android boot image
>>> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>>> +
>>> +Create a dummy ramdisk image:::
>>> +
>>> +       $ echo "This is not a ramdisk" > ramdisk.img
>>> +
>>> +Compress u-boot binary:::
>>> +
>>> +       $ gzip -c u-boot.bin > u-boot.bin.gz
>>> +
>>> +Append DTB again (binary we use already have DTB embedded in, but
>>> +Android boot image format requires another DTB at the end of the
>>> +archive):::
>>> +
>>> +       $ cat u-boot.bin.gz u-boot.dtb > u-boot.bin.gz-dtb
>>> +
>>> +Now we've got everything to build android boot image:::
>>> +
>>> +       $ mkbootimg --kernel u-boot.bin.gz-dtb \
>>> +       --ramdisk ramdisk.img --pagesize 4096 \
>>> +       --base 0x80000000 -o boot.img
>>> +
>>> +Finally you can flash new boot image with fastboot:::
>>> +
>>> +       $ fastboot flash boot boot.img
>>> +
>>> +Or just boot U-Boot without flashing anything:::
>>> +
>>> +       $ fastboot boot boot.img
>>> +
>>> +Boot in EL2 mode instead of Qualcomm's hypervisor stub
>>> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>>> +This approach ensures that U-Boot is booted in EL2 and it is possible
>>> +to run virtualization software (like Xen or KVM) on the board. You
>>> +must understand that this approach breaks Qualcomm's boot chain. You
>>> +will not be able to call all subsequent loaders, so you will not be
>>> +able to use fastboot for example. Use this approach only if you want
>>> +to experiment with virtualization on SA8155P-ADP.
>>> +
>>> +U-Boot ELF file needs to be signed with test keys. `qtestsign
>>> +<https://urldefense.com/v3/__https://github.com/msm8916-mainline/qtestsign__;!!GF_29dbcQIUBPA!0UfvyQldjKBqYC9K5XA-YFiHToTTSqPC1Bik0hYoZFjtfVhrSIOdYKRg45Pu_frCx0I4Shei89pxPWV2V1fqTuquDoA$
>>> [github[.]com]>`_ tool can be used ::
>>> +
>>> +       $ ../qtestsign/qtestsign.py -v6 hyp u-boot.elf
>>> +
>>> +Resulting ``u-boot-test-signed.mbn`` then can be written to the
>>> +board. Easiest way is to use ``edl`` tool: ::
>>> +
>>> +       $ ../edl/edl w hyp_a u-boot-test-signed.mbn --memory=ufs --lun=4
>>> +
>>
>> Can you provide reference to the EDL tool and its usage so that people
>> can recover their board if it gets bricked?
> 
> Sure, I'll add the link in the next version.
> 

-- 
// Caleb (they/them)

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Volodymyr Babchuk]

Hi Caleb,

Caleb Connolly <caleb.connolly@linaro.org> writes:

[...]
>>>> +};
>>>> +
>>>> +&tlmm {
>>>> +       /* U-Boot pinctrl driver does not understand multiple tiles */
>>>> +       reg = <0x0 0x03000000 0x0 0x1000000>;
>>>> +       /delete-property/ reg-names;
>>>
>>> This won't be needed if we can make the tiles offset in the pinctrl
>>> driver compatible:
>>>
>>> #define WEST   0x00000000
>>> #define EAST   0x00400000
>>> #define NORTH  0x00800000
>>> #define SOUTH  0x00C00000
>> 
>> Hmm, I assume that in this case pinctrl driver should map all the four
>> tiles independently? Are there guarantees in U-Boot that four separate
>> memory regions will be mapped into virtual memory with the same relative
>> positions? Linux clearly don't make such guarantees.
>
> U-Boot doesn't use virtual addresses on arm platforms, it only goes as
> far as reading the address from DT, nothing else, so this is totally
> fine and is how the other SoCs do it.

For me it looks like we are depending on implementation details
knowledge. I.e MMU API does not provide such guarantees, but drivers
know how ARM MMU code is working internally and drivers depend on
exactly this behavior. But if you are saying that it is totally fine,
I'll rework the patch. No big deal. Actually, I already tried this and
it is working fine.

>>>> +
>>>> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
>>>> +       /delete-node/ phy-reset-pins;
>>>
>>> I suppose this is not needed as phy-reset-pins also configures the pin
>>> as GPIO only.
>>>
>> Well, yes. This also puzzles me up, but for some reason it stops working
>> if I leave this node intact. Looks like I need to look at this deeper
>> before posting the next version.
>
> Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
> misbehave, can you check if this patch fixes it (there is a bug in the
> line "return msm_gpio_direction_input(dev, gpio);", it should become
> just "msm_gpio_direction_input(dev, gpio);").
>
> I had the exact same issue with the gpio-regulator driver and this was
> the solution I ended up going with.
>
> https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787db0@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
> [lore[.]kernel[.]org]

It is exactly this. With your patch I don't need to /delete-node/
anymore. I'll add a comment in the cover message that this series are
depended on your patch.

(and sorry for the mangled link. It is our corporate mail server doing)


>> 
>>>> +};
>>>> diff --git a/board/qualcomm/sa8155p-adp/MAINTAINERS b/board/qualcomm/sa8155p-adp/MAINTAINERS
>>>> new file mode 100644
>>>> index 0000000000..03fac84f51
>>>> --- /dev/null
>>>> +++ b/board/qualcomm/sa8155p-adp/MAINTAINERS
>>>> @@ -0,0 +1,5 @@
>>>> +Qualcomm SA8155P Automotive Development Platform
>>>> +M:     Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>>>> +S:     Maintained
>>>> +F:     board/qualcomm/sa8155p-adp/
>>>> +F:     configs/sa8155p-adp_defconfig
>>>> diff --git a/configs/sa8155p_adp_defconfig b/configs/sa8155p_adp_defconfig
>>>> new file mode 100644
>>>> index 0000000000..b6969767f8
>>>> --- /dev/null
>>>> +++ b/configs/sa8155p_adp_defconfig
>>>> @@ -0,0 +1,35 @@
>>>> +CONFIG_ARM=y
>>>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>>>> +CONFIG_COUNTER_FREQUENCY=19000000
>>>> +CONFIG_POSITION_INDEPENDENT=y
>>>> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
>>>> +CONFIG_ARCH_SNAPDRAGON=y
>>>> +CONFIG_TEXT_BASE=0x85710000
>>>
>>> Being position independent shouldn't require a hardcoded U-Boot text
>>> base. Can you try if we can get rid of this?
>>>
>> 
>> Well, it is required if we want to load U-Boot instead of hyp.mbn. We
>> need correct addresses in the ELF file so Qualcomm loader will not
>> reject it right away.
>> 
>>>> +CONFIG_DEFAULT_DEVICE_TREE="qcom/sa8155p-adp"
>>>> +CONFIG_IDENT_STRING="\nQualcomm SA8155P-ADP"
>>>> +CONFIG_SYS_LOAD_ADDR=0x85710000
>>>
>>> Ditto.
>>>
>>>> +CONFIG_REMAKE_ELF=y
>>>> +CONFIG_BOOTDELAY=3
>>>> +CONFIG_SYS_CBSIZE=512
>>>> +# CONFIG_DISPLAY_CPUINFO is not set
>>>> +CONFIG_HUSH_PARSER=y
>>>> +CONFIG_OF_UPSTREAM=y
>>>> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>>>> +CONFIG_NET_RANDOM_ETHADDR=y
>>>> +CONFIG_CLK=y
>>>> +CONFIG_CLK_QCOM_SM8150=y
>>>> +CONFIG_MSM_GPIO=y
>>>> +CONFIG_PHY_MICREL=y
>>>> +CONFIG_PHY_MICREL_KSZ90X1=y
>>>> +CONFIG_DM_MDIO=y
>>>> +CONFIG_DM_ETH_PHY=y
>>>> +CONFIG_DWC_ETH_QOS=y
>>>> +CONFIG_DWC_ETH_QOS_QCOM=y
>>>> +CONFIG_PHY=y
>>>> +CONFIG_PINCTRL=y
>>>> +CONFIG_PINCONF=y
>>>> +CONFIG_PINCTRL_QCOM_SM8150=y
>>>> +CONFIG_POWER_DOMAIN=y
>>>> +CONFIG_MSM_GENI_SERIAL=y
>>>> +CONFIG_SPMI_MSM=y
>>>> +CONFIG_LMB_MAX_REGIONS=64
>>>
>>> Apart from above, I think this platform should be able to reuse
>>> qcom_defconfig as you can find most of the config options there. Can
>>> you try to reuse it?
>> 
>> Honestly, the whole reason I am porting U-Boot to this platform is
>> because I want to run Xen on it. And to run Xen, I need to run U-Boot in
>> EL2. And to do this I need u-boot.elf with "correct" load address and
>> entry point.
>> 
>> I am planning to publish and upstream Xen patches as well (once I finish
>> them). And it will be really nice if Xen users will be able use
>> mainline U-Boot to boot Xen.
>
> I would like to enable the SM8150 drivers in qcom_defconfig (for
> chainloading and supporting other platforms). But I'm totally fine with
> having a separate defconfig for this board with this configuration.

Yes, this is a good approach. I'll do this.

[...]

-- 
WBR, Volodymyr

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Sumit Garg]

On Thu, 7 Mar 2024 at 02:54, Volodymyr Babchuk
<Volodymyr_Babchuk@epam.com> wrote:
>
>
> Hi Caleb,
>
> Caleb Connolly <caleb.connolly@linaro.org> writes:
>
> [...]
> >>>> +};
> >>>> +
> >>>> +&tlmm {
> >>>> +       /* U-Boot pinctrl driver does not understand multiple tiles */
> >>>> +       reg = <0x0 0x03000000 0x0 0x1000000>;
> >>>> +       /delete-property/ reg-names;
> >>>
> >>> This won't be needed if we can make the tiles offset in the pinctrl
> >>> driver compatible:
> >>>
> >>> #define WEST   0x00000000
> >>> #define EAST   0x00400000
> >>> #define NORTH  0x00800000
> >>> #define SOUTH  0x00C00000
> >>
> >> Hmm, I assume that in this case pinctrl driver should map all the four
> >> tiles independently? Are there guarantees in U-Boot that four separate
> >> memory regions will be mapped into virtual memory with the same relative
> >> positions? Linux clearly don't make such guarantees.
> >
> > U-Boot doesn't use virtual addresses on arm platforms, it only goes as
> > far as reading the address from DT, nothing else, so this is totally
> > fine and is how the other SoCs do it.
>
> For me it looks like we are depending on implementation details
> knowledge. I.e MMU API does not provide such guarantees, but drivers
> know how ARM MMU code is working internally and drivers depend on
> exactly this behavior. But if you are saying that it is totally fine,
> I'll rework the patch. No big deal. Actually, I already tried this and
> it is working fine.

I agree doing it properly via mapping pinctrl tiles individually is
the appropriate approach. BTW, the current implementation just relies
on 1:1 VA to PA mapping in U-Boot, it just avoids deviation from
upstream DTS. If you are willing to change msm_pinctrl_probe() to
parse tiles properly then I would be happy to review that.

>
> >>>> +
> >>>> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
> >>>> +       /delete-node/ phy-reset-pins;
> >>>
> >>> I suppose this is not needed as phy-reset-pins also configures the pin
> >>> as GPIO only.
> >>>
> >> Well, yes. This also puzzles me up, but for some reason it stops working
> >> if I leave this node intact. Looks like I need to look at this deeper
> >> before posting the next version.
> >
> > Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
> > misbehave, can you check if this patch fixes it (there is a bug in the
> > line "return msm_gpio_direction_input(dev, gpio);", it should become
> > just "msm_gpio_direction_input(dev, gpio);").
> >
> > I had the exact same issue with the gpio-regulator driver and this was
> > the solution I ended up going with.
> >
> > https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787db0@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
> > [lore[.]kernel[.]org]
>
> It is exactly this. With your patch I don't need to /delete-node/
> anymore. I'll add a comment in the cover message that this series are
> depended on your patch.
>

+1

> (and sorry for the mangled link. It is our corporate mail server doing)
>
>
> >>
> >>>> +};
> >>>> diff --git a/board/qualcomm/sa8155p-adp/MAINTAINERS b/board/qualcomm/sa8155p-adp/MAINTAINERS
> >>>> new file mode 100644
> >>>> index 0000000000..03fac84f51
> >>>> --- /dev/null
> >>>> +++ b/board/qualcomm/sa8155p-adp/MAINTAINERS
> >>>> @@ -0,0 +1,5 @@
> >>>> +Qualcomm SA8155P Automotive Development Platform
> >>>> +M:     Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> >>>> +S:     Maintained
> >>>> +F:     board/qualcomm/sa8155p-adp/
> >>>> +F:     configs/sa8155p-adp_defconfig
> >>>> diff --git a/configs/sa8155p_adp_defconfig b/configs/sa8155p_adp_defconfig
> >>>> new file mode 100644
> >>>> index 0000000000..b6969767f8
> >>>> --- /dev/null
> >>>> +++ b/configs/sa8155p_adp_defconfig
> >>>> @@ -0,0 +1,35 @@
> >>>> +CONFIG_ARM=y
> >>>> +CONFIG_SKIP_LOWLEVEL_INIT=y
> >>>> +CONFIG_COUNTER_FREQUENCY=19000000
> >>>> +CONFIG_POSITION_INDEPENDENT=y
> >>>> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> >>>> +CONFIG_ARCH_SNAPDRAGON=y
> >>>> +CONFIG_TEXT_BASE=0x85710000
> >>>
> >>> Being position independent shouldn't require a hardcoded U-Boot text
> >>> base. Can you try if we can get rid of this?
> >>>
> >>
> >> Well, it is required if we want to load U-Boot instead of hyp.mbn. We
> >> need correct addresses in the ELF file so Qualcomm loader will not
> >> reject it right away.
> >>

I see the hard dependency due to prior stage Qcom bootloaders.

> >>>> +CONFIG_DEFAULT_DEVICE_TREE="qcom/sa8155p-adp"
> >>>> +CONFIG_IDENT_STRING="\nQualcomm SA8155P-ADP"
> >>>> +CONFIG_SYS_LOAD_ADDR=0x85710000
> >>>
> >>> Ditto.
> >>>
> >>>> +CONFIG_REMAKE_ELF=y
> >>>> +CONFIG_BOOTDELAY=3
> >>>> +CONFIG_SYS_CBSIZE=512
> >>>> +# CONFIG_DISPLAY_CPUINFO is not set
> >>>> +CONFIG_HUSH_PARSER=y
> >>>> +CONFIG_OF_UPSTREAM=y
> >>>> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> >>>> +CONFIG_NET_RANDOM_ETHADDR=y
> >>>> +CONFIG_CLK=y
> >>>> +CONFIG_CLK_QCOM_SM8150=y
> >>>> +CONFIG_MSM_GPIO=y
> >>>> +CONFIG_PHY_MICREL=y
> >>>> +CONFIG_PHY_MICREL_KSZ90X1=y
> >>>> +CONFIG_DM_MDIO=y
> >>>> +CONFIG_DM_ETH_PHY=y
> >>>> +CONFIG_DWC_ETH_QOS=y
> >>>> +CONFIG_DWC_ETH_QOS_QCOM=y
> >>>> +CONFIG_PHY=y
> >>>> +CONFIG_PINCTRL=y
> >>>> +CONFIG_PINCONF=y
> >>>> +CONFIG_PINCTRL_QCOM_SM8150=y
> >>>> +CONFIG_POWER_DOMAIN=y
> >>>> +CONFIG_MSM_GENI_SERIAL=y
> >>>> +CONFIG_SPMI_MSM=y
> >>>> +CONFIG_LMB_MAX_REGIONS=64
> >>>
> >>> Apart from above, I think this platform should be able to reuse
> >>> qcom_defconfig as you can find most of the config options there. Can
> >>> you try to reuse it?
> >>
> >> Honestly, the whole reason I am porting U-Boot to this platform is
> >> because I want to run Xen on it. And to run Xen, I need to run U-Boot in
> >> EL2. And to do this I need u-boot.elf with "correct" load address and
> >> entry point.
> >>
> >> I am planning to publish and upstream Xen patches as well (once I finish
> >> them). And it will be really nice if Xen users will be able use
> >> mainline U-Boot to boot Xen.

That's fair and I am happy for it to be a separate defconfig.

> >
> > I would like to enable the SM8150 drivers in qcom_defconfig (for
> > chainloading and supporting other platforms). But I'm totally fine with
> > having a separate defconfig for this board with this configuration.

Probably the common defconfig is up for renaming:
s/qcom_defconfig/qcom_chainload_defconfig/ since that seems to be the
only configuration we can support with a common defconfig.

>
> Yes, this is a good approach. I'll do this.
>

So you can probably drop CONFIG_POSITION_INDEPENDENT=y from this
defconfig and rather use the common defconfig for chainloaded
configuration.

-Sumit

> [...]


>
> --
> WBR, Volodymyr

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Caleb Connolly]

On 06/03/2024 21:24, Volodymyr Babchuk wrote:
> 
> Hi Caleb,
> 
> Caleb Connolly <caleb.connolly@linaro.org> writes:
> 
> [...]
>>>>> +};
>>>>> +
>>>>> +&tlmm {
>>>>> +       /* U-Boot pinctrl driver does not understand multiple tiles */
>>>>> +       reg = <0x0 0x03000000 0x0 0x1000000>;
>>>>> +       /delete-property/ reg-names;
>>>>
>>>> This won't be needed if we can make the tiles offset in the pinctrl
>>>> driver compatible:
>>>>
>>>> #define WEST   0x00000000
>>>> #define EAST   0x00400000
>>>> #define NORTH  0x00800000
>>>> #define SOUTH  0x00C00000
>>>
>>> Hmm, I assume that in this case pinctrl driver should map all the four
>>> tiles independently? Are there guarantees in U-Boot that four separate
>>> memory regions will be mapped into virtual memory with the same relative
>>> positions? Linux clearly don't make such guarantees.
>>
>> U-Boot doesn't use virtual addresses on arm platforms, it only goes as
>> far as reading the address from DT, nothing else, so this is totally
>> fine and is how the other SoCs do it.
> 
> For me it looks like we are depending on implementation details
> knowledge. I.e MMU API does not provide such guarantees, but drivers
> know how ARM MMU code is working internally and drivers depend on
> exactly this behavior. But if you are saying that it is totally fine,
> I'll rework the patch. No big deal. Actually, I already tried this and
> it is working fine.
> 
>>>>> +
>>>>> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
>>>>> +       /delete-node/ phy-reset-pins;
>>>>
>>>> I suppose this is not needed as phy-reset-pins also configures the pin
>>>> as GPIO only.
>>>>
>>> Well, yes. This also puzzles me up, but for some reason it stops working
>>> if I leave this node intact. Looks like I need to look at this deeper
>>> before posting the next version.
>>
>> Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
>> misbehave, can you check if this patch fixes it (there is a bug in the
>> line "return msm_gpio_direction_input(dev, gpio);", it should become
>> just "msm_gpio_direction_input(dev, gpio);").
>>
>> I had the exact same issue with the gpio-regulator driver and this was
>> the solution I ended up going with.
>>
>> https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787db0@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
>> [lore[.]kernel[.]org]
> 
> It is exactly this. With your patch I don't need to /delete-node/
> anymore. I'll add a comment in the cover message that this series are
> depended on your patch.

Please can you split the power domain and clock patches into a separate
series? As I'd like to depend on them for the next revision of my
series, and we'd otherwise have a cyclical dependency.
> 
> (and sorry for the mangled link. It is our corporate mail server doing)
> 
> 
>>>
>>>>> +};
>>>>> diff --git a/board/qualcomm/sa8155p-adp/MAINTAINERS b/board/qualcomm/sa8155p-adp/MAINTAINERS
>>>>> new file mode 100644
>>>>> index 0000000000..03fac84f51
>>>>> --- /dev/null
>>>>> +++ b/board/qualcomm/sa8155p-adp/MAINTAINERS
>>>>> @@ -0,0 +1,5 @@
>>>>> +Qualcomm SA8155P Automotive Development Platform
>>>>> +M:     Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>>>>> +S:     Maintained
>>>>> +F:     board/qualcomm/sa8155p-adp/
>>>>> +F:     configs/sa8155p-adp_defconfig
>>>>> diff --git a/configs/sa8155p_adp_defconfig b/configs/sa8155p_adp_defconfig
>>>>> new file mode 100644
>>>>> index 0000000000..b6969767f8
>>>>> --- /dev/null
>>>>> +++ b/configs/sa8155p_adp_defconfig
>>>>> @@ -0,0 +1,35 @@
>>>>> +CONFIG_ARM=y
>>>>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>>>>> +CONFIG_COUNTER_FREQUENCY=19000000
>>>>> +CONFIG_POSITION_INDEPENDENT=y
>>>>> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
>>>>> +CONFIG_ARCH_SNAPDRAGON=y
>>>>> +CONFIG_TEXT_BASE=0x85710000
>>>>
>>>> Being position independent shouldn't require a hardcoded U-Boot text
>>>> base. Can you try if we can get rid of this?
>>>>
>>>
>>> Well, it is required if we want to load U-Boot instead of hyp.mbn. We
>>> need correct addresses in the ELF file so Qualcomm loader will not
>>> reject it right away.
>>>
>>>>> +CONFIG_DEFAULT_DEVICE_TREE="qcom/sa8155p-adp"
>>>>> +CONFIG_IDENT_STRING="\nQualcomm SA8155P-ADP"
>>>>> +CONFIG_SYS_LOAD_ADDR=0x85710000
>>>>
>>>> Ditto.
>>>>
>>>>> +CONFIG_REMAKE_ELF=y
>>>>> +CONFIG_BOOTDELAY=3
>>>>> +CONFIG_SYS_CBSIZE=512
>>>>> +# CONFIG_DISPLAY_CPUINFO is not set
>>>>> +CONFIG_HUSH_PARSER=y
>>>>> +CONFIG_OF_UPSTREAM=y
>>>>> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
>>>>> +CONFIG_NET_RANDOM_ETHADDR=y
>>>>> +CONFIG_CLK=y
>>>>> +CONFIG_CLK_QCOM_SM8150=y
>>>>> +CONFIG_MSM_GPIO=y
>>>>> +CONFIG_PHY_MICREL=y
>>>>> +CONFIG_PHY_MICREL_KSZ90X1=y
>>>>> +CONFIG_DM_MDIO=y
>>>>> +CONFIG_DM_ETH_PHY=y
>>>>> +CONFIG_DWC_ETH_QOS=y
>>>>> +CONFIG_DWC_ETH_QOS_QCOM=y
>>>>> +CONFIG_PHY=y
>>>>> +CONFIG_PINCTRL=y
>>>>> +CONFIG_PINCONF=y
>>>>> +CONFIG_PINCTRL_QCOM_SM8150=y
>>>>> +CONFIG_POWER_DOMAIN=y
>>>>> +CONFIG_MSM_GENI_SERIAL=y
>>>>> +CONFIG_SPMI_MSM=y
>>>>> +CONFIG_LMB_MAX_REGIONS=64
>>>>
>>>> Apart from above, I think this platform should be able to reuse
>>>> qcom_defconfig as you can find most of the config options there. Can
>>>> you try to reuse it?
>>>
>>> Honestly, the whole reason I am porting U-Boot to this platform is
>>> because I want to run Xen on it. And to run Xen, I need to run U-Boot in
>>> EL2. And to do this I need u-boot.elf with "correct" load address and
>>> entry point.
>>>
>>> I am planning to publish and upstream Xen patches as well (once I finish
>>> them). And it will be really nice if Xen users will be able use
>>> mainline U-Boot to boot Xen.
>>
>> I would like to enable the SM8150 drivers in qcom_defconfig (for
>> chainloading and supporting other platforms). But I'm totally fine with
>> having a separate defconfig for this board with this configuration.
> 
> Yes, this is a good approach. I'll do this.
> 
> [...]
> 

-- 
// Caleb (they/them)

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Volodymyr Babchuk]

Hi Caleb,

Caleb Connolly <caleb.connolly@linaro.org> writes:

> On 06/03/2024 21:24, Volodymyr Babchuk wrote:
>> 
>> Hi Caleb,
>> 
>> Caleb Connolly <caleb.connolly@linaro.org> writes:
>> 
>> [...]
>>>>>> +};
>>>>>> +
>>>>>> +&tlmm {
>>>>>> +       /* U-Boot pinctrl driver does not understand multiple tiles */
>>>>>> +       reg = <0x0 0x03000000 0x0 0x1000000>;
>>>>>> +       /delete-property/ reg-names;
>>>>>
>>>>> This won't be needed if we can make the tiles offset in the pinctrl
>>>>> driver compatible:
>>>>>
>>>>> #define WEST   0x00000000
>>>>> #define EAST   0x00400000
>>>>> #define NORTH  0x00800000
>>>>> #define SOUTH  0x00C00000
>>>>
>>>> Hmm, I assume that in this case pinctrl driver should map all the four
>>>> tiles independently? Are there guarantees in U-Boot that four separate
>>>> memory regions will be mapped into virtual memory with the same relative
>>>> positions? Linux clearly don't make such guarantees.
>>>
>>> U-Boot doesn't use virtual addresses on arm platforms, it only goes as
>>> far as reading the address from DT, nothing else, so this is totally
>>> fine and is how the other SoCs do it.
>> 
>> For me it looks like we are depending on implementation details
>> knowledge. I.e MMU API does not provide such guarantees, but drivers
>> know how ARM MMU code is working internally and drivers depend on
>> exactly this behavior. But if you are saying that it is totally fine,
>> I'll rework the patch. No big deal. Actually, I already tried this and
>> it is working fine.
>> 
>>>>>> +
>>>>>> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
>>>>>> +       /delete-node/ phy-reset-pins;
>>>>>
>>>>> I suppose this is not needed as phy-reset-pins also configures the pin
>>>>> as GPIO only.
>>>>>
>>>> Well, yes. This also puzzles me up, but for some reason it stops working
>>>> if I leave this node intact. Looks like I need to look at this deeper
>>>> before posting the next version.
>>>
>>> Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
>>> misbehave, can you check if this patch fixes it (there is a bug in the
>>> line "return msm_gpio_direction_input(dev, gpio);", it should become
>>> just "msm_gpio_direction_input(dev, gpio);").
>>>
>>> I had the exact same issue with the gpio-regulator driver and this was
>>> the solution I ended up going with.
>>>
>>> https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787db0@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
>>> [lore[.]kernel[.]org]
>> 
>> It is exactly this. With your patch I don't need to /delete-node/
>> anymore. I'll add a comment in the cover message that this series are
>> depended on your patch.
>
> Please can you split the power domain and clock patches into a separate
> series? As I'd like to depend on them for the next revision of my
> series, and we'd otherwise have a cyclical dependency.

Of course.

As I understood, you are interested in "clk: qcom: clear div mask before
assigning a new divider" and "clk: qcom: add support for power domains
uclass", correct?


-- 
WBR, Volodymyr

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Caleb Connolly]

On 11/03/2024 18:23, Volodymyr Babchuk wrote:
> 
> Hi Caleb,
> 
> Caleb Connolly <caleb.connolly@linaro.org> writes:
> 
>> On 06/03/2024 21:24, Volodymyr Babchuk wrote:
>>>
>>> Hi Caleb,
>>>
>>> Caleb Connolly <caleb.connolly@linaro.org> writes:
>>>
>>> [...]
>>>>>>> +};
>>>>>>> +
>>>>>>> +&tlmm {
>>>>>>> +       /* U-Boot pinctrl driver does not understand multiple tiles */
>>>>>>> +       reg = <0x0 0x03000000 0x0 0x1000000>;
>>>>>>> +       /delete-property/ reg-names;
>>>>>>
>>>>>> This won't be needed if we can make the tiles offset in the pinctrl
>>>>>> driver compatible:
>>>>>>
>>>>>> #define WEST   0x00000000
>>>>>> #define EAST   0x00400000
>>>>>> #define NORTH  0x00800000
>>>>>> #define SOUTH  0x00C00000
>>>>>
>>>>> Hmm, I assume that in this case pinctrl driver should map all the four
>>>>> tiles independently? Are there guarantees in U-Boot that four separate
>>>>> memory regions will be mapped into virtual memory with the same relative
>>>>> positions? Linux clearly don't make such guarantees.
>>>>
>>>> U-Boot doesn't use virtual addresses on arm platforms, it only goes as
>>>> far as reading the address from DT, nothing else, so this is totally
>>>> fine and is how the other SoCs do it.
>>>
>>> For me it looks like we are depending on implementation details
>>> knowledge. I.e MMU API does not provide such guarantees, but drivers
>>> know how ARM MMU code is working internally and drivers depend on
>>> exactly this behavior. But if you are saying that it is totally fine,
>>> I'll rework the patch. No big deal. Actually, I already tried this and
>>> it is working fine.
>>>
>>>>>>> +
>>>>>>> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
>>>>>>> +       /delete-node/ phy-reset-pins;
>>>>>>
>>>>>> I suppose this is not needed as phy-reset-pins also configures the pin
>>>>>> as GPIO only.
>>>>>>
>>>>> Well, yes. This also puzzles me up, but for some reason it stops working
>>>>> if I leave this node intact. Looks like I need to look at this deeper
>>>>> before posting the next version.
>>>>
>>>> Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
>>>> misbehave, can you check if this patch fixes it (there is a bug in the
>>>> line "return msm_gpio_direction_input(dev, gpio);", it should become
>>>> just "msm_gpio_direction_input(dev, gpio);").
>>>>
>>>> I had the exact same issue with the gpio-regulator driver and this was
>>>> the solution I ended up going with.
>>>>
>>>> https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787db0@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
>>>> [lore[.]kernel[.]org]
>>>
>>> It is exactly this. With your patch I don't need to /delete-node/
>>> anymore. I'll add a comment in the cover message that this series are
>>> depended on your patch.
>>
>> Please can you split the power domain and clock patches into a separate
>> series? As I'd like to depend on them for the next revision of my
>> series, and we'd otherwise have a cyclical dependency.
> 
> Of course.
> 
> As I understood, you are interested in "clk: qcom: clear div mask before
> assigning a new divider" and "clk: qcom: add support for power domains
> uclass", correct?

Yes. I tried the power domain stuff out on SMD845 today and ran into 
quite a few issues. Specifically as a lot of the devices reference the 
rpmhpd power domain which we don't support (and don't *need* to support) 
in U-Boot. I'm not sure what the best way forward will be for this. 
Maybe a "nop" power domain driver?

Do you have the same issues on sm8150?
> 
> 

-- 
// Caleb (they/them)

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Volodymyr Babchuk]

Caleb Connolly <caleb.connolly@linaro.org> writes:

> On 11/03/2024 18:23, Volodymyr Babchuk wrote:
>> Hi Caleb,
>> Caleb Connolly <caleb.connolly@linaro.org> writes:
>> 
>>> On 06/03/2024 21:24, Volodymyr Babchuk wrote:
>>>>
>>>> Hi Caleb,
>>>>
>>>> Caleb Connolly <caleb.connolly@linaro.org> writes:
>>>>
>>>> [...]
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&tlmm {
>>>>>>>> +       /* U-Boot pinctrl driver does not understand multiple tiles */
>>>>>>>> +       reg = <0x0 0x03000000 0x0 0x1000000>;
>>>>>>>> +       /delete-property/ reg-names;
>>>>>>>
>>>>>>> This won't be needed if we can make the tiles offset in the pinctrl
>>>>>>> driver compatible:
>>>>>>>
>>>>>>> #define WEST   0x00000000
>>>>>>> #define EAST   0x00400000
>>>>>>> #define NORTH  0x00800000
>>>>>>> #define SOUTH  0x00C00000
>>>>>>
>>>>>> Hmm, I assume that in this case pinctrl driver should map all the four
>>>>>> tiles independently? Are there guarantees in U-Boot that four separate
>>>>>> memory regions will be mapped into virtual memory with the same relative
>>>>>> positions? Linux clearly don't make such guarantees.
>>>>>
>>>>> U-Boot doesn't use virtual addresses on arm platforms, it only goes as
>>>>> far as reading the address from DT, nothing else, so this is totally
>>>>> fine and is how the other SoCs do it.
>>>>
>>>> For me it looks like we are depending on implementation details
>>>> knowledge. I.e MMU API does not provide such guarantees, but drivers
>>>> know how ARM MMU code is working internally and drivers depend on
>>>> exactly this behavior. But if you are saying that it is totally fine,
>>>> I'll rework the patch. No big deal. Actually, I already tried this and
>>>> it is working fine.
>>>>
>>>>>>>> +
>>>>>>>> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
>>>>>>>> +       /delete-node/ phy-reset-pins;
>>>>>>>
>>>>>>> I suppose this is not needed as phy-reset-pins also configures the pin
>>>>>>> as GPIO only.
>>>>>>>
>>>>>> Well, yes. This also puzzles me up, but for some reason it stops working
>>>>>> if I leave this node intact. Looks like I need to look at this deeper
>>>>>> before posting the next version.
>>>>>
>>>>> Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
>>>>> misbehave, can you check if this patch fixes it (there is a bug in the
>>>>> line "return msm_gpio_direction_input(dev, gpio);", it should become
>>>>> just "msm_gpio_direction_input(dev, gpio);").
>>>>>
>>>>> I had the exact same issue with the gpio-regulator driver and this was
>>>>> the solution I ended up going with.
>>>>>
>>>>> https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787db0@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
>>>>> [lore[.]kernel[.]org]
>>>>
>>>> It is exactly this. With your patch I don't need to /delete-node/
>>>> anymore. I'll add a comment in the cover message that this series are
>>>> depended on your patch.
>>>
>>> Please can you split the power domain and clock patches into a separate
>>> series? As I'd like to depend on them for the next revision of my
>>> series, and we'd otherwise have a cyclical dependency.
>> Of course.
>> As I understood, you are interested in "clk: qcom: clear div mask
>> before
>> assigning a new divider" and "clk: qcom: add support for power domains
>> uclass", correct?
>
> Yes.

Okay, I'll send it today.

> I tried the power domain stuff out on SMD845 today and ran into
> quite a few issues. Specifically as a lot of the devices reference the
> rpmhpd power domain which we don't support (and don't *need* to
> support) in U-Boot. I'm not sure what the best way forward will be for
> this. Maybe a "nop" power domain driver?

Are you sure that they are not required?

"nop" power domain always is the option. Especially if it prints some
warning about an unknown device. I had quite a lot of issues with clock and
pin drivers that silently ignore unknown devices...

> Do you have the same issues on sm8150?

Yes and no. No, because I was lucky so far and devices I tried to use in
U-Boot does not require rpmhpd. Looking at DTS, I may only encounter
issues with sdhc_2, which requires rpmhpd for some reason. Also UFS
requires clock from rpmhcc.

And "yes", because I have found root cause for my troubles with UFS in
Linux kernel, when I am skipping hyp.mbn. This is not strictly related
to U-Boot, but you may be interested in this: apparently Qualcomm's
hypervisor enables access to RPM (maybe brings it out of reset?). cmd-db
shared memory region can't be accessed if I skip the hypervisor and try
to boot directly into Linux. So now I am looking for ways to enable it.

-- 
WBR, Volodymyr

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Volodymyr Babchuk]

Hi,

Volodymyr Babchuk <volodymyr_babchuk@epam.com> writes:

> Caleb Connolly <caleb.connolly@linaro.org> writes:
>
>> On 11/03/2024 18:23, Volodymyr Babchuk wrote:
>>> Hi Caleb,
>>> Caleb Connolly <caleb.connolly@linaro.org> writes:
>>> 
>>>> On 06/03/2024 21:24, Volodymyr Babchuk wrote:
>>>>>
>>>>> Hi Caleb,
>>>>>
>>>>> Caleb Connolly <caleb.connolly@linaro.org> writes:
>>>>>
>>>>> [...]
>>>>>>>>> +};
>>>>>>>>> +
>>>>>>>>> +&tlmm {
>>>>>>>>> +       /* U-Boot pinctrl driver does not understand multiple tiles */
>>>>>>>>> +       reg = <0x0 0x03000000 0x0 0x1000000>;
>>>>>>>>> +       /delete-property/ reg-names;
>>>>>>>>
>>>>>>>> This won't be needed if we can make the tiles offset in the pinctrl
>>>>>>>> driver compatible:
>>>>>>>>
>>>>>>>> #define WEST   0x00000000
>>>>>>>> #define EAST   0x00400000
>>>>>>>> #define NORTH  0x00800000
>>>>>>>> #define SOUTH  0x00C00000
>>>>>>>
>>>>>>> Hmm, I assume that in this case pinctrl driver should map all the four
>>>>>>> tiles independently? Are there guarantees in U-Boot that four separate
>>>>>>> memory regions will be mapped into virtual memory with the same relative
>>>>>>> positions? Linux clearly don't make such guarantees.
>>>>>>
>>>>>> U-Boot doesn't use virtual addresses on arm platforms, it only goes as
>>>>>> far as reading the address from DT, nothing else, so this is totally
>>>>>> fine and is how the other SoCs do it.
>>>>>
>>>>> For me it looks like we are depending on implementation details
>>>>> knowledge. I.e MMU API does not provide such guarantees, but drivers
>>>>> know how ARM MMU code is working internally and drivers depend on
>>>>> exactly this behavior. But if you are saying that it is totally fine,
>>>>> I'll rework the patch. No big deal. Actually, I already tried this and
>>>>> it is working fine.
>>>>>
>>>>>>>>> +
>>>>>>>>> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
>>>>>>>>> +       /delete-node/ phy-reset-pins;
>>>>>>>>
>>>>>>>> I suppose this is not needed as phy-reset-pins also configures the pin
>>>>>>>> as GPIO only.
>>>>>>>>
>>>>>>> Well, yes. This also puzzles me up, but for some reason it stops working
>>>>>>> if I leave this node intact. Looks like I need to look at this deeper
>>>>>>> before posting the next version.
>>>>>>
>>>>>> Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
>>>>>> misbehave, can you check if this patch fixes it (there is a bug in the
>>>>>> line "return msm_gpio_direction_input(dev, gpio);", it should become
>>>>>> just "msm_gpio_direction_input(dev, gpio);").
>>>>>>
>>>>>> I had the exact same issue with the gpio-regulator driver and this was
>>>>>> the solution I ended up going with.
>>>>>>
>>>>>> https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787db0@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
>>>>>> [lore[.]kernel[.]org]
>>>>>
>>>>> It is exactly this. With your patch I don't need to /delete-node/
>>>>> anymore. I'll add a comment in the cover message that this series are
>>>>> depended on your patch.
>>>>
>>>> Please can you split the power domain and clock patches into a separate
>>>> series? As I'd like to depend on them for the next revision of my
>>>> series, and we'd otherwise have a cyclical dependency.
>>> Of course.
>>> As I understood, you are interested in "clk: qcom: clear div mask
>>> before
>>> assigning a new divider" and "clk: qcom: add support for power domains
>>> uclass", correct?
>>
>> Yes.
>
> Okay, I'll send it today.
>
>> I tried the power domain stuff out on SMD845 today and ran into
>> quite a few issues. Specifically as a lot of the devices reference the
>> rpmhpd power domain which we don't support (and don't *need* to
>> support) in U-Boot. I'm not sure what the best way forward will be for
>> this. Maybe a "nop" power domain driver?
>
> Are you sure that they are not required?
>
> "nop" power domain always is the option. Especially if it prints some
> warning about an unknown device. I had quite a lot of issues with clock and
> pin drivers that silently ignore unknown devices...
>
>> Do you have the same issues on sm8150?
>
> Yes and no. No, because I was lucky so far and devices I tried to use in
> U-Boot does not require rpmhpd. Looking at DTS, I may only encounter
> issues with sdhc_2, which requires rpmhpd for some reason. Also UFS
> requires clock from rpmhcc.
>
> And "yes", because I have found root cause for my troubles with UFS in
> Linux kernel, when I am skipping hyp.mbn. This is not strictly related
> to U-Boot, but you may be interested in this: apparently Qualcomm's
> hypervisor enables access to RPM (maybe brings it out of reset?). cmd-db
> shared memory region can't be accessed if I skip the hypervisor and try
> to boot directly into Linux. So now I am looking for ways to enable it.

I want to share the solution, in case if someone got the same
problem. It all boiled down to correct memory attributes. Qualcomm's
hypervisor mapped cmd-db shared memory as non-cached in Stage 2
translation table, while Linux maps it as cacheable in Stage 1. Thus,
the final memory attribute was "non-cacheable".

Xen, on other hand, used default mapping which is normal cacheable
memory. And of course this lead to cacheable accesses to cmd-db. For
some reason this caused the hardware error, which manifested as a secure
interrupt (while I expected SError at most), which in turn led to
endless loop somewhere in TZ.

I am going to fix this by applying the correct mappings in the Linux
cmd-db driver. Plan B is to have workaround in Xen, but I really want to
avoid this.

Right now I have a working Xen that is able to boot Dom0 straight to
console, if anyone interested.

-- 
WBR, Volodymyr

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Caleb Connolly]

On 19/03/2024 21:18, Volodymyr Babchuk wrote:
> 
> Hi,
> 
> Volodymyr Babchuk <volodymyr_babchuk@epam.com> writes:
> 
>> Caleb Connolly <caleb.connolly@linaro.org> writes:
>>
>>> On 11/03/2024 18:23, Volodymyr Babchuk wrote:
>>>> Hi Caleb,
>>>> Caleb Connolly <caleb.connolly@linaro.org> writes:
>>>>
>>>>> On 06/03/2024 21:24, Volodymyr Babchuk wrote:
>>>>>>
>>>>>> Hi Caleb,
>>>>>>
>>>>>> Caleb Connolly <caleb.connolly@linaro.org> writes:
>>>>>>
>>>>>> [...]
>>>>>>>>>> +};
>>>>>>>>>> +
>>>>>>>>>> +&tlmm {
>>>>>>>>>> +       /* U-Boot pinctrl driver does not understand multiple tiles */
>>>>>>>>>> +       reg = <0x0 0x03000000 0x0 0x1000000>;
>>>>>>>>>> +       /delete-property/ reg-names;
>>>>>>>>>
>>>>>>>>> This won't be needed if we can make the tiles offset in the pinctrl
>>>>>>>>> driver compatible:
>>>>>>>>>
>>>>>>>>> #define WEST   0x00000000
>>>>>>>>> #define EAST   0x00400000
>>>>>>>>> #define NORTH  0x00800000
>>>>>>>>> #define SOUTH  0x00C00000
>>>>>>>>
>>>>>>>> Hmm, I assume that in this case pinctrl driver should map all the four
>>>>>>>> tiles independently? Are there guarantees in U-Boot that four separate
>>>>>>>> memory regions will be mapped into virtual memory with the same relative
>>>>>>>> positions? Linux clearly don't make such guarantees.
>>>>>>>
>>>>>>> U-Boot doesn't use virtual addresses on arm platforms, it only goes as
>>>>>>> far as reading the address from DT, nothing else, so this is totally
>>>>>>> fine and is how the other SoCs do it.
>>>>>>
>>>>>> For me it looks like we are depending on implementation details
>>>>>> knowledge. I.e MMU API does not provide such guarantees, but drivers
>>>>>> know how ARM MMU code is working internally and drivers depend on
>>>>>> exactly this behavior. But if you are saying that it is totally fine,
>>>>>> I'll rework the patch. No big deal. Actually, I already tried this and
>>>>>> it is working fine.
>>>>>>
>>>>>>>>>> +
>>>>>>>>>> +       /* U-Boot ethernet driver wants to drive reset as GPIO */
>>>>>>>>>> +       /delete-node/ phy-reset-pins;
>>>>>>>>>
>>>>>>>>> I suppose this is not needed as phy-reset-pins also configures the pin
>>>>>>>>> as GPIO only.
>>>>>>>>>
>>>>>>>> Well, yes. This also puzzles me up, but for some reason it stops working
>>>>>>>> if I leave this node intact. Looks like I need to look at this deeper
>>>>>>>> before posting the next version.
>>>>>>>
>>>>>>> Possibly the pinconf defined in the phy-reset-pins node causes U-Boot to
>>>>>>> misbehave, can you check if this patch fixes it (there is a bug in the
>>>>>>> line "return msm_gpio_direction_input(dev, gpio);", it should become
>>>>>>> just "msm_gpio_direction_input(dev, gpio);").
>>>>>>>
>>>>>>> I had the exact same issue with the gpio-regulator driver and this was
>>>>>>> the solution I ended up going with.
>>>>>>>
>>>>>>> https://urldefense.com/v3/__https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-7-4071c0787db0@linaro.org/__;!!GF_29dbcQIUBPA!xFhZe7DKgRbr63sirEJLuH-B0AnGs7jvx8tdJPKLTgFuZ3I3_zpVml7l23G-_vJO_JiUR-wUO4GMPJFcE-8p50H3pf7nbxit$
>>>>>>> [lore[.]kernel[.]org]
>>>>>>
>>>>>> It is exactly this. With your patch I don't need to /delete-node/
>>>>>> anymore. I'll add a comment in the cover message that this series are
>>>>>> depended on your patch.
>>>>>
>>>>> Please can you split the power domain and clock patches into a separate
>>>>> series? As I'd like to depend on them for the next revision of my
>>>>> series, and we'd otherwise have a cyclical dependency.
>>>> Of course.
>>>> As I understood, you are interested in "clk: qcom: clear div mask
>>>> before
>>>> assigning a new divider" and "clk: qcom: add support for power domains
>>>> uclass", correct?
>>>
>>> Yes.
>>
>> Okay, I'll send it today.
>>
>>> I tried the power domain stuff out on SMD845 today and ran into
>>> quite a few issues. Specifically as a lot of the devices reference the
>>> rpmhpd power domain which we don't support (and don't *need* to
>>> support) in U-Boot. I'm not sure what the best way forward will be for
>>> this. Maybe a "nop" power domain driver?
>>
>> Are you sure that they are not required?
>>
>> "nop" power domain always is the option. Especially if it prints some
>> warning about an unknown device. I had quite a lot of issues with clock and
>> pin drivers that silently ignore unknown devices...
>>
>>> Do you have the same issues on sm8150?
>>
>> Yes and no. No, because I was lucky so far and devices I tried to use in
>> U-Boot does not require rpmhpd. Looking at DTS, I may only encounter
>> issues with sdhc_2, which requires rpmhpd for some reason. Also UFS
>> requires clock from rpmhcc.
>>
>> And "yes", because I have found root cause for my troubles with UFS in
>> Linux kernel, when I am skipping hyp.mbn. This is not strictly related
>> to U-Boot, but you may be interested in this: apparently Qualcomm's
>> hypervisor enables access to RPM (maybe brings it out of reset?). cmd-db
>> shared memory region can't be accessed if I skip the hypervisor and try
>> to boot directly into Linux. So now I am looking for ways to enable it.
> 
> I want to share the solution, in case if someone got the same
> problem. It all boiled down to correct memory attributes. Qualcomm's
> hypervisor mapped cmd-db shared memory as non-cached in Stage 2
> translation table, while Linux maps it as cacheable in Stage 1. Thus,
> the final memory attribute was "non-cacheable".
> 
> Xen, on other hand, used default mapping which is normal cacheable
> memory. And of course this lead to cacheable accesses to cmd-db. For
> some reason this caused the hardware error, which manifested as a secure
> interrupt (while I expected SError at most), which in turn led to
> endless loop somewhere in TZ.

ohh, nice find! I guess if Linux started sending bogus data to the rpmh
this could definitely lead to some XPU violation or another excuse for a
secure interrupt...
> 
> I am going to fix this by applying the correct mappings in the Linux
> cmd-db driver. Plan B is to have workaround in Xen, but I really want to
> avoid this.

I agree this is definitely a Linux bug, it should make sense to fix it
there.
> 
> Right now I have a working Xen that is able to boot Dom0 straight to
> console, if anyone interested.

Awesome! Yeah I'd love to take a look :D
> 

-- 
// Caleb (they/them)

Re: [PATCH v2 8/8] board: add support for Qualcomm SA8155P-ADP board

[Caleb Connolly]

On 06/03/2024 00:53, Volodymyr Babchuk wrote:
> SA8155P Automotive Development Platform is Qualcomm SA8155-based board
> for developers. The nice thing that it has unlocked loaders with test
> keys support, which means that U-Boot for this platform can be
> launched at earlier stages.
> 
> This patch adds basic board support with only serial port and
> networking operation. I am using U-Boot to ease up Xen porting onto
> this board, so I am mostly interesting in booting U-Boot in EL2. But
> more conventional setup with Android boot image is supported as well.
> 
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> 
> ---
> 
> Changes in v2:
>  - Rebased onto qcom-next branch
>  - Removed unnecessary files thanks to generic qualcomm board support
>  - Enabled CONFIG_REMAKE_ELF (this removes one extra step in the
>    readme)
> 
>  arch/arm/dts/sa8155p-adp-u-boot.dtsi   | 30 +++++++++
>  board/qualcomm/sa8155p-adp/MAINTAINERS |  5 ++
>  configs/sa8155p_adp_defconfig          | 35 +++++++++++
>  doc/board/qualcomm/index.rst           |  1 +
>  doc/board/qualcomm/sa8155p-adp.rst     | 87 ++++++++++++++++++++++++++
>  5 files changed, 158 insertions(+)
>  create mode 100644 arch/arm/dts/sa8155p-adp-u-boot.dtsi
>  create mode 100644 board/qualcomm/sa8155p-adp/MAINTAINERS
>  create mode 100644 configs/sa8155p_adp_defconfig
>  create mode 100644 doc/board/qualcomm/sa8155p-adp.rst
> 
> diff --git a/arch/arm/dts/sa8155p-adp-u-boot.dtsi b/arch/arm/dts/sa8155p-adp-u-boot.dtsi
> new file mode 100644
> index 0000000000..ffbf0933c7
> --- /dev/null
> +++ b/arch/arm/dts/sa8155p-adp-u-boot.dtsi
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Qualcomm SA8155P-ADP device tree fixups for U-BOot
> + *
> + * Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> + * Copyright (c) 2024 EPAM Systems.
> + */
> +
> +/ {
> +	/* Populate memory node with actual memory configuration */
> +	memory@80000000 {
> +		reg = <0x00 0x80000000 0x00 0x39900000>,
> +		<0x02 0x0        0x1  0x7fd00000>,
> +		<0x00 0xC0000000 0x1  0x40000000>;
> +	};
> +};
> +
> +&ethernet {
> +	/* Ethernet driver tries to find reset by name */
> +	reset-names = "emac";
> +};
> +
> +&tlmm {
> +	/* U-Boot pinctrl driver does not understand multiple tiles */
> +	reg = <0x0 0x03000000 0x0 0x1000000>;
could you follow the other pinctrl drivers and just define the tile
offsets relative to the first tile specified in DT? Otherwise every
sm8150 board will need this DTS hack. Fixing this in the driver would
also make it possible to use the same DT to boot Linux which is quite
useful.
> +	/delete-property/ reg-names;
There's no need to drop this property, and Linux depends on it.

With those changes:

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
> +
> +	/* U-Boot ethernet driver wants to drive reset as GPIO */
> +	/delete-node/ phy-reset-pins;
> +};
> diff --git a/board/qualcomm/sa8155p-adp/MAINTAINERS b/board/qualcomm/sa8155p-adp/MAINTAINERS
> new file mode 100644
> index 0000000000..03fac84f51
> --- /dev/null
> +++ b/board/qualcomm/sa8155p-adp/MAINTAINERS
> @@ -0,0 +1,5 @@
> +Qualcomm SA8155P Automotive Development Platform
> +M:	Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> +S:	Maintained
> +F:	board/qualcomm/sa8155p-adp/
> +F:	configs/sa8155p-adp_defconfig
> diff --git a/configs/sa8155p_adp_defconfig b/configs/sa8155p_adp_defconfig
> new file mode 100644
> index 0000000000..b6969767f8
> --- /dev/null
> +++ b/configs/sa8155p_adp_defconfig
> @@ -0,0 +1,35 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=19000000
> +CONFIG_POSITION_INDEPENDENT=y
> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> +CONFIG_ARCH_SNAPDRAGON=y
> +CONFIG_TEXT_BASE=0x85710000
> +CONFIG_DEFAULT_DEVICE_TREE="qcom/sa8155p-adp"
> +CONFIG_IDENT_STRING="\nQualcomm SA8155P-ADP"
> +CONFIG_SYS_LOAD_ADDR=0x85710000
> +CONFIG_REMAKE_ELF=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_SYS_CBSIZE=512
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_HUSH_PARSER=y
> +CONFIG_OF_UPSTREAM=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_CLK=y
> +CONFIG_CLK_QCOM_SM8150=y
> +CONFIG_MSM_GPIO=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_PHY_MICREL_KSZ90X1=y
> +CONFIG_DM_MDIO=y
> +CONFIG_DM_ETH_PHY=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_QCOM=y
> +CONFIG_PHY=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCONF=y
> +CONFIG_PINCTRL_QCOM_SM8150=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_MSM_GENI_SERIAL=y
> +CONFIG_SPMI_MSM=y
> +CONFIG_LMB_MAX_REGIONS=64
> diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
> index 4955274a39..268218b05f 100644
> --- a/doc/board/qualcomm/index.rst
> +++ b/doc/board/qualcomm/index.rst
> @@ -7,5 +7,6 @@ Qualcomm
>     :maxdepth: 2
>  
>     dragonboard410c
> +   sa8155p-adp
>     board
>     debugging
> diff --git a/doc/board/qualcomm/sa8155p-adp.rst b/doc/board/qualcomm/sa8155p-adp.rst
> new file mode 100644
> index 0000000000..66db512b52
> --- /dev/null
> +++ b/doc/board/qualcomm/sa8155p-adp.rst
> @@ -0,0 +1,87 @@
> +.. SPDX-License-Identifier: BSD-3-Clause
> +.. sectionauthor:: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> +
> +SA8155P Automotive Development Platform
> +=======================================
> +
> +About
> +-----
> +This document describes the information about SA8155P Automotive
> +Development Platform aka SA8155P-ADP.
> +
> +Currently U-Boot can be booted either as Android boot image, or in EL2
> +mode, instead of hypervisor image. In the latter case it is possible
> +to use U-Boot to either boot Linux with KVM support or to boot Xen
> +Hypervisor on this board.
> +
> +Supported HW modules
> +^^^^^^^^^^^^^^^^^^^^
> +Port for this board is in early development state. Right now U-Boot
> +supports serial console and networking. No USB/fastboot or UFS support
> +yet. So it is not possible to save environment variables as
> +well. Nevertheless this is enough for development as user can download
> +all required images via TFTP.
> +
> +Installation
> +------------
> +Build
> +^^^^^
> +Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
> +
> +	$ export CROSS_COMPILE=<aarch64 toolchain prefix>
> +	$ make sa8155p_adp_defconfig
> +	$ make
> +
> +This will build ``u-boot.bin`` in the configured output directory.
> +
> +Boot in EL1 mode instead of Android boot image
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +
> +Create a dummy ramdisk image:::
> +
> +	$ echo "This is not a ramdisk" > ramdisk.img
> +
> +Compress u-boot binary:::
> +
> +	$ gzip -c u-boot.bin > u-boot.bin.gz
> +
> +Append DTB again (binary we use already have DTB embedded in, but
> +Android boot image format requires another DTB at the end of the
> +archive):::
> +
> +	$ cat u-boot.bin.gz u-boot.dtb > u-boot.bin.gz-dtb
> +
> +Now we've got everything to build android boot image:::
> +
> +	$ mkbootimg --kernel u-boot.bin.gz-dtb \
> +	--ramdisk ramdisk.img --pagesize 4096 \
> +	--base 0x80000000 -o boot.img
> +
> +Finally you can flash new boot image with fastboot:::
> +
> +	$ fastboot flash boot boot.img
> +
> +Or just boot U-Boot without flashing anything:::
> +
> +	$ fastboot boot boot.img
> +
> +Boot in EL2 mode instead of Qualcomm's hypervisor stub
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +This approach ensures that U-Boot is booted in EL2 and it is possible
> +to run virtualization software (like Xen or KVM) on the board. You
> +must understand that this approach breaks Qualcomm's boot chain. You
> +will not be able to call all subsequent loaders, so you will not be
> +able to use fastboot for example. Use this approach only if you want
> +to experiment with virtualization on SA8155P-ADP.
> +
> +U-Boot ELF file needs to be signed with test keys. `qtestsign
> +<https://github.com/msm8916-mainline/qtestsign>`_ tool can be used ::
> +
> +	$ ../qtestsign/qtestsign.py -v6 hyp u-boot.elf
> +
> +Resulting ``u-boot-test-signed.mbn`` then can be written to the
> +board. Easiest way is to use ``edl`` tool: ::
> +
> +	$ ../edl/edl w hyp_a u-boot-test-signed.mbn --memory=ufs --lun=4
> +
> +Be sure to backup existing hyp_a loader before flashing U-Boot.

-- 
// Caleb (they/them)