[U-Boot-Users] PCI OHCI / testing-USB branch

[U-Boot-Users] PCI OHCI / testing-USB branch

[Matthias Fuchs]

Hi,

is someone currently working on the testing-USB branch? Does it contain
the most up to date USB code?
I have to add support for a PCI OHCI controller on a 405 board. This will 
result in some modifications (endianess + bus offsets) of drivers/usb_ohci.c.

Is someone else using a PCI OHCI controller on a board that I might have 
missed to check?

Matthias

[U-Boot-Users] PCI OHCI / testing-USB branch

[Markus Klotzbücher]

Dear Matthias,

Matthias Fuchs <matthias.fuchs@esd-electronics.com> writes:

> is someone currently working on the testing-USB branch? Does it contain
> the most up to date USB code?

Yes, and no. I've got a couple of patches for the generic OHCI driver
which have not been merged yet, because I want to do some more
testing. I'll try to do this soon.

> I have to add support for a PCI OHCI controller on a 405 board. This will 
> result in some modifications (endianess + bus offsets) of drivers/usb_ohci.c.

Ok.

> Is someone else using a PCI OHCI controller on a board that I might have 
> missed to check?

Not that I know of.


Regards

Markus Klotzbuecher

[U-Boot-Users] PCI OHCI / testing-USB branch

[Robert Delien]

Dear Markus,

> > is someone currently working on the testing-USB branch? Does it 
contain
> > the most up to date USB code?
> 
> Yes, and no. I've got a couple of patches for the generic OHCI driver
> which have not been merged yet, because I want to do some more
> testing. I'll try to do this soon.

I was working on that too, but I only started today, so I'm glad I'm 
reading this posting now instead of two weeks later ;-). Could you please 
send me your patches, or even post them here? I could help you debugging 
it...

> > I have to add support for a PCI OHCI controller on a 405 board. This 
will 
> > result in some modifications (endianess + bus offsets) of
> > drivers/usb_ohci.c.

I'm currently working on the NXP (previously Philips Semiconductors) 
PNX8535 SoC with a MIPS 4Kec core in it. We're running it in little endian 
mode, but I'm to keep everything big endian compatible using readl/writel 
from io.h.

> > Is someone else using a PCI OHCI controller on a board that I might 
have 
> > missed to check?

Yes, I am, but we haven't pushed back our contributions yet. We're still 
working on U-Boot 1.1.3, while at the same time I'm porting 1.1.4. 
Unfortunately 1.1.5 came before I finished and scr*wed everything up 
again.
I could send you my work, but I doubt if one day of work on a 1.1.3 file 
would be of any help ;-)

With kind regards,

        Robert.
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[U-Boot-Users] PCI OHCI / testing-USB branch

[Markus Klotzbücher]

Dear Robert,

Robert Delien <robert.delien@nxp.com> writes:

>> > is someone currently working on the testing-USB branch? Does it
> contain
>> > the most up to date USB code?
>>
>> Yes, and no. I've got a couple of patches for the generic OHCI
> driver
>> which have not been merged yet, because I want to do some more
>> testing. I'll try to do this soon.
> I was working on that too, but I only started today, so I'm glad I'm
> reading this posting now instead of two weeks later ;-). Could you
> please send me your patches, or even post them here? I could help you
> debugging it...

It's now all in the testing-USB branch. Please also see
doc/README.generic_usb_ohci for a brief description.

Regards

Markus Klotzbuecher

[U-Boot-Users] PCI OHCI / testing-USB branch

[Matthias Fuchs]

Hi Markus,

do you see a problem in passing a pointer to the gohci structure to 
usb_cpu_init() or at least to usb_board_init()?

In order to get the base address of my PCI OHCI controller I first have to 
find the device on the PCI bus. I think usb_board_init() is the right place 
for this. But I need &gohci to pass it back to the usb driver.

Here's is what I mean:

diff --git a/drivers/usb_ohci.c b/drivers/usb_ohci.c
index c5e4c38..8afadd1 100644
--- a/drivers/usb_ohci.c
+++ b/drivers/usb_ohci.c
@@ -1680,19 +1680,20 @@ static char ohci_inited = 0;
 
 int usb_lowlevel_init(void)
 {
+       memset (&gohci, 0, sizeof (ohci_t));
 
 #ifdef CFG_USB_OHCI_CPU_INIT
        /* cpu dependant init */
-       if(usb_cpu_init())
+       if(usb_cpu_init(&gohci))
                return -1;
 #endif
 
 #ifdef CFG_USB_OHCI_BOARD_INIT
        /*  board dependant init */
-       if(usb_board_init())
+       if(usb_board_init(&gohci))
                return -1;
 #endif
-       memset (&gohci, 0, sizeof (ohci_t));
+
        memset (&urb_priv, 0, sizeof (urb_priv_t));
 
        /* align the storage */
@@ -1719,8 +1720,10 @@ int usb_lowlevel_init(void)
        gohci.disabled = 1;
        gohci.sleeping = 0;
        gohci.irq = -1;
-       gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
 
+#ifdef CFG_USB_OHCI_REGS_BASE
+       gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
+#endif
        gohci.flags = 0;
        gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;


Regards
Matthias

On Tuesday 28 November 2006 14:24, Markus Klotzb?cher wrote:
> Dear Robert,
>
> Robert Delien <robert.delien@nxp.com> writes:
> >> > is someone currently working on the testing-USB branch? Does it
> >
> > contain
> >
> >> > the most up to date USB code?
> >>
> >> Yes, and no. I've got a couple of patches for the generic OHCI
> >
> > driver
> >
> >> which have not been merged yet, because I want to do some more
> >> testing. I'll try to do this soon.
> >
> > I was working on that too, but I only started today, so I'm glad I'm
> > reading this posting now instead of two weeks later ;-). Could you
> > please send me your patches, or even post them here? I could help you
> > debugging it...
>
> It's now all in the testing-USB branch. Please also see
> doc/README.generic_usb_ohci for a brief description.
>
> Regards
>
> Markus Klotzbuecher

[U-Boot-Users] PCI OHCI / testing-USB branch

[Markus Klotzbücher]

Hi Matthias,

Matthias Fuchs <matthias.fuchs@esd-electronics.com> writes:

> do you see a problem in passing a pointer to the gohci structure to 
> usb_cpu_init() or at least to usb_board_init()?
>
> In order to get the base address of my PCI OHCI controller I first have to 
> find the device on the PCI bus. I think usb_board_init() is the right place 
> for this. But I need &gohci to pass it back to the usb driver.

Thats ok with me. I think it makes sense to pass the pointer to both
board and cpu init. But please provide a proper patch.

Thanks!

Markus Klotzb?cher

[U-Boot-Users] PCI OHCI / testing-USB branch

[reckless]

Hi 

I am stuck at the position where iam not getting any data on USB bus. I am
using the ISP1562 chip on my PCI and using the OHCI code. I am able to reset
and initialize the controller as i am able to see the reset signal and High
speed chirp signal on the bus but there is no data on the bus. It shows the
invalid packet on with all 0xFF at the first time i connect the mass storage
device and running the usb reset command what could be the problem ? 
How i have to map the PCI memory ? 
I though that it could be the invalid memory access as i am taking the gohci
and hcca structure by just taking it as an array and the controller HcHcca
registers are unable to access that location it 0x7ffa0000 in my case where
my PCI memory is mapped at 0x80000000 

Need some help 
Regards


Markus Klotzb?cher-2 wrote:
> 
> Dear Matthias,
> 
> Matthias Fuchs <matthias.fuchs@esd-electronics.com> writes:
> 
>> is someone currently working on the testing-USB branch? Does it contain
>> the most up to date USB code?
> 
> Yes, and no. I've got a couple of patches for the generic OHCI driver
> which have not been merged yet, because I want to do some more
> testing. I'll try to do this soon.
> 
>> I have to add support for a PCI OHCI controller on a 405 board. This will 
>> result in some modifications (endianess + bus offsets) of
>> drivers/usb_ohci.c.
> 
> Ok.
> 
>> Is someone else using a PCI OHCI controller on a board that I might have 
>> missed to check?
> 
> Not that I know of.
> 
> 
> Regards
> 
> Markus Klotzbuecher
> 
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