From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Korsgaard Date: Mon, 17 Jun 2013 22:13:46 +0200 Subject: [U-Boot] [PATCH] am33xx: fix the ddr_cmdtctrl structure In-Reply-To: <1371477567-8418-1-git-send-email-ilya@compulab.co.il> (Ilya Ledvich's message of "Mon, 17 Jun 2013 16:59:27 +0300") References: <1371477567-8418-1-git-send-email-ilya@compulab.co.il> Message-ID: <87r4g0sdfp.fsf@dell.be.48ers.dk> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de >>>>> "Ilya" == Ilya Ledvich writes: Ilya> Fix the wrong mapping between the DDR I/O control registers on Ilya> AM33XX SoCs and the software representation in the SPL code. The Ilya> most recent public TRM defines the following DDR I/O control Ilya> registers offsets: Ilya> * ddr_cmd0_ioctrl : offset 0x44E11404 Ilya> * ddr_cmd1_ioctrl : offset 0x44E11408 Ilya> * ddr_cmd2_ioctrl : offset 0x44E1140C Ilya> * ddr_data0_ioctrl: offset 0x44E11440 Ilya> * ddr_data1_ioctrl: offset 0x44E11444 Ilya> While the struct ddr_cmdtctrl has also some reserved bits in the Ilya> beginning. The struct is mapped to the address 0x44E11404. As a Ilya> result "cm0ioctl" points to the ddr_cmd1_ioctrl register, Ilya> "cm1ioctl" to the ddr_cmd2_ioctrl and etc. Registers Ilya> ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because Ilya> of this mapping mismatch. Ilya> Signed-off-by: Ilya Ledvich Reviewed-by: Peter Korsgaard -- Bye, Peter Korsgaard