From: Andreas Schwab <schwab@linux-m68k.org>
To: Green Wan <green.wan@sifive.com>
Cc: bmeng.cn@gmail.com, Rick Chen <rick@andestech.com>,
Leo <ycliang@andestech.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup.patel@wdc.com>,
Atish Patra <atish.patra@wdc.com>,
Pragnesh Patel <pragnesh.patel@sifive.com>,
Lukasz Majewski <lukma@denx.de>,
u-boot@lists.denx.de
Subject: Re: [PATCH v12 2/8] drivers: clk: add fu740 support
Date: Tue, 15 Jun 2021 21:12:27 +0200 [thread overview]
Message-ID: <87sg1juelg.fsf@igel.home> (raw)
In-Reply-To: <20210527135215.370524-3-green.wan@sifive.com> (Green Wan's message of "Thu, 27 May 2021 06:52:08 -0700")
On Mai 27 2021, Green Wan wrote:
> +/* List of clock controls provided by the PRCI */
> +struct __prci_clock __prci_init_clocks_fu740[] = {
> + [PRCI_CLK_COREPLL] = {
> + .name = "corepll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_corepll_data,
> + },
> + [PRCI_CLK_DDRPLL] = {
> + .name = "ddrpll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_ddrpll_data,
> + },
> + [PRCI_CLK_GEMGXLPLL] = {
> + .name = "gemgxlpll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_gemgxlpll_data,
> + },
> + [PRCI_CLK_DVFSCOREPLL] = {
> + .name = "dvfscorepll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_dvfscorepll_data,
> + },
> + [PRCI_CLK_HFPCLKPLL] = {
> + .name = "hfpclkpll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_hfpclkpll_data,
> + },
> + [PRCI_CLK_CLTXPLL] = {
> + .name = "cltxpll",
> + .parent_name = "hfclk",
> + .ops = &sifive_fu740_prci_wrpll_clk_ops,
> + .pwd = &__prci_cltxpll_data,
> + },
> + [PRCI_CLK_TLCLK] = {
> + .name = "tlclk",
> + .parent_name = "corepll",
> + .ops = &sifive_fu740_prci_tlclksel_clk_ops,
> + },
> + [PRCI_CLK_PCLK] = {
> + .name = "pclk",
> + .parent_name = "hfpclkpll",
> + .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
> + },
> + [PRCI_CLK_PCIEAUX] {
> + .name = "pciaux",
Shouldn't that be called "pcieaux"?
Andreas.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
next prev parent reply other threads:[~2021-06-15 23:45 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-27 13:52 [PATCH v12 0/8] Add FU740 chip and HiFive Unmatched board support Green Wan
2021-05-27 13:52 ` [PATCH v12 1/8] riscv: cpu: fu740: Add support for cpu fu740 Green Wan
2021-05-27 13:52 ` [PATCH v12 2/8] drivers: clk: add fu740 support Green Wan
2021-06-15 19:12 ` Andreas Schwab [this message]
2021-06-28 10:21 ` Green Wan
2021-05-27 13:52 ` [PATCH v12 3/8] drivers: ram: sifive: rename fu540_ddr and " Green Wan
2021-05-27 13:52 ` [PATCH v12 4/8] drivers: pci: add pcie support for fu740 Green Wan
2021-05-27 13:52 ` [PATCH v12 5/8] riscv: dts: add fu740 support Green Wan
2021-05-27 13:52 ` [PATCH v12 6/8] riscv: dts: add SiFive Unmatched board support Green Wan
2021-05-27 13:52 ` [PATCH v12 7/8] board: sifive: add HiFive " Green Wan
2021-05-27 13:52 ` [PATCH v12 8/8] riscv: cpu: fu740: clear feature disable CSR Green Wan
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