[U-Boot] [PATCH 1/2] sunxi: clock: Fix EHCI and OHCI clocks on A64

[U-Boot] [PATCH 1/2] sunxi: clock: Fix EHCI and OHCI clocks on A64

[Vasily Khoruzhick]

EHCI0 is bit 24, EHCI1 - 25, OHCI0 - 28, OHCI1 - 29

Fixed commit fef73766d9ad ("sunxi: clock: Fix OHCI clock gating for H3/H5")

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 8acf79fbba..8afeaf872e 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -280,8 +280,10 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI1	26
 #define AHB_GATE_OFFSET_USB_EHCI0	24
 #elif defined(CONFIG_MACH_SUN50I)
-#define AHB_GATE_OFFSET_USB_OHCI0	29
-#define AHB_GATE_OFFSET_USB_EHCI0	25
+#define AHB_GATE_OFFSET_USB_OHCI0	28
+#define AHB_GATE_OFFSET_USB_OHCI1	29
+#define AHB_GATE_OFFSET_USB_EHCI0	24
+#define AHB_GATE_OFFSET_USB_EHCI1	25
 #else
 #define AHB_GATE_OFFSET_USB_OHCI1	30
 #define AHB_GATE_OFFSET_USB_OHCI0	29
-- 
2.17.1

[U-Boot] [PATCH 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Vasily Khoruzhick]

On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
clock when OHCI1 is in use.

Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
 drivers/usb/host/ohci-sunxi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index ce2b47a5c4..5661557a3d 100644
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
 	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
 	struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
 	int extra_ahb_gate_mask = 0;
+	int extra_usb_gate_mask = 0;
 	int phys, ret;
 
 	priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
@@ -78,13 +79,17 @@ no_phy:
 	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
 	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#ifdef CONFIG_MACH_SUN50I
+	extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#endif
 	priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
 	extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
 	priv->usb_gate_mask <<= phys;
 
 	setbits_le32(&priv->ccm->ahb_gate0,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
-	setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
+	setbits_le32(&priv->ccm->usb_clk_cfg,
+		     priv->usb_gate_mask | extra_usb_gate_mask);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 	setbits_le32(&priv->ccm->ahb_reset0_cfg,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
-- 
2.17.1

[U-Boot] [PATCH 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Marek Vasut]

On 06/06/2018 05:38 AM, Vasily Khoruzhick wrote:
> On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
> clock when OHCI1 is in use.
> 
> Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")
> 
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
>  drivers/usb/host/ohci-sunxi.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
> index ce2b47a5c4..5661557a3d 100644
> --- a/drivers/usb/host/ohci-sunxi.c
> +++ b/drivers/usb/host/ohci-sunxi.c
> @@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
>  	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
>  	struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
>  	int extra_ahb_gate_mask = 0;
> +	int extra_usb_gate_mask = 0;
>  	int phys, ret;
>  
>  	priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> @@ -78,13 +79,17 @@ no_phy:
>  	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
>  #endif
>  	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
> +#ifdef CONFIG_MACH_SUN50I
> +	extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
> +#endif
>  	priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
>  	extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
>  	priv->usb_gate_mask <<= phys;
>  
>  	setbits_le32(&priv->ccm->ahb_gate0,
>  		     priv->ahb_gate_mask | extra_ahb_gate_mask);
> -	setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
> +	setbits_le32(&priv->ccm->usb_clk_cfg,
> +		     priv->usb_gate_mask | extra_usb_gate_mask);

Why is the SoC / compatible information not coming from DT instead ? Why
is the driver polluted by more ifdefs ?

>  #ifdef CONFIG_SUNXI_GEN_SUN6I
>  	setbits_le32(&priv->ccm->ahb_reset0_cfg,
>  		     priv->ahb_gate_mask | extra_ahb_gate_mask);
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Jagan Teki]

On Wed, Jun 6, 2018 at 9:08 AM, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
> On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
> clock when OHCI1 is in use.
>
> Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")
>
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
>  drivers/usb/host/ohci-sunxi.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
> index ce2b47a5c4..5661557a3d 100644
> --- a/drivers/usb/host/ohci-sunxi.c
> +++ b/drivers/usb/host/ohci-sunxi.c
> @@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
>         struct ohci_sunxi_priv *priv = dev_get_priv(dev);
>         struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
>         int extra_ahb_gate_mask = 0;
> +       int extra_usb_gate_mask = 0;
>         int phys, ret;
>
>         priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> @@ -78,13 +79,17 @@ no_phy:
>         extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
>  #endif
>         priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
> +#ifdef CONFIG_MACH_SUN50I
> +       extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;

This look reassigning same clock to twice?

[U-Boot] [PATCH 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Vasily Khoruzhick]

On Wed, Jun 6, 2018 at 2:02 AM, Marek Vasut <marex@denx.de> wrote:
> On 06/06/2018 05:38 AM, Vasily Khoruzhick wrote:
>> On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
>> clock when OHCI1 is in use.
>>
>> Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")
>>
>> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
>> ---
>>  drivers/usb/host/ohci-sunxi.c | 7 ++++++-
>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
>> index ce2b47a5c4..5661557a3d 100644
>> --- a/drivers/usb/host/ohci-sunxi.c
>> +++ b/drivers/usb/host/ohci-sunxi.c
>> @@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
>>       struct ohci_sunxi_priv *priv = dev_get_priv(dev);
>>       struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
>>       int extra_ahb_gate_mask = 0;
>> +     int extra_usb_gate_mask = 0;
>>       int phys, ret;
>>
>>       priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>> @@ -78,13 +79,17 @@ no_phy:
>>       extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
>>  #endif
>>       priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>> +#ifdef CONFIG_MACH_SUN50I
>> +     extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>> +#endif
>>       priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
>>       extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
>>       priv->usb_gate_mask <<= phys;
>>
>>       setbits_le32(&priv->ccm->ahb_gate0,
>>                    priv->ahb_gate_mask | extra_ahb_gate_mask);
>> -     setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
>> +     setbits_le32(&priv->ccm->usb_clk_cfg,
>> +                  priv->usb_gate_mask | extra_usb_gate_mask);
>
> Why is the SoC / compatible information not coming from DT instead ? Why
> is the driver polluted by more ifdefs ?

Because this platform doesn't have DM clock driver yet. This code will
be removed once this driver is implemented.

>>  #ifdef CONFIG_SUNXI_GEN_SUN6I
>>       setbits_le32(&priv->ccm->ahb_reset0_cfg,
>>                    priv->ahb_gate_mask | extra_ahb_gate_mask);
>>
>
>
> --
> Best regards,
> Marek Vasut

[U-Boot] [PATCH 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Vasily Khoruzhick]

On Wed, Jun 6, 2018 at 6:56 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> On Wed, Jun 6, 2018 at 9:08 AM, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
>> On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
>> clock when OHCI1 is in use.
>>
>> Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")
>>
>> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
>> ---
>>  drivers/usb/host/ohci-sunxi.c | 7 ++++++-
>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
>> index ce2b47a5c4..5661557a3d 100644
>> --- a/drivers/usb/host/ohci-sunxi.c
>> +++ b/drivers/usb/host/ohci-sunxi.c
>> @@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
>>         struct ohci_sunxi_priv *priv = dev_get_priv(dev);
>>         struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
>>         int extra_ahb_gate_mask = 0;
>> +       int extra_usb_gate_mask = 0;
>>         int phys, ret;
>>
>>         priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>> @@ -78,13 +79,17 @@ no_phy:
>>         extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
>>  #endif
>>         priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>> +#ifdef CONFIG_MACH_SUN50I
>> +       extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>
> This look reassigning same clock to twice?

extra_usb_gate_mask isn't shifted later and thus
CCM_USB_CTRL_OHCI0_CLK and CCM_USB_CTRL_OHCI1_CLK will be enabled for
phy 1 on A64.

[U-Boot] [PATCH 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Marek Vasut]

On 06/06/2018 05:12 PM, Vasily Khoruzhick wrote:
> On Wed, Jun 6, 2018 at 2:02 AM, Marek Vasut <marex@denx.de> wrote:
>> On 06/06/2018 05:38 AM, Vasily Khoruzhick wrote:
>>> On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
>>> clock when OHCI1 is in use.
>>>
>>> Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")
>>>
>>> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
>>> ---
>>>  drivers/usb/host/ohci-sunxi.c | 7 ++++++-
>>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
>>> index ce2b47a5c4..5661557a3d 100644
>>> --- a/drivers/usb/host/ohci-sunxi.c
>>> +++ b/drivers/usb/host/ohci-sunxi.c
>>> @@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
>>>       struct ohci_sunxi_priv *priv = dev_get_priv(dev);
>>>       struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
>>>       int extra_ahb_gate_mask = 0;
>>> +     int extra_usb_gate_mask = 0;
>>>       int phys, ret;
>>>
>>>       priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>> @@ -78,13 +79,17 @@ no_phy:
>>>       extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
>>>  #endif
>>>       priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>>> +#ifdef CONFIG_MACH_SUN50I
>>> +     extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>>> +#endif
>>>       priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
>>>       extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
>>>       priv->usb_gate_mask <<= phys;
>>>
>>>       setbits_le32(&priv->ccm->ahb_gate0,
>>>                    priv->ahb_gate_mask | extra_ahb_gate_mask);
>>> -     setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
>>> +     setbits_le32(&priv->ccm->usb_clk_cfg,
>>> +                  priv->usb_gate_mask | extra_usb_gate_mask);
>>
>> Why is the SoC / compatible information not coming from DT instead ? Why
>> is the driver polluted by more ifdefs ?
> 
> Because this platform doesn't have DM clock driver yet. This code will
> be removed once this driver is implemented.

You don't need DM clock driver, you can check the compatible string I
think ?

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Jagan Teki]

On Wed, Jun 6, 2018 at 8:43 PM, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
> On Wed, Jun 6, 2018 at 6:56 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>> On Wed, Jun 6, 2018 at 9:08 AM, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
>>> On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
>>> clock when OHCI1 is in use.
>>>
>>> Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")
>>>
>>> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
>>> ---
>>>  drivers/usb/host/ohci-sunxi.c | 7 ++++++-
>>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
>>> index ce2b47a5c4..5661557a3d 100644
>>> --- a/drivers/usb/host/ohci-sunxi.c
>>> +++ b/drivers/usb/host/ohci-sunxi.c
>>> @@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
>>>         struct ohci_sunxi_priv *priv = dev_get_priv(dev);
>>>         struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
>>>         int extra_ahb_gate_mask = 0;
>>> +       int extra_usb_gate_mask = 0;
>>>         int phys, ret;
>>>
>>>         priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>> @@ -78,13 +79,17 @@ no_phy:
>>>         extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
>>>  #endif
>>>         priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>>> +#ifdef CONFIG_MACH_SUN50I
>>> +       extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>>
>> This look reassigning same clock to twice?
>
> extra_usb_gate_mask isn't shifted later and thus
> CCM_USB_CTRL_OHCI0_CLK and CCM_USB_CTRL_OHCI1_CLK will be enabled for
> phy 1 on A64.

Where are you checking phy 1? and you still using
CCM_USB_CTRL_OHCI0_CLK not OHCI1_CLK

[U-Boot] [PATCH 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Jagan Teki]

On Wed, Jun 6, 2018 at 8:43 PM, Marek Vasut <marex@denx.de> wrote:
> On 06/06/2018 05:12 PM, Vasily Khoruzhick wrote:
>> On Wed, Jun 6, 2018 at 2:02 AM, Marek Vasut <marex@denx.de> wrote:
>>> On 06/06/2018 05:38 AM, Vasily Khoruzhick wrote:
>>>> On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
>>>> clock when OHCI1 is in use.
>>>>
>>>> Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")
>>>>
>>>> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
>>>> ---
>>>>  drivers/usb/host/ohci-sunxi.c | 7 ++++++-
>>>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
>>>> index ce2b47a5c4..5661557a3d 100644
>>>> --- a/drivers/usb/host/ohci-sunxi.c
>>>> +++ b/drivers/usb/host/ohci-sunxi.c
>>>> @@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
>>>>       struct ohci_sunxi_priv *priv = dev_get_priv(dev);
>>>>       struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
>>>>       int extra_ahb_gate_mask = 0;
>>>> +     int extra_usb_gate_mask = 0;
>>>>       int phys, ret;
>>>>
>>>>       priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>>>> @@ -78,13 +79,17 @@ no_phy:
>>>>       extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
>>>>  #endif
>>>>       priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>>>> +#ifdef CONFIG_MACH_SUN50I
>>>> +     extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
>>>> +#endif
>>>>       priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
>>>>       extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
>>>>       priv->usb_gate_mask <<= phys;
>>>>
>>>>       setbits_le32(&priv->ccm->ahb_gate0,
>>>>                    priv->ahb_gate_mask | extra_ahb_gate_mask);
>>>> -     setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
>>>> +     setbits_le32(&priv->ccm->usb_clk_cfg,
>>>> +                  priv->usb_gate_mask | extra_usb_gate_mask);
>>>
>>> Why is the SoC / compatible information not coming from DT instead ? Why
>>> is the driver polluted by more ifdefs ?
>>
>> Because this platform doesn't have DM clock driver yet. This code will
>> be removed once this driver is implemented.
>
> You don't need DM clock driver, you can check the compatible string I
> think ?

Yes or driver_data, if we wanted to get rid of other #Ifdef on the file

[U-Boot] [PATCH 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Vasily Khoruzhick]

On Wed, Jun 6, 2018 at 9:35 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> On Wed, Jun 6, 2018 at 8:43 PM, Vasily Khoruzhick <anarsoul@gmail.com> wrote:

>> extra_usb_gate_mask isn't shifted later and thus
>> CCM_USB_CTRL_OHCI0_CLK and CCM_USB_CTRL_OHCI1_CLK will be enabled for
>> phy 1 on A64.
>
> Where are you checking phy 1? and you still using
> CCM_USB_CTRL_OHCI0_CLK not OHCI1_CLK

phys is PHY index, usb_gate_mask is shifted to PHY index later - thus
it'll be CCM_USB_CTRL_OHCI1_CLK,
extra_usb_gate_mask is not - it'll remain CCM_USB_CTRL_OHCI0_CLK.

Since A64 has only 2 USB controllers that covers it.

[U-Boot] [PATCH 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Vasily Khoruzhick]

On Wed, Jun 6, 2018 at 9:36 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>>>> Why is the SoC / compatible information not coming from DT instead ? Why
>>>> is the driver polluted by more ifdefs ?
>>>
>>> Because this platform doesn't have DM clock driver yet. This code will
>>> be removed once this driver is implemented.
>>
>> You don't need DM clock driver, you can check the compatible string I
>> think ?
>
> Yes or driver_data, if we wanted to get rid of other #Ifdef on the file

OK, I'll change it to use driver_data.

[U-Boot] [U-Boot, 1/2] sunxi: clock: Fix EHCI and OHCI clocks on A64

[Vagrant Cascadian]

On 2018-06-05, Vasily Khoruzhick wrote:
> EHCI0 is bit 24, EHCI1 - 25, OHCI0 - 28, OHCI1 - 29
>
> Fixed commit fef73766d9ad ("sunxi: clock: Fix OHCI clock gating for H3/H5")
>
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)

Tested loading kernel+initrd+dtb on pine64+

Tested-by: Vagrant Cascadian <vagrant@debian.org>

live well,
  vagrant

> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index 8acf79fbba..8afeaf872e 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -280,8 +280,10 @@ struct sunxi_ccm_reg {
>  #define AHB_GATE_OFFSET_USB_EHCI1	26
>  #define AHB_GATE_OFFSET_USB_EHCI0	24
>  #elif defined(CONFIG_MACH_SUN50I)
> -#define AHB_GATE_OFFSET_USB_OHCI0	29
> -#define AHB_GATE_OFFSET_USB_EHCI0	25
> +#define AHB_GATE_OFFSET_USB_OHCI0	28
> +#define AHB_GATE_OFFSET_USB_OHCI1	29
> +#define AHB_GATE_OFFSET_USB_EHCI0	24
> +#define AHB_GATE_OFFSET_USB_EHCI1	25
>  #else
>  #define AHB_GATE_OFFSET_USB_OHCI1	30
>  #define AHB_GATE_OFFSET_USB_OHCI0	29
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[U-Boot] [U-Boot, 2/2] usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

[Vagrant Cascadian]

On 2018-06-05, Vasily Khoruzhick wrote:
> On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
> clock when OHCI1 is in use.
>
> Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")
>
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
>  drivers/usb/host/ohci-sunxi.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)

Tested loading kernel+initrd+dtb on pine64+

Tested-by: Vagrant Cascadian <vagrant@debian.org>

live well,
  vagrant


> diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
> index ce2b47a5c4..5661557a3d 100644
> --- a/drivers/usb/host/ohci-sunxi.c
> +++ b/drivers/usb/host/ohci-sunxi.c
> @@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
>  	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
>  	struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
>  	int extra_ahb_gate_mask = 0;
> +	int extra_usb_gate_mask = 0;
>  	int phys, ret;
>  
>  	priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> @@ -78,13 +79,17 @@ no_phy:
>  	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
>  #endif
>  	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
> +#ifdef CONFIG_MACH_SUN50I
> +	extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
> +#endif
>  	priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
>  	extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
>  	priv->usb_gate_mask <<= phys;
>  
>  	setbits_le32(&priv->ccm->ahb_gate0,
>  		     priv->ahb_gate_mask | extra_ahb_gate_mask);
> -	setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
> +	setbits_le32(&priv->ccm->usb_clk_cfg,
> +		     priv->usb_gate_mask | extra_usb_gate_mask);
>  #ifdef CONFIG_SUNXI_GEN_SUN6I
>  	setbits_le32(&priv->ccm->ahb_reset0_cfg,
>  		     priv->ahb_gate_mask | extra_ahb_gate_mask);
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