From: Baruch Siach <baruch@tkos.co.il>
To: u-boot@lists.denx.de
Subject: [PATCH 2/2] mv_ddr: ddr3: Update {min, max}_read_sample calculation
Date: Wed, 27 May 2020 07:50:32 +0300 [thread overview]
Message-ID: <87tv02asmf.fsf@tarshish> (raw)
In-Reply-To: <20200527013131.1663-3-judge.packham@gmail.com>
Hi Chris,
On Wed, May 27 2020, Chris Packham wrote:
> From: Chris Packham <chris.packham@alliedtelesis.co.nz>
>
> Measurements on actual hardware shown that the read ODT is early by 3
> clocks. Adjust the calculation to avoid this.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>
> [upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
> Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested here on an Armada 385 based system. Running memtester for more
than an hour.
Tested-by: Baruch Siach <baruch@tkos.co.il>
Thanks,
baruch
> ---
>
> drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> index ce9a47fc2ce0..58ffb205072e 100644
> --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c
> @@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
> min_read_sample = read_sample[cs_num];
> }
>
> - min_read_sample = min_read_sample - 1;
> - max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
> + min_read_sample = min_read_sample + 2;
> + max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1;
> if (min_read_sample >= 0xf)
> min_read_sample = 0xf;
> if (max_read_sample >= 0x1f)
--
~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
next prev parent reply other threads:[~2020-05-27 4:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-27 1:31 [PATCH 0/2] mvebu: ddr3: Armada-385 read ODT configuration Chris Packham
2020-05-27 1:31 ` [PATCH 1/2] mv_ddr: ddr3: Use correct bitmask for read sample delay Chris Packham
2020-05-27 5:41 ` Stefan Roese
2020-05-27 1:31 ` [PATCH 2/2] mv_ddr: ddr3: Update {min,max}_read_sample calculation Chris Packham
2020-05-27 4:50 ` Baruch Siach [this message]
2020-05-27 5:41 ` Stefan Roese
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