From mboxrd@z Thu Jan 1 00:00:00 1970 From: Baruch Siach Date: Wed, 27 May 2020 07:50:32 +0300 Subject: [PATCH 2/2] mv_ddr: ddr3: Update {min, max}_read_sample calculation In-Reply-To: <20200527013131.1663-3-judge.packham@gmail.com> References: <20200527013131.1663-1-judge.packham@gmail.com> <20200527013131.1663-3-judge.packham@gmail.com> Message-ID: <87tv02asmf.fsf@tarshish> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Chris, On Wed, May 27 2020, Chris Packham wrote: > From: Chris Packham > > Measurements on actual hardware shown that the read ODT is early by 3 > clocks. Adjust the calculation to avoid this. > > Signed-off-by: Chris Packham > > [upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22] > Signed-off-by: Chris Packham Tested here on an Armada 385 based system. Running memtester for more than an hour. Tested-by: Baruch Siach Thanks, baruch > --- > > drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c > index ce9a47fc2ce0..58ffb205072e 100644 > --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c > +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c > @@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) > min_read_sample = read_sample[cs_num]; > } > > - min_read_sample = min_read_sample - 1; > - max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1; > + min_read_sample = min_read_sample + 2; > + max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1; > if (min_read_sample >= 0xf) > min_read_sample = 0xf; > if (max_read_sample >= 0x1f) -- ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -