From: Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
To: u-boot@lists.denx.de
Subject: rockchip: correctly set vop0 or vop1
Date: Mon, 08 Jun 2020 10:18:19 +0200 [thread overview]
Message-ID: <87y2oy6kdw.fsf@lechat.rtp-net.org> (raw)
In-Reply-To: <20200607183612.GA82210@ryzen.blueri.se> (Patrick Wildt's message of "Sun, 7 Jun 2020 20:36:12 +0200")
Patrick Wildt <patrick@blueri.se> writes:
Hi,
> The EDP_LCDC_SEL bit has to be set correctly to select vop0 or
> vop1, but so far we have set it in both conditions, which is not
> correct.
>
> Can someone verify this is the correct way round? vop1 -> set,
> vop0 -> clear?
>
> Signed-off-by: Patrick Wildt <patrick@blueri.se>
>
> diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
> index 92188be9275..000bd481408 100644
> --- a/drivers/video/rockchip/rk_edp.c
> +++ b/drivers/video/rockchip/rk_edp.c
> @@ -1062,7 +1062,8 @@ static int rk_edp_probe(struct udevice *dev)
> rk_setreg(&priv->grf->soc_con12, 1 << 4);
>
> /* select epd signal from vop0 or vop1 */
> - rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5));
> + rk_clrsetreg(&priv->grf->soc_con6, (1 << 5),
> + (vop_id == 1) ? (1 << 5) : (0 << 5));
While working on PBP EDP support, found this too but I'm not sure it's
fine or not. For rk3399, my (not yet published) patch is doing:
+ if (vop_id == 0)
+ rk_clrreg(&priv->grf->soc_con20, (1 << 5));
+ else
+ rk_setreg(&priv->grf->soc_con20, (1 << 5));
I believe that the rk3288 may need similar treatment but I've yet to
look@the rk3288 manual.
Arnaud
next prev parent reply other threads:[~2020-06-08 8:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-07 18:36 rockchip: correctly set vop0 or vop1 Patrick Wildt
2020-06-08 8:18 ` Arnaud Patard [this message]
2020-06-08 11:10 ` Patrick Wildt
2020-06-08 12:24 ` Arnaud Patard
2020-06-08 12:39 ` Patrick Wildt
2020-06-27 12:56 ` Kever Yang
2020-06-28 2:24 ` Andy Yan
2020-06-28 1:50 ` Kever Yang
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