From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 821D7C433F5 for ; Mon, 4 Apr 2022 13:41:02 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 747D481DCD; Mon, 4 Apr 2022 15:40:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1649079660; bh=GEk1hwCOZTHkqFryOvn/aC1BlqF74PspcKtB/JgnqCs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=z5T9FwQBrXocEkvZQNL1rR7eYdaIy+qrHVPQ0TlXoRXpVmAIX/Sl8ZDpLUfhH+qZm SzGgyzGvL+Td7qzqPObnsI3HCwz1/xqtXbbJxvK2UArhBEPiKgiZHUEi4oHbKkaxb+ egNI1vf4azRovLhMbookITgrpOYFleoxrD2gi71tRvbpVyUe2iM4/bdsoLTbiiKICP /4Jau7ciiHQXcUTIK5BsIuJ9+GVwPCrpfhIp5ja81IOI7q2WUjvix12qZ9MFIIU/Ge 8pFNZDdTQ8nKMyGlEEQjquQ47wtCCU2Ldh5NqyoYGNlNzezsH9BDkeKzV4UJxyO0+5 KNQfKtdCjyRKg== Received: from [127.0.0.1] (p578adb1c.dip0.t-ipconnect.de [87.138.219.28]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 0650981B5C; Mon, 4 Apr 2022 15:40:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1649079657; bh=GEk1hwCOZTHkqFryOvn/aC1BlqF74PspcKtB/JgnqCs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Dv827laOJDzghYxOPKEC+262uWXOxZ4RcTxlewX4yvcNCm49zsQckS3g0yv54SeHe +GP4/XZzjEgVwwyRJBURloNpunpvznK5g5/hG+ltP9ar1OEecZNK3xTLKxQW5jBwTv ubmrCuOfehPBX3BeWbrlaEy0sE3KdPhjvqaKS/jRL2CiIzXj+ubOlqNLXkhzZPSVl6 Bto5t9CXOm1KjbnWBqETQm3gq3FwKhIFXByEUlDsUwuSSQwwdxAJU5AML6Wb/Ph1Tq cwvrDD/QcS7zghQftIl4MydZNCTUx1AGkv0yvg3V25n6kuH+1+bd2Cx+ROPssmEJLG zLmDaVxRF8dvA== Message-ID: <8f75eeb6-bd2d-0475-ed06-e455d884133d@denx.de> Date: Mon, 4 Apr 2022 15:40:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [RFC PATCH 1/3] mx6: ddr: Restore ralat/walat in write level calibration Content-Language: en-US To: Francesco Dolcini , Stefano Babic , Fabio Estevam , uboot-imx@nxp.com, Tim Harvey Cc: u-boot@lists.denx.de References: <20220404085119.97792-1-francesco.dolcini@toradex.com> <20220404085119.97792-2-francesco.dolcini@toradex.com> From: Marek Vasut In-Reply-To: <20220404085119.97792-2-francesco.dolcini@toradex.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On 4/4/22 10:51, Francesco Dolcini wrote: > The current DDR write level calibration routine always overwrite > the ralat/walat fields to their maximum value, just save > the existing values at the beginning of the calibration routine > and restore it at the end. > > In case the delay is estimated by the user to be more than one cycle the > walat should be configured according to that, this is not > automatically done. From the i.MX6 RM: > > The user should read the results of the associated delay-line at > MPWLDECTRL#[WL_DL_ABS_OFFSET#] and in case the user estimates that the > reasonable delay may be above 1 cycle then the user should indicate it at > MPWLDECTRL#[WL_CYC_DEL#]. Moreover the user should indicate it in > MDMISC[WALAT] field. For example, if the result of the write leveling calibration > is 100/256 parts of a cycle, but the user estimates that the delay is above 2 cycles > then MPWLDECTRL#[WL_CYC_DEL#] should be configured to 2, so the total > delay will be 2 and 100/256 parts of a cycle > > Probably it would just possible to not overwrite the mdmisc register in > the first place, since this is not present in the write_level_calib() example > in NXP AN4467 [1] nor in the i.MX6 RM (44.11.6.1 Hardware Write Leveling > Calibration). > > Fixes: d339f16911c7 ("arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL") > Signed-off-by: Francesco Dolcini > --- > arch/arm/mach-imx/mx6/ddr.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c > index f872bfdab315..08e2f0f130a6 100644 > --- a/arch/arm/mach-imx/mx6/ddr.c > +++ b/arch/arm/mach-imx/mx6/ddr.c > @@ -108,7 +108,7 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo) > { > struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; > struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; > - u32 esdmisc_val, zq_val; > + u32 esdmisc_val, zq_val, mdmisc_val; > u32 errors = 0; > u32 ldectrl[4] = {0}; > u32 ddr_mr1 = 0x4; > @@ -131,6 +131,9 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo) > /* disable Adopt power down timer */ > setbits_le32(&mmdc0->mapsr, 0x1); > > + /* Save old RALAT and WALAT values */ > + mdmisc_val = readl(&mmdc0->mdmisc); > + > debug("Starting write leveling calibration.\n"); > > /* > @@ -217,6 +220,9 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo) > writel(esdmisc_val, &mmdc0->mdref); > writel(zq_val, &mmdc0->mpzqhwctrl); > > + /* restore walat/ralat */ > + writel(mdmisc_val, &mmdc0->mdmisc); > + > debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n", > readl(&mmdc0->mpwldectrl0)); > debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n", Reviewed-by: Marek Vasut