* [U-Boot] [PATCH] rtc: imxdi: Initial support
2012-07-20 14:24 ` [U-Boot] [PATCH] rtc: imxdi: Initial support Benoît Thébaudeau
@ 2012-08-03 23:06 ` Benoît Thébaudeau
2012-08-05 7:13 ` Stefano Babic
2012-08-08 11:57 ` [U-Boot] [PATCH v2] " Benoît Thébaudeau
2 siblings, 0 replies; 10+ messages in thread
From: Benoît Thébaudeau @ 2012-08-03 23:06 UTC (permalink / raw)
To: u-boot
On Fri, Jul 20, 2012 at 04:24:38 PM, Beno?t Th?baudeau wrote:
> Add support for Freescale's i.MX DryIce RTC, present on i.MX25.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> .../drivers/rtc/Makefile | 1 +
> /dev/null => u-boot-66714b1/drivers/rtc/imxdi.c | 224
> ++++++++++++++++++++
> 2 files changed, 225 insertions(+)
> create mode 100644 u-boot-66714b1/drivers/rtc/imxdi.c
>
> diff --git u-boot-66714b1.orig/drivers/rtc/Makefile
> u-boot-66714b1/drivers/rtc/Makefile
> index faf4fcd..aeeea37 100644
> --- u-boot-66714b1.orig/drivers/rtc/Makefile
> +++ u-boot-66714b1/drivers/rtc/Makefile
> @@ -43,6 +43,7 @@ COBJS-$(CONFIG_RTC_DS164x) += ds164x.o
> COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
> COBJS-$(CONFIG_RTC_DS3231) += ds3231.o
> COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
> +COBJS-$(CONFIG_RTC_IMXDI) += imxdi.o
> COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o
> COBJS-$(CONFIG_RTC_M41T11) += m41t11.o
> COBJS-$(CONFIG_RTC_M41T60) += m41t60.o
> diff --git u-boot-66714b1/drivers/rtc/imxdi.c
> u-boot-66714b1/drivers/rtc/imxdi.c
> new file mode 100644
> index 0000000..c2be842
> --- /dev/null
> +++ u-boot-66714b1/drivers/rtc/imxdi.c
> @@ -0,0 +1,224 @@
> +/*
> + * (C) Copyright 2009-2012 ADVANSEE
> + * Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> + *
> + * Based on the Linux rtc-imxdi.c driver, which is:
> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights
> Reserved.
> + * Copyright 2010 Orex Computed Radiography
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * Date & Time support for Freescale i.MX DryIce RTC
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <rtc.h>
> +
> +#if defined(CONFIG_CMD_DATE)
> +
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +
> +/* DryIce Register Definitions */
> +
> +#define DTCMR 0x00 /* Time Counter MSB Reg */
> +#define DTCLR 0x04 /* Time Counter LSB Reg */
> +
> +#define DCAMR 0x08 /* Clock Alarm MSB Reg */
> +#define DCALR 0x0c /* Clock Alarm LSB Reg */
> +#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
> +
> +#define DCR 0x10 /* Control Reg */
> +#define DCR_TCE (1 << 3) /* Time Counter Enable */
> +
> +#define DSR 0x14 /* Status Reg */
> +#define DSR_WBF (1 << 10) /* Write Busy Flag */
> +#define DSR_WNF (1 << 9) /* Write Next Flag */
> +#define DSR_WCF (1 << 8) /* Write Complete Flag */
> +#define DSR_WEF (1 << 7) /* Write Error Flag */
> +#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
> +#define DSR_NVF (1 << 1) /* Non-Valid Flag */
> +#define DSR_SVF (1 << 0) /* Security Violation Flag */
> +
> +#define DIER 0x18 /* Interrupt Enable Reg */
> +#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
> +#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable
> */
> +#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
> +#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
> +
> +/*
> + * This function attempts to clear the dryice write-error flag.
> + *
> + * A dryice write error is similar to a bus fault and should not
> occur in
> + * normal operation. Clearing the flag requires another write, so
> the root
> + * cause of the problem may need to be fixed before the flag can be
> cleared.
> + */
> +static void clear_write_error(void)
> +{
> + int cnt;
> +
> + puts("### Warning: RTC - Register write error!\n");
> +
> + /* clear the write error flag */
> + __raw_writel(DSR_WEF, IMX_DRYICE_BASE + DSR);
> +
> + /* wait for it to take effect */
> + for (cnt = 0; cnt < 1000; cnt++) {
> + if ((__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_WEF) == 0)
> + return;
> + udelay(10);
> + }
> + puts("### Error: RTC - Cannot clear write-error flag!\n");
> +}
> +
> +/*
> + * Write a dryice register and wait until it completes.
> + *
> + * This function uses interrupt flags to determine when the
> + * write has completed.
> + */
> +static int di_write_wait(u32 val, int reg)
> +{
> + int cnt;
> + int ret = 0;
> + int rc = 0;
> +
> + /* do the register write */
> + __raw_writel(val, IMX_DRYICE_BASE + reg);
> +
> + /* wait for the write to finish */
> + for (cnt = 0; cnt < 100; cnt++) {
> + if ((__raw_readl(IMX_DRYICE_BASE + DSR) &
> + (DSR_WCF | DSR_WEF)) != 0) {
> + ret = 1;
> + break;
> + }
> + udelay(10);
> + }
> + if (ret == 0)
> + printf("### Warning: RTC - Write-wait timeout "
> + "val = 0x%.8x reg = 0x%.8x\n", val, reg);
> +
> + /* check for write error */
> + if (__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_WEF) {
> + clear_write_error();
> + rc = -1;
> + }
> +
> + return rc;
> +}
> +
> +/*
> + * Initialize dryice hardware
> + */
> +static int di_init(void)
> +{
> + int rc = 0;
> +
> + /* mask all interrupts */
> + __raw_writel(0, IMX_DRYICE_BASE + DIER);
> +
> + /* put dryice into valid state */
> + if (__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_NVF) {
> + rc = di_write_wait(DSR_NVF | DSR_SVF, DSR);
> + if (rc)
> + goto err;
> + }
> +
> + /* initialize alarm */
> + rc = di_write_wait(DCAMR_UNSET, DCAMR);
> + if (rc)
> + goto err;
> + rc = di_write_wait(0, DCALR);
> + if (rc)
> + goto err;
> +
> + /* clear alarm flag */
> + if (__raw_readl(IMX_DRYICE_BASE + DSR) & DSR_CAF) {
> + rc = di_write_wait(DSR_CAF, DSR);
> + if (rc)
> + goto err;
> + }
> +
> + /* the timer won't count if it has never been written to */
> + if (__raw_readl(IMX_DRYICE_BASE + DTCMR) == 0) {
> + rc = di_write_wait(0, DTCMR);
> + if (rc)
> + goto err;
> + }
> +
> + /* start keeping time */
> + if (!(__raw_readl(IMX_DRYICE_BASE + DCR) & DCR_TCE)) {
> + rc = di_write_wait(__raw_readl(IMX_DRYICE_BASE + DCR) | DCR_TCE,
> + DCR);
> + if (rc)
> + goto err;
> + }
> +
> + return 0;
> +
> +err:
> + return rc;
> +}
> +
> +int rtc_get(struct rtc_time *tmp)
> +{
> + unsigned long now;
> + int rc;
> +
> + rc = di_init();
> + if (rc)
> + goto err;
> +
> + now = __raw_readl(IMX_DRYICE_BASE + DTCMR);
> + to_tm(now, tmp);
> +
> +err:
> + return rc;
> +}
> +
> +int rtc_set(struct rtc_time *tmp)
> +{
> + unsigned long now;
> + int rc;
> +
> + rc = di_init();
> + if (rc)
> + goto err;
> +
> + now = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
> + tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
> + /* zero the fractional part first */
> + rc = di_write_wait(0, DTCLR);
> + if (rc == 0)
> + rc = di_write_wait(now, DTCMR);
> +
> +err:
> + return rc;
> +}
> +
> +void rtc_reset(void)
> +{
> + di_init();
> +}
> +
> +#endif
>
Ping?
Beno?t
^ permalink raw reply [flat|nested] 10+ messages in thread* [U-Boot] [PATCH] rtc: imxdi: Initial support
2012-07-20 14:24 ` [U-Boot] [PATCH] rtc: imxdi: Initial support Benoît Thébaudeau
2012-08-03 23:06 ` Benoît Thébaudeau
@ 2012-08-05 7:13 ` Stefano Babic
2012-08-05 14:14 ` Benoît Thébaudeau
2012-08-08 11:57 ` [U-Boot] [PATCH v2] " Benoît Thébaudeau
2 siblings, 1 reply; 10+ messages in thread
From: Stefano Babic @ 2012-08-05 7:13 UTC (permalink / raw)
To: u-boot
On 20/07/2012 16:24, Beno?t Th?baudeau wrote:
> Add support for Freescale's i.MX DryIce RTC, present on i.MX25.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
Hi Benoit,
just a few comments.
> +
> +/*
> + * Date & Time support for Freescale i.MX DryIce RTC
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <rtc.h>
> +
> +#if defined(CONFIG_CMD_DATE)
> +
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +
> +/* DryIce Register Definitions */
> +
> +#define DTCMR 0x00 /* Time Counter MSB Reg */
> +#define DTCLR 0x04 /* Time Counter LSB Reg */
> +
> +#define DCAMR 0x08 /* Clock Alarm MSB Reg */
> +#define DCALR 0x0c /* Clock Alarm LSB Reg */
U-Boot as rule does not allow usage of start address + offset to access
internal registers. Instead of that, please define a proper C structure
with the register's layout. This should be fixed globally for all read /
write accesses.
> +/*
> + * This function attempts to clear the dryice write-error flag.
> + *
> + * A dryice write error is similar to a bus fault and should not occur in
> + * normal operation. Clearing the flag requires another write, so the root
> + * cause of the problem may need to be fixed before the flag can be cleared.
> + */
> +static void clear_write_error(void)
> +{
> + int cnt;
> +
> + puts("### Warning: RTC - Register write error!\n");
> +
> + /* clear the write error flag */
> + __raw_writel(DSR_WEF, IMX_DRYICE_BASE + DSR);
Ditto
> +int rtc_get(struct rtc_time *tmp)
> +{
> + unsigned long now;
> + int rc;
> +
> + rc = di_init();
Why is di_init always called ? Should be not checked if it is was
already initialized and the function should be called only once ?
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread* [U-Boot] [PATCH] rtc: imxdi: Initial support
2012-08-05 7:13 ` Stefano Babic
@ 2012-08-05 14:14 ` Benoît Thébaudeau
0 siblings, 0 replies; 10+ messages in thread
From: Benoît Thébaudeau @ 2012-08-05 14:14 UTC (permalink / raw)
To: u-boot
On Sun, Aug 5, 2012 at 09:13:29 AM, Stefano Babic wrote:
> On 20/07/2012 16:24, Beno?t Th?baudeau wrote:
> > Add support for Freescale's i.MX DryIce RTC, present on i.MX25.
> >
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > Cc: Wolfgang Denk <wd@denx.de>
> > Cc: Stefano Babic <sbabic@denx.de>
> > ---
>
> Hi Benoit,
>
>
> just a few comments.
>
> > +
> > +/*
> > + * Date & Time support for Freescale i.MX DryIce RTC
> > + */
> > +
> > +#include <common.h>
> > +#include <command.h>
> > +#include <rtc.h>
> > +
> > +#if defined(CONFIG_CMD_DATE)
> > +
> > +#include <asm/io.h>
> > +#include <asm/arch/imx-regs.h>
> > +
> > +/* DryIce Register Definitions */
> > +
> > +#define DTCMR 0x00 /* Time Counter MSB Reg */
> > +#define DTCLR 0x04 /* Time Counter LSB Reg */
> > +
> > +#define DCAMR 0x08 /* Clock Alarm MSB Reg */
> > +#define DCALR 0x0c /* Clock Alarm LSB Reg */
>
> U-Boot as rule does not allow usage of start address + offset to
> access
> internal registers. Instead of that, please define a proper C
> structure
> with the register's layout. This should be fixed globally for all
> read /
> write accesses.
OK, I'll do that.
> > +/*
> > + * This function attempts to clear the dryice write-error flag.
> > + *
> > + * A dryice write error is similar to a bus fault and should not
> > occur in
> > + * normal operation. Clearing the flag requires another write, so
> > the root
> > + * cause of the problem may need to be fixed before the flag can
> > be cleared.
> > + */
> > +static void clear_write_error(void)
> > +{
> > + int cnt;
> > +
> > + puts("### Warning: RTC - Register write error!\n");
> > +
> > + /* clear the write error flag */
> > + __raw_writel(DSR_WEF, IMX_DRYICE_BASE + DSR);
>
> Ditto
>
> > +int rtc_get(struct rtc_time *tmp)
> > +{
> > + unsigned long now;
> > + int rc;
> > +
> > + rc = di_init();
>
> Why is di_init always called ? Should be not checked if it is was
> already initialized and the function should be called only once ?
I think this can be done. I'll check that this does not cause any regression.
I think only the reset function should have to call di_init unconditionally.
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2] rtc: imxdi: Initial support
2012-07-20 14:24 ` [U-Boot] [PATCH] rtc: imxdi: Initial support Benoît Thébaudeau
2012-08-03 23:06 ` Benoît Thébaudeau
2012-08-05 7:13 ` Stefano Babic
@ 2012-08-08 11:57 ` Benoît Thébaudeau
2012-08-08 14:29 ` Stefano Babic
2 siblings, 1 reply; 10+ messages in thread
From: Benoît Thébaudeau @ 2012-08-08 11:57 UTC (permalink / raw)
To: u-boot
Add support for Freescale's i.MX DryIce RTC, present on i.MX25.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
- Define registers with struct instead of #define's.
- Call di_init() only once, except if requested by rtc_reset().
.../drivers/rtc/Makefile | 1 +
/dev/null => u-boot-2012.07/drivers/rtc/imxdi.c | 244 ++++++++++++++++++++
2 files changed, 245 insertions(+)
create mode 100644 u-boot-2012.07/drivers/rtc/imxdi.c
diff --git u-boot-2012.07.orig/drivers/rtc/Makefile u-boot-2012.07/drivers/rtc/Makefile
index faf4fcd..aeeea37 100644
--- u-boot-2012.07.orig/drivers/rtc/Makefile
+++ u-boot-2012.07/drivers/rtc/Makefile
@@ -43,6 +43,7 @@ COBJS-$(CONFIG_RTC_DS164x) += ds164x.o
COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
COBJS-$(CONFIG_RTC_DS3231) += ds3231.o
COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
+COBJS-$(CONFIG_RTC_IMXDI) += imxdi.o
COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o
COBJS-$(CONFIG_RTC_M41T11) += m41t11.o
COBJS-$(CONFIG_RTC_M41T60) += m41t60.o
diff --git u-boot-2012.07/drivers/rtc/imxdi.c u-boot-2012.07/drivers/rtc/imxdi.c
new file mode 100644
index 0000000..0766027
--- /dev/null
+++ u-boot-2012.07/drivers/rtc/imxdi.c
@@ -0,0 +1,244 @@
+/*
+ * (C) Copyright 2009-2012 ADVANSEE
+ * Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the Linux rtc-imxdi.c driver, which is:
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2010 Orex Computed Radiography
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for Freescale i.MX DryIce RTC
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/compat.h>
+#include <rtc.h>
+
+#if defined(CONFIG_CMD_DATE)
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/* DryIce Register Definitions */
+
+struct imxdi_regs {
+ u32 dtcmr; /* Time Counter MSB Reg */
+ u32 dtclr; /* Time Counter LSB Reg */
+ u32 dcamr; /* Clock Alarm MSB Reg */
+ u32 dcalr; /* Clock Alarm LSB Reg */
+ u32 dcr; /* Control Reg */
+ u32 dsr; /* Status Reg */
+ u32 dier; /* Interrupt Enable Reg */
+};
+
+#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
+
+#define DCR_TCE (1 << 3) /* Time Counter Enable */
+
+#define DSR_WBF (1 << 10) /* Write Busy Flag */
+#define DSR_WNF (1 << 9) /* Write Next Flag */
+#define DSR_WCF (1 << 8) /* Write Complete Flag */
+#define DSR_WEF (1 << 7) /* Write Error Flag */
+#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
+#define DSR_NVF (1 << 1) /* Non-Valid Flag */
+#define DSR_SVF (1 << 0) /* Security Violation Flag */
+
+#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
+#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
+#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
+#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
+
+/* Driver Private Data */
+
+struct imxdi_data {
+ struct imxdi_regs __iomem *regs;
+ int init_done;
+};
+
+static struct imxdi_data data;
+
+/*
+ * This function attempts to clear the dryice write-error flag.
+ *
+ * A dryice write error is similar to a bus fault and should not occur in
+ * normal operation. Clearing the flag requires another write, so the root
+ * cause of the problem may need to be fixed before the flag can be cleared.
+ */
+static void clear_write_error(void)
+{
+ int cnt;
+
+ puts("### Warning: RTC - Register write error!\n");
+
+ /* clear the write error flag */
+ __raw_writel(DSR_WEF, &data.regs->dsr);
+
+ /* wait for it to take effect */
+ for (cnt = 0; cnt < 1000; cnt++) {
+ if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0)
+ return;
+ udelay(10);
+ }
+ puts("### Error: RTC - Cannot clear write-error flag!\n");
+}
+
+/*
+ * Write a dryice register and wait until it completes.
+ *
+ * Use interrupt flags to determine when the write has completed.
+ */
+#define DI_WRITE_WAIT(val, reg) \
+( \
+ /* do the register write */ \
+ __raw_writel((val), &data.regs->reg), \
+ \
+ di_write_wait((val), #reg) \
+)
+static int di_write_wait(u32 val, const char *reg)
+{
+ int cnt;
+ int ret = 0;
+ int rc = 0;
+
+ /* wait for the write to finish */
+ for (cnt = 0; cnt < 100; cnt++) {
+ if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) {
+ ret = 1;
+ break;
+ }
+ udelay(10);
+ }
+ if (ret == 0)
+ printf("### Warning: RTC - Write-wait timeout "
+ "val = 0x%.8x reg = %s\n", val, reg);
+
+ /* check for write error */
+ if (__raw_readl(&data.regs->dsr) & DSR_WEF) {
+ clear_write_error();
+ rc = -1;
+ }
+
+ return rc;
+}
+
+/*
+ * Initialize dryice hardware
+ */
+static int di_init(void)
+{
+ int rc = 0;
+
+ data.regs = (struct imxdi_regs __iomem *)IMX_DRYICE_BASE;
+
+ /* mask all interrupts */
+ __raw_writel(0, &data.regs->dier);
+
+ /* put dryice into valid state */
+ if (__raw_readl(&data.regs->dsr) & DSR_NVF) {
+ rc = DI_WRITE_WAIT(DSR_NVF | DSR_SVF, dsr);
+ if (rc)
+ goto err;
+ }
+
+ /* initialize alarm */
+ rc = DI_WRITE_WAIT(DCAMR_UNSET, dcamr);
+ if (rc)
+ goto err;
+ rc = DI_WRITE_WAIT(0, dcalr);
+ if (rc)
+ goto err;
+
+ /* clear alarm flag */
+ if (__raw_readl(&data.regs->dsr) & DSR_CAF) {
+ rc = DI_WRITE_WAIT(DSR_CAF, dsr);
+ if (rc)
+ goto err;
+ }
+
+ /* the timer won't count if it has never been written to */
+ if (__raw_readl(&data.regs->dtcmr) == 0) {
+ rc = DI_WRITE_WAIT(0, dtcmr);
+ if (rc)
+ goto err;
+ }
+
+ /* start keeping time */
+ if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) {
+ rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr);
+ if (rc)
+ goto err;
+ }
+
+ data.init_done = 1;
+ return 0;
+
+err:
+ return rc;
+}
+
+int rtc_get(struct rtc_time *tmp)
+{
+ unsigned long now;
+ int rc = 0;
+
+ if (!data.init_done) {
+ rc = di_init();
+ if (rc)
+ goto err;
+ }
+
+ now = __raw_readl(&data.regs->dtcmr);
+ to_tm(now, tmp);
+
+err:
+ return rc;
+}
+
+int rtc_set(struct rtc_time *tmp)
+{
+ unsigned long now;
+ int rc;
+
+ if (!data.init_done) {
+ rc = di_init();
+ if (rc)
+ goto err;
+ }
+
+ now = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ /* zero the fractional part first */
+ rc = DI_WRITE_WAIT(0, dtclr);
+ if (rc == 0)
+ rc = DI_WRITE_WAIT(now, dtcmr);
+
+err:
+ return rc;
+}
+
+void rtc_reset(void)
+{
+ di_init();
+}
+
+#endif
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v2] rtc: imxdi: Initial support
2012-08-08 11:57 ` [U-Boot] [PATCH v2] " Benoît Thébaudeau
@ 2012-08-08 14:29 ` Stefano Babic
2012-08-08 14:52 ` [U-Boot] [PATCH v3] " Benoît Thébaudeau
2012-08-08 14:57 ` [U-Boot] [PATCH v2] " Benoît Thébaudeau
0 siblings, 2 replies; 10+ messages in thread
From: Stefano Babic @ 2012-08-08 14:29 UTC (permalink / raw)
To: u-boot
On 08/08/2012 13:57, Beno?t Th?baudeau wrote:
> Add support for Freescale's i.MX DryIce RTC, present on i.MX25.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
Hi Beno?t,
checkpatch reports an error when I run your patch. Can you fix it ?
ERROR: code indent should use tabs where possible
#275: FILE: drivers/rtc/imxdi.c:229:
+^I tmp->tm_hour, tmp->tm_min, tmp->tm_sec);$
Apart of that, here my:
Acked-by: Stefano Babic <sbabic@denx.de>
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v3] rtc: imxdi: Initial support
2012-08-08 14:29 ` Stefano Babic
@ 2012-08-08 14:52 ` Benoît Thébaudeau
2012-08-09 13:58 ` Stefano Babic
2012-08-08 14:57 ` [U-Boot] [PATCH v2] " Benoît Thébaudeau
1 sibling, 1 reply; 10+ messages in thread
From: Benoît Thébaudeau @ 2012-08-08 14:52 UTC (permalink / raw)
To: u-boot
Add support for Freescale's i.MX DryIce RTC, present on i.MX25.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
- Define registers with struct instead of #define's.
- Call di_init() only once, except if requested by rtc_reset().
Changes for v3:
- Fix a tab indent.
.../drivers/rtc/Makefile | 1 +
/dev/null => u-boot-2012.07/drivers/rtc/imxdi.c | 244 ++++++++++++++++++++
2 files changed, 245 insertions(+)
create mode 100644 u-boot-2012.07/drivers/rtc/imxdi.c
diff --git u-boot-2012.07.orig/drivers/rtc/Makefile u-boot-2012.07/drivers/rtc/Makefile
index faf4fcd..aeeea37 100644
--- u-boot-2012.07.orig/drivers/rtc/Makefile
+++ u-boot-2012.07/drivers/rtc/Makefile
@@ -43,6 +43,7 @@ COBJS-$(CONFIG_RTC_DS164x) += ds164x.o
COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
COBJS-$(CONFIG_RTC_DS3231) += ds3231.o
COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
+COBJS-$(CONFIG_RTC_IMXDI) += imxdi.o
COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o
COBJS-$(CONFIG_RTC_M41T11) += m41t11.o
COBJS-$(CONFIG_RTC_M41T60) += m41t60.o
diff --git u-boot-2012.07/drivers/rtc/imxdi.c u-boot-2012.07/drivers/rtc/imxdi.c
new file mode 100644
index 0000000..985ce93
--- /dev/null
+++ u-boot-2012.07/drivers/rtc/imxdi.c
@@ -0,0 +1,244 @@
+/*
+ * (C) Copyright 2009-2012 ADVANSEE
+ * Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the Linux rtc-imxdi.c driver, which is:
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2010 Orex Computed Radiography
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for Freescale i.MX DryIce RTC
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/compat.h>
+#include <rtc.h>
+
+#if defined(CONFIG_CMD_DATE)
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/* DryIce Register Definitions */
+
+struct imxdi_regs {
+ u32 dtcmr; /* Time Counter MSB Reg */
+ u32 dtclr; /* Time Counter LSB Reg */
+ u32 dcamr; /* Clock Alarm MSB Reg */
+ u32 dcalr; /* Clock Alarm LSB Reg */
+ u32 dcr; /* Control Reg */
+ u32 dsr; /* Status Reg */
+ u32 dier; /* Interrupt Enable Reg */
+};
+
+#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
+
+#define DCR_TCE (1 << 3) /* Time Counter Enable */
+
+#define DSR_WBF (1 << 10) /* Write Busy Flag */
+#define DSR_WNF (1 << 9) /* Write Next Flag */
+#define DSR_WCF (1 << 8) /* Write Complete Flag */
+#define DSR_WEF (1 << 7) /* Write Error Flag */
+#define DSR_CAF (1 << 4) /* Clock Alarm Flag */
+#define DSR_NVF (1 << 1) /* Non-Valid Flag */
+#define DSR_SVF (1 << 0) /* Security Violation Flag */
+
+#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
+#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
+#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
+#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
+
+/* Driver Private Data */
+
+struct imxdi_data {
+ struct imxdi_regs __iomem *regs;
+ int init_done;
+};
+
+static struct imxdi_data data;
+
+/*
+ * This function attempts to clear the dryice write-error flag.
+ *
+ * A dryice write error is similar to a bus fault and should not occur in
+ * normal operation. Clearing the flag requires another write, so the root
+ * cause of the problem may need to be fixed before the flag can be cleared.
+ */
+static void clear_write_error(void)
+{
+ int cnt;
+
+ puts("### Warning: RTC - Register write error!\n");
+
+ /* clear the write error flag */
+ __raw_writel(DSR_WEF, &data.regs->dsr);
+
+ /* wait for it to take effect */
+ for (cnt = 0; cnt < 1000; cnt++) {
+ if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0)
+ return;
+ udelay(10);
+ }
+ puts("### Error: RTC - Cannot clear write-error flag!\n");
+}
+
+/*
+ * Write a dryice register and wait until it completes.
+ *
+ * Use interrupt flags to determine when the write has completed.
+ */
+#define DI_WRITE_WAIT(val, reg) \
+( \
+ /* do the register write */ \
+ __raw_writel((val), &data.regs->reg), \
+ \
+ di_write_wait((val), #reg) \
+)
+static int di_write_wait(u32 val, const char *reg)
+{
+ int cnt;
+ int ret = 0;
+ int rc = 0;
+
+ /* wait for the write to finish */
+ for (cnt = 0; cnt < 100; cnt++) {
+ if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) {
+ ret = 1;
+ break;
+ }
+ udelay(10);
+ }
+ if (ret == 0)
+ printf("### Warning: RTC - Write-wait timeout "
+ "val = 0x%.8x reg = %s\n", val, reg);
+
+ /* check for write error */
+ if (__raw_readl(&data.regs->dsr) & DSR_WEF) {
+ clear_write_error();
+ rc = -1;
+ }
+
+ return rc;
+}
+
+/*
+ * Initialize dryice hardware
+ */
+static int di_init(void)
+{
+ int rc = 0;
+
+ data.regs = (struct imxdi_regs __iomem *)IMX_DRYICE_BASE;
+
+ /* mask all interrupts */
+ __raw_writel(0, &data.regs->dier);
+
+ /* put dryice into valid state */
+ if (__raw_readl(&data.regs->dsr) & DSR_NVF) {
+ rc = DI_WRITE_WAIT(DSR_NVF | DSR_SVF, dsr);
+ if (rc)
+ goto err;
+ }
+
+ /* initialize alarm */
+ rc = DI_WRITE_WAIT(DCAMR_UNSET, dcamr);
+ if (rc)
+ goto err;
+ rc = DI_WRITE_WAIT(0, dcalr);
+ if (rc)
+ goto err;
+
+ /* clear alarm flag */
+ if (__raw_readl(&data.regs->dsr) & DSR_CAF) {
+ rc = DI_WRITE_WAIT(DSR_CAF, dsr);
+ if (rc)
+ goto err;
+ }
+
+ /* the timer won't count if it has never been written to */
+ if (__raw_readl(&data.regs->dtcmr) == 0) {
+ rc = DI_WRITE_WAIT(0, dtcmr);
+ if (rc)
+ goto err;
+ }
+
+ /* start keeping time */
+ if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) {
+ rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr);
+ if (rc)
+ goto err;
+ }
+
+ data.init_done = 1;
+ return 0;
+
+err:
+ return rc;
+}
+
+int rtc_get(struct rtc_time *tmp)
+{
+ unsigned long now;
+ int rc = 0;
+
+ if (!data.init_done) {
+ rc = di_init();
+ if (rc)
+ goto err;
+ }
+
+ now = __raw_readl(&data.regs->dtcmr);
+ to_tm(now, tmp);
+
+err:
+ return rc;
+}
+
+int rtc_set(struct rtc_time *tmp)
+{
+ unsigned long now;
+ int rc;
+
+ if (!data.init_done) {
+ rc = di_init();
+ if (rc)
+ goto err;
+ }
+
+ now = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ /* zero the fractional part first */
+ rc = DI_WRITE_WAIT(0, dtclr);
+ if (rc == 0)
+ rc = DI_WRITE_WAIT(now, dtcmr);
+
+err:
+ return rc;
+}
+
+void rtc_reset(void)
+{
+ di_init();
+}
+
+#endif
^ permalink raw reply related [flat|nested] 10+ messages in thread* [U-Boot] [PATCH v3] rtc: imxdi: Initial support
2012-08-08 14:52 ` [U-Boot] [PATCH v3] " Benoît Thébaudeau
@ 2012-08-09 13:58 ` Stefano Babic
0 siblings, 0 replies; 10+ messages in thread
From: Stefano Babic @ 2012-08-09 13:58 UTC (permalink / raw)
To: u-boot
On 08/08/2012 16:52, Beno?t Th?baudeau wrote:
> Add support for Freescale's i.MX DryIce RTC, present on i.MX25.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2] rtc: imxdi: Initial support
2012-08-08 14:29 ` Stefano Babic
2012-08-08 14:52 ` [U-Boot] [PATCH v3] " Benoît Thébaudeau
@ 2012-08-08 14:57 ` Benoît Thébaudeau
2012-08-08 15:24 ` Stefano Babic
1 sibling, 1 reply; 10+ messages in thread
From: Benoît Thébaudeau @ 2012-08-08 14:57 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On 08/08/2012 16:29, Stefano Babic wrote:
> On 08/08/2012 13:57, Beno?t Th?baudeau wrote:
> > Add support for Freescale's i.MX DryIce RTC, present on i.MX25.
> >
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > Cc: Wolfgang Denk <wd@denx.de>
> > Cc: Stefano Babic <sbabic@denx.de>
> > ---
>
> Hi Beno?t,
>
> checkpatch reports an error when I run your patch. Can you fix it ?
>
> ERROR: code indent should use tabs where possible
> #275: FILE: drivers/rtc/imxdi.c:229:
> +^I tmp->tm_hour, tmp->tm_min, tmp->tm_sec);$
I've just posted a v3 fixing that.
> Apart of that, here my:
>
> Acked-by: Stefano Babic <sbabic@denx.de>
Thanks. Who is supposed to apply it, and to which repository?
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2] rtc: imxdi: Initial support
2012-08-08 14:57 ` [U-Boot] [PATCH v2] " Benoît Thébaudeau
@ 2012-08-08 15:24 ` Stefano Babic
0 siblings, 0 replies; 10+ messages in thread
From: Stefano Babic @ 2012-08-08 15:24 UTC (permalink / raw)
To: u-boot
On 08/08/2012 16:57, Beno?t Th?baudeau wrote:
> Hi Stefano,
>
> On 08/08/2012 16:29, Stefano Babic wrote:
>> On 08/08/2012 13:57, Beno?t Th?baudeau wrote:
>>> Add support for Freescale's i.MX DryIce RTC, present on i.MX25.
>>>
>>> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
>>> Cc: Wolfgang Denk <wd@denx.de>
>>> Cc: Stefano Babic <sbabic@denx.de>
>>> ---
>>
>> Hi Beno?t,
>>
>> checkpatch reports an error when I run your patch. Can you fix it ?
>>
>> ERROR: code indent should use tabs where possible
>> #275: FILE: drivers/rtc/imxdi.c:229:
>> +^I tmp->tm_hour, tmp->tm_min, tmp->tm_sec);$
>
> I've just posted a v3 fixing that.
>
>> Apart of that, here my:
>>
>> Acked-by: Stefano Babic <sbabic@denx.de>
>
> Thanks. Who is supposed to apply it, and to which repository?
The driver is used by i.MX only - we have no strict rules, but I am
going to apply it to u-boot-imx.
Regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 10+ messages in thread