From: "Kumar, Udit" <u-kumar1@ti.com>
To: Hrushikesh Salunke <h-salunke@ti.com>, <trini@konsulko.com>,
<a-nandan@ti.com>, <m-chawdhry@ti.com>, <c-vankar@ti.com>,
<j-keerthy@ti.com>, <marek.vasut+renesas@mailbox.org>,
<n-francis@ti.com>, <jm@ti.com>, <anshuld@ti.com>,
<s-vadapalli@ti.com>, <ahalaney@redhat.com>,
<semen.protsenko@linaro.org>, <mkorpershoek@kernel.org>
Cc: <u-boot@lists.denx.de>, <danishanwar@ti.com>, <u-kumar1@ti.com>
Subject: Re: [PATCH v4 10/10] docs: board: ti: j784s4_evm: Add PCIe boot documentation
Date: Mon, 1 Dec 2025 22:17:35 +0530 [thread overview]
Message-ID: <90a2a3d6-e308-4507-9706-abc68c5ce2ee@ti.com> (raw)
In-Reply-To: <20251201110103.845413-11-h-salunke@ti.com>
On 12/1/2025 4:31 PM, Hrushikesh Salunke wrote:
> Add PCIe boot documentation for J784S4-EVM including boot mode switch
> settings, hardware setup requirements, endpoint configuration details
> and step-by-step boot procedure.
>
> Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
> ---
> doc/board/ti/j784s4_evm.rst | 267 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 267 insertions(+)
>
> diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst
> index 22442874110..0c9dad122a7 100644
> --- a/doc/board/ti/j784s4_evm.rst
> +++ b/doc/board/ti/j784s4_evm.rst
> @@ -280,6 +280,10 @@ http://www.ti.com/lit/zip/spruj52 under the `Boot Mode Pins` section.
> - 00000000
> - 01110000
>
> + * - PCIe
> + - 10001000
> + - 01010000
> +
> For SW7 and SW11, the switch state in the "ON" position = 1.
>
> Boot Mode Pins for AM69-SK
> @@ -311,6 +315,269 @@ section.
>
> For SW2, the switch state in the "ON" position = 1.
>
> +PCIe Boot
> +---------
> +
> +The J784S4 SoC supports booting over PCIe, allowing the device to function
> +as a PCIe endpoint and receive boot loader images from a PCIe root complex.
> +
> +Hardware Setup
> +^^^^^^^^^^^^^^
> +
> +To boot J784S4 via PCIe, the following hardware setup is required:
> +
> +1. Configure the boot mode switches on J784S4-EVM for PCIe boot:
> +
> + .. code-block:: text
> +
> + SW7: 01010000
> + SW11: 10001000
> +
> +2. Connect the J784S4-EVM (endpoint) to a PCIe root complex (e.g., x86 host)
> + using a PCIe cable. Both boards should be powered off before making the
> + connection.
> +
> +Endpoint Configuration
> +^^^^^^^^^^^^^^^^^^^^^^
> +
> +The following configuration options are enabled by default in
> +``j784s4_evm_r5_defconfig`` and ``j784s4_evm_a72_defconfig``:
> +
> +- ``CONFIG_SPL_PCI_DFU_BAR_SIZE``: Size of the PCIe BAR for DFU/boot image download
> +- ``CONFIG_SPL_PCI_DFU_VENDOR_ID``: PCIe vendor ID advertised by the endpoint
> +- ``CONFIG_SPL_PCI_DFU_DEVICE_ID``: PCIe device ID advertised by the endpoint
> +- ``CONFIG_SPL_PCI_DFU_MAGIC_WORD``: Magic word written by root complex to signal image transfer completion
> +- ``CONFIG_SPL_PCI_DFU_BOOT_PHASE``: Current boot phase indicator for root complex
> +
> +By default, PCIe root complex mode is enabled in the device tree. To enable
> +endpoint mode, build the boot loaders with the device tree overlay
> +``k3-j784s4-evm-pcie0-pcie1-ep.dtso``.
Do you think, you need bootph property in pcie_ep node ?
> +
> +PCIe Boot Procedure
> +^^^^^^^^^^^^^^^^^^^
> [..]+
> +The following steps describe how to boot J784S4 over PCIe:
> +
> [..]
prev parent reply other threads:[~2025-12-01 16:47 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-01 11:00 [PATCH v4 00/10] arm: k3: j784s4: Add PCIe boot support Hrushikesh Salunke
2025-12-01 11:00 ` [PATCH v4 01/10] arm: mach-k3: j784s4: Update SoC autogen data to enable PCIe boot Hrushikesh Salunke
2025-12-01 11:00 ` [PATCH v4 02/10] phy: cadence: Add config to enable Cadence Torrent PHY at SPL stage Hrushikesh Salunke
2025-12-01 11:00 ` [PATCH v4 03/10] phy: ti: Add config to enable J721E WIZ SERDES wrapper " Hrushikesh Salunke
2025-12-01 11:00 ` [PATCH v4 04/10] configs: j784s4_evm_r5_defconfig: Enable configs for PCIe boot Hrushikesh Salunke
2025-12-01 11:00 ` [PATCH v4 05/10] configs: j784s4_evm_a72_defconfig: " Hrushikesh Salunke
2025-12-01 11:00 ` [PATCH v4 06/10] configs: am69_sk_r5_defconfig: Disable PCIe boot configs Hrushikesh Salunke
2025-12-01 16:29 ` Kumar, Udit
2025-12-01 11:01 ` [PATCH v4 07/10] configs: am69_sk_a72_defconfig: " Hrushikesh Salunke
2025-12-01 11:01 ` [PATCH v4 08/10] configs: j742s2_evm_r5_defconfig: " Hrushikesh Salunke
2025-12-01 16:23 ` Kumar, Udit
2025-12-01 11:01 ` [PATCH v4 09/10] configs: j742s2_evm_a72_defconfig: " Hrushikesh Salunke
2025-12-01 11:01 ` [PATCH v4 10/10] docs: board: ti: j784s4_evm: Add PCIe boot documentation Hrushikesh Salunke
2025-12-01 16:47 ` Kumar, Udit [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=90a2a3d6-e308-4507-9706-abc68c5ce2ee@ti.com \
--to=u-kumar1@ti.com \
--cc=a-nandan@ti.com \
--cc=ahalaney@redhat.com \
--cc=anshuld@ti.com \
--cc=c-vankar@ti.com \
--cc=danishanwar@ti.com \
--cc=h-salunke@ti.com \
--cc=j-keerthy@ti.com \
--cc=jm@ti.com \
--cc=m-chawdhry@ti.com \
--cc=marek.vasut+renesas@mailbox.org \
--cc=mkorpershoek@kernel.org \
--cc=n-francis@ti.com \
--cc=s-vadapalli@ti.com \
--cc=semen.protsenko@linaro.org \
--cc=trini@konsulko.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox