* [PATCH 0/4] Bringup of SM7150 SoC
@ 2025-08-31 0:45 Jens Reidel
2025-08-31 0:45 ` [PATCH 1/4] clk/qcom: add driver for SM7150 GCC Jens Reidel
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Jens Reidel @ 2025-08-31 0:45 UTC (permalink / raw)
To: Casey Connolly, Neil Armstrong, Sumit Garg, Tom Rini,
Lukasz Majewski, Sean Anderson, Ilias Apalodimas, Sam Day,
Varadarajan Narayanan, Marek Vasut, Sughosh Ganu,
Balaji Selvanathan, Julius Lehmann, Aswin Murugan, Bhupesh Sharma,
Alexey Minnekhanov
Cc: Danila Tikhonov, Luca Weiss, u-boot-qcom, u-boot, Jens Reidel
This series adds a clock and pinctrl driver for the Qualcomm SM7150 SoC
and enables support for the SoC in the UFS driver.
The other necessary bits are part of Luca's SM6350 series [1] or were sent
separately.
All the drivers sent here are upstream in Linux already, however the
devicetrees aren't yet, but that shouldn't be a blocker for including
these drivers in U-Boot.
Tested on a couple of different Xiaomi devices, the Google Pixel 4a and
the Samsung Galaxy A71.
[1]: https://lore.kernel.org/u-boot/20250618-sm6350-bringup-v1-0-3cc22aab7a7a@fairphone.com/
Signed-off-by: Jens Reidel <adrian@mainlining.org>
---
Danila Tikhonov (4):
clk/qcom: add driver for SM7150 GCC
pinctrl: qcom: add SM7150 pinctrl driver
phy: qcom-qmp-ufs: Import SM7150 tables from Linux
configs: qcom_defconfig: Enable SM7150 GCC and Pinctrl
configs/qcom_defconfig | 2 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clock-sm7150.c | 250 ++++++++++++++++++++++++++
drivers/phy/qcom/phy-qcom-qmp-ufs.c | 61 +++++++
drivers/pinctrl/qcom/Kconfig | 7 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sm7150.c | 142 +++++++++++++++
8 files changed, 472 insertions(+)
create mode 100644 drivers/clk/qcom/clock-sm7150.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm7150.c
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] clk/qcom: add driver for SM7150 GCC
2025-08-31 0:45 [PATCH 0/4] Bringup of SM7150 SoC Jens Reidel
@ 2025-08-31 0:45 ` Jens Reidel
2025-08-31 0:46 ` [PATCH 2/4] pinctrl: qcom: add SM7150 pinctrl driver Jens Reidel
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Jens Reidel @ 2025-08-31 0:45 UTC (permalink / raw)
To: Casey Connolly, Neil Armstrong, Sumit Garg, Tom Rini,
Lukasz Majewski, Sean Anderson, Ilias Apalodimas, Sam Day,
Varadarajan Narayanan, Marek Vasut, Sughosh Ganu,
Balaji Selvanathan, Julius Lehmann, Aswin Murugan, Bhupesh Sharma,
Alexey Minnekhanov
Cc: Danila Tikhonov, Luca Weiss, u-boot-qcom, u-boot, Jens Reidel
From: Danila Tikhonov <danila@jiaxyga.com>
Add a clock driver for the SM7150 SoC. This driver can enable necessary
clocks for UART, UFS, USB, and MMC.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Co-developed-by: Jens Reidel <adrian@mainlining.org>
Signed-off-by: Jens Reidel <adrian@mainlining.org>
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clock-sm7150.c | 250 ++++++++++++++++++++++++++++++++
3 files changed, 259 insertions(+)
create mode 100644 drivers/clk/qcom/clock-sm7150.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 34e41461e72..ca913feb2af 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -103,6 +103,14 @@ config CLK_QCOM_SM6115
on the Snapdragon SM6115 SoC. This driver supports the clocks
and resets exposed by the GCC hardware block.
+config CLK_QCOM_SM7150
+ bool "Qualcomm SM7150 GCC"
+ select CLK_QCOM
+ help
+ Say Y here to enable support for the Global Clock Controller
+ on the Snapdragon SM7150 SoC. This driver supports the clocks
+ and resets exposed by the GCC hardware block.
+
config CLK_QCOM_SM8150
bool "Qualcomm SM8150 GCC"
select CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index b3d95b0faa3..9e8ca2bd69e 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_CLK_QCOM_QCS615) += clock-qcs615.o
obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
+obj-$(CONFIG_CLK_QCOM_SM7150) += clock-sm7150.o
obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o
obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o
obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o
diff --git a/drivers/clk/qcom/clock-sm7150.c b/drivers/clk/qcom/clock-sm7150.c
new file mode 100644
index 00000000000..8fe2076e55e
--- /dev/null
+++ b/drivers/clk/qcom/clock-sm7150.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm SM7150
+ *
+ * (C) Copyright 2025 Danila Tikhonov <danila@jiaxyga.com>
+ * (C) Copyright 2025 Jens Reidel <adrian@mainlining.org>
+ *
+ * Based on Linux Kernel driver
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,sm7150-gcc.h>
+
+#include "clock-qcom.h"
+
+#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf034
+#define USB3_PRIM_PHY_AUX_CLK_CMD_RCGR 0xf060
+
+#define SE8_UART_APPS_CMD_RCGR 0x18278
+#define GCC_SDCC2_APPS_CLK_SRC_REG 0x1400c
+
+#define APCS_GPLL7_STATUS 0x27000
+#define APCS_GPLLX_ENA_REG 0x52000
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+ F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+ F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+ F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+ F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+ F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+ F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+ F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+ F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+ F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
+ F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
+ F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
+ F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
+ F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+ F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+ F(9600000, CFG_CLK_SRC_CXO, 2, 0, 0),
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+ F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+ F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+ F(208000000, CFG_CLK_SRC_GPLL7, 4, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+ F(66666667, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+ F(133333333, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+ F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
+ F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ F(20000000, CFG_CLK_SRC_GPLL0_EVEN, 15, 0, 0),
+ F(40000000, CFG_CLK_SRC_GPLL0_EVEN, 7.5, 0, 0),
+ F(60000000, CFG_CLK_SRC_GPLL0, 10, 0, 0),
+ { }
+};
+
+static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ { }
+};
+
+static ulong sm7150_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+ const struct freq_tbl *freq;
+
+ if (clk->id < priv->data->num_clks)
+ debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
+
+ switch (clk->id) {
+ case GCC_QUPV3_WRAP1_S2_CLK: /* UART8 */
+ freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, SE8_UART_APPS_CMD_RCGR,
+ freq->pre_div, freq->m, freq->n, freq->src, 16);
+ return freq->freq;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
+ freq->pre_div, freq->m, freq->n, freq->src, 8);
+ return freq->freq;
+ case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+ freq = qcom_find_freq(ftbl_gcc_usb30_prim_mock_utmi_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
+ freq->pre_div, freq->m, freq->n, freq->src, 0);
+ return freq->freq;
+ case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
+ freq = qcom_find_freq(ftbl_gcc_usb3_prim_phy_aux_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CLK_CMD_RCGR,
+ freq->pre_div, freq->m, freq->n, freq->src, 0);
+ return freq->freq;
+ case GCC_SDCC2_APPS_CLK:
+ freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, GCC_SDCC2_APPS_CLK_SRC_REG,
+ freq->pre_div, freq->m, freq->n, freq->src, 8);
+ return freq->freq;
+ default:
+ return 0;
+ }
+}
+
+static const struct gate_clk sm7150_clks[] = {
+ GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x82024, BIT(0)),
+ GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x8201c, BIT(0)),
+ GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x502c, BIT(0)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, BIT(10)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, BIT(11)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, BIT(12)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, BIT(13)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x5200c, BIT(14)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x5200c, BIT(15)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x5200c, BIT(16)),
+ GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x5200c, BIT(17)),
+ GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x5200c, BIT(22)),
+ GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x5200c, BIT(23)),
+ GATE_CLK(GCC_QUPV3_WRAP1_S2_CLK, 0x5200c, BIT(24)),
+ GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x5200c, BIT(25)),
+ GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, BIT(26)),
+ GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, BIT(27)),
+ GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK, 0x5200c, BIT(28)),
+ GATE_CLK(GCC_QUPV3_WRAP1_S7_CLK, 0x5200c, BIT(29)),
+ GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x5200c, BIT(6)),
+ GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x5200c, BIT(7)),
+ GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x5200c, BIT(20)),
+ GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x5200c, BIT(21)),
+ GATE_CLK(GCC_SDCC1_AHB_CLK, 0x12008, BIT(0)),
+ GATE_CLK(GCC_SDCC1_APPS_CLK, 0x1200c, BIT(0)),
+ GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x12040, BIT(0)),
+ GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)),
+ GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)),
+ GATE_CLK(GCC_SDCC4_AHB_CLK, 0x16008, BIT(0)),
+ GATE_CLK(GCC_SDCC4_APPS_CLK, 0x16004, BIT(0)),
+ GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)),
+ GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0)),
+ GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77038, BIT(0)),
+ GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77090, BIT(0)),
+ GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x77094, BIT(0)),
+ GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0)),
+ GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0)),
+ GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7708c, BIT(0)),
+ GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x0f010, BIT(0)),
+ GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x0f018, BIT(0)),
+ GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x0f014, BIT(0)),
+ GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c010, BIT(0)),
+ GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x0f050, BIT(0)),
+ GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x0f054, BIT(0)),
+ GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x0f058, BIT(0)),
+ GATE_CLK(GCC_USB_PHY_CFG_AHB2PHY_CLK, 0x6a004, BIT(0)),
+};
+
+static int sm7150_clk_enable(struct clk *clk)
+{
+ struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (priv->data->num_clks < clk->id) {
+ debug("%s: unknown clk id %lu\n", __func__, clk->id);
+ return 0;
+ }
+
+ debug("%s: clk %s\n", __func__, sm7150_clks[clk->id].name);
+
+ switch (clk->id) {
+ case GCC_AGGRE_USB3_PRIM_AXI_CLK:
+ qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
+ fallthrough;
+ case GCC_USB30_PRIM_MASTER_CLK:
+ qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
+ qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
+ break;
+ }
+
+ return qcom_gate_clk_en(priv, clk->id);
+}
+
+static const struct qcom_reset_map sm7150_gcc_resets[] = {
+ [GCC_UFS_PHY_BCR] = { 0x77000 },
+ [GCC_USB30_PRIM_BCR] = { 0xf000 },
+ [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
+ [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
+ [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
+ [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
+};
+
+static const struct qcom_power_map sm7150_gdscs[] = {
+ [PCIE_0_GDSC] = { 0x6b004 },
+ [UFS_PHY_GDSC] = { 0x77004 },
+ [USB30_PRIM_GDSC] = { 0xf004 },
+};
+
+static const phys_addr_t sm7150_rcg_addrs[] = {
+ 0x10f01c, // USB30_PRIM_MASTER_CLK_CMD_RCGR
+ 0x10f034, // USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR
+ 0x10f060, // USB3_PRIM_PHY_AUX_CLK_CMD_RCGR,
+};
+
+static const char *const sm7150_rcg_names[] = {
+ "USB30_PRIM_MASTER_CLK",
+ "USB30_PRIM_MOCK_UTMI_CLK",
+ "USB3_PRIM_PHY_AUX_CLK",
+};
+
+static struct msm_clk_data sm7150_gcc_data = {
+ .resets = sm7150_gcc_resets,
+ .num_resets = ARRAY_SIZE(sm7150_gcc_resets),
+ .clks = sm7150_clks,
+ .num_clks = ARRAY_SIZE(sm7150_clks),
+
+ .power_domains = sm7150_gdscs,
+ .num_power_domains = ARRAY_SIZE(sm7150_gdscs),
+
+ .enable = sm7150_clk_enable,
+ .set_rate = sm7150_clk_set_rate,
+
+ .dbg_rcg_addrs = sm7150_rcg_addrs,
+ .num_rcgs = ARRAY_SIZE(sm7150_rcg_addrs),
+ .dbg_rcg_names = sm7150_rcg_names,
+};
+
+static const struct udevice_id gcc_sm7150_of_match[] = {
+ { .compatible = "qcom,sm7150-gcc", .data = (ulong)&sm7150_gcc_data, },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gcc_sm7150) = {
+ .name = "gcc_sm7150",
+ .id = UCLASS_NOP,
+ .of_match = gcc_sm7150_of_match,
+ .bind = qcom_cc_bind,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/4] pinctrl: qcom: add SM7150 pinctrl driver
2025-08-31 0:45 [PATCH 0/4] Bringup of SM7150 SoC Jens Reidel
2025-08-31 0:45 ` [PATCH 1/4] clk/qcom: add driver for SM7150 GCC Jens Reidel
@ 2025-08-31 0:46 ` Jens Reidel
2025-08-31 0:46 ` [PATCH 3/4] phy: qcom-qmp-ufs: Import SM7150 tables from Linux Jens Reidel
2025-08-31 0:46 ` [PATCH 4/4] configs: qcom_defconfig: Enable SM7150 GCC and Pinctrl Jens Reidel
3 siblings, 0 replies; 6+ messages in thread
From: Jens Reidel @ 2025-08-31 0:46 UTC (permalink / raw)
To: Casey Connolly, Neil Armstrong, Sumit Garg, Tom Rini,
Lukasz Majewski, Sean Anderson, Ilias Apalodimas, Sam Day,
Varadarajan Narayanan, Marek Vasut, Sughosh Ganu,
Balaji Selvanathan, Julius Lehmann, Aswin Murugan, Bhupesh Sharma,
Alexey Minnekhanov
Cc: Danila Tikhonov, Luca Weiss, u-boot-qcom, u-boot, Jens Reidel
From: Danila Tikhonov <danila@jiaxyga.com>
This SoC features a pinctrl block with north, south, and west tiles
accessible to the AP.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Co-developed-by: Jens Reidel <adrian@mainlining.org>
Signed-off-by: Jens Reidel <adrian@mainlining.org>
---
drivers/pinctrl/qcom/Kconfig | 7 ++
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sm7150.c | 142 ++++++++++++++++++++++++++
3 files changed, 150 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sm7150.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 21f81b66099..d83ede21c75 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -89,6 +89,13 @@ config PINCTRL_QCOM_SM6115
Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC,
as well as the associated GPIO driver.
+config PINCTRL_QCOM_SM7150
+ bool "Qualcomm SM7150 GCC"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon SM7150 SoC,
+ as well as the associated GPIO driver.
+
config PINCTRL_QCOM_SM8150
bool "Qualcomm SM8150 Pinctrl"
select PINCTRL_QCOM
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 6cb53838e71..73c08a02a3d 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SC7280) += pinctrl-sc7280.o
obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
+obj-$(CONFIG_PINCTRL_QCOM_SM7150) += pinctrl-sm7150.o
obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
obj-$(CONFIG_PINCTRL_QCOM_SM8250) += pinctrl-sm8250.o
obj-$(CONFIG_PINCTRL_QCOM_SM8550) += pinctrl-sm8550.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sm7150.c b/drivers/pinctrl/qcom/pinctrl-sm7150.c
new file mode 100644
index 00000000000..435ba39b1db
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sm7150.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Pinctrl driver for Qualcomm SM7150
+ *
+ * (C) Copyright 2025 Danila Tikhonov <danila@jiaxyga.com>
+ * (C) Copyright 2025 Jens Reidel <adrian@mainlining.org>
+ *
+ * Based on Linux Kernel driver
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define WEST 0x00000000
+#define NORTH 0x00400000
+#define SOUTH 0x00800000
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ { "qup12", 1 },
+ { "gpio", 0 },
+ { "sdc2_clk", 0 } /* special pin GPIO124 */
+};
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ }
+
+#define UFS_RESET(pg_name, offset) \
+ { \
+ .name = pg_name, \
+ .ctl_reg = offset, \
+ .io_reg = offset + 0x4, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ }
+
+static const struct msm_special_pin_data msm_special_pins_data[] = {
+ [0] = UFS_RESET("ufs_reset", 0x9f000),
+ [1] = SDC_QDSD_PINGROUP("sdc1_rclk", WEST + 0x9a000, 15, 0),
+ [2] = SDC_QDSD_PINGROUP("sdc1_clk", WEST + 0x9a000, 13, 6),
+ [3] = SDC_QDSD_PINGROUP("sdc1_cmd", WEST + 0x9a000, 11, 3),
+ [4] = SDC_QDSD_PINGROUP("sdc1_data", WEST + 0x9a000, 9, 0),
+ [5] = SDC_QDSD_PINGROUP("sdc2_clk", SOUTH + 0x98000, 14, 6),
+ [6] = SDC_QDSD_PINGROUP("sdc2_cmd", SOUTH + 0x98000, 11, 3),
+ [7] = SDC_QDSD_PINGROUP("sdc2_data", SOUTH + 0x98000, 9, 0),
+};
+
+static const unsigned int sm7150_pin_offsets[] = {
+ [0] = SOUTH, [1] = SOUTH, [2] = SOUTH, [3] = SOUTH,
+ [4] = NORTH, [5] = NORTH, [6] = NORTH, [7] = NORTH,
+ [8] = NORTH, [9] = NORTH, [10] = NORTH, [11] = NORTH,
+ [12] = SOUTH, [13] = SOUTH, [14] = SOUTH, [15] = SOUTH,
+ [16] = SOUTH, [17] = SOUTH, [18] = SOUTH, [19] = SOUTH,
+ [20] = SOUTH, [21] = SOUTH, [22] = SOUTH, [23] = SOUTH,
+ [24] = SOUTH, [25] = SOUTH, [26] = SOUTH, [27] = SOUTH,
+ [28] = SOUTH, [29] = NORTH, [30] = SOUTH, [31] = WEST,
+ [32] = NORTH, [33] = NORTH, [34] = SOUTH, [35] = SOUTH,
+ [36] = SOUTH, [37] = SOUTH, [38] = SOUTH, [39] = SOUTH,
+ [40] = SOUTH, [41] = SOUTH, [42] = NORTH, [43] = NORTH,
+ [44] = NORTH, [45] = NORTH, [46] = NORTH, [47] = NORTH,
+ [48] = WEST, [49] = WEST, [50] = WEST, [51] = WEST,
+ [52] = WEST, [53] = WEST, [54] = WEST, [55] = WEST,
+ [56] = WEST, [57] = WEST, [58] = WEST, [59] = NORTH,
+ [60] = NORTH, [61] = NORTH, [62] = NORTH, [63] = NORTH,
+ [64] = NORTH, [65] = NORTH, [66] = NORTH, [67] = NORTH,
+ [68] = NORTH, [69] = NORTH, [70] = NORTH, [71] = NORTH,
+ [72] = NORTH, [73] = NORTH, [74] = WEST, [75] = WEST,
+ [76] = WEST, [77] = WEST, [78] = WEST, [79] = WEST,
+ [80] = WEST, [81] = WEST, [82] = WEST, [83] = WEST,
+ [84] = WEST, [85] = WEST, [86] = NORTH, [87] = NORTH,
+ [88] = NORTH, [89] = NORTH, [90] = NORTH, [91] = NORTH,
+ [92] = NORTH, [93] = NORTH, [94] = SOUTH, [95] = WEST,
+ [96] = WEST, [97] = WEST, [98] = WEST, [99] = WEST,
+ [100] = WEST, [101] = NORTH, [102] = NORTH, [103] = NORTH,
+ [104] = WEST, [105] = NORTH, [106] = NORTH, [107] = WEST,
+ [108] = SOUTH, [109] = SOUTH, [110] = NORTH, [111] = NORTH,
+ [112] = NORTH, [113] = NORTH, [114] = NORTH, [115] = NORTH,
+ [116] = NORTH, [117] = NORTH, [118] = NORTH,
+};
+
+static const char *sm7150_get_function_name(struct udevice *dev, unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sm7150_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ if (selector >= 119 && selector <= 126)
+ snprintf(pin_name, MAX_PIN_NAME_LEN,
+ msm_special_pins_data[selector - 119].name);
+ else
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+ return pin_name;
+}
+
+static int sm7150_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sm7150_data = {
+ .pin_data = {
+ .pin_offsets = sm7150_pin_offsets,
+ .pin_count = 126,
+ .special_pins_start = 119,
+ .special_pins_data = msm_special_pins_data,
+ },
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = sm7150_get_function_name,
+ .get_function_mux = sm7150_get_function_mux,
+ .get_pin_name = sm7150_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+ { .compatible = "qcom,sm7150-tlmm", .data = (ulong)&sm7150_data },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_sm7150) = {
+ .name = "pinctrl_sm7150",
+ .id = UCLASS_NOP,
+ .of_match = msm_pinctrl_ids,
+ .ops = &msm_pinctrl_ops,
+ .bind = msm_pinctrl_bind,
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/4] phy: qcom-qmp-ufs: Import SM7150 tables from Linux
2025-08-31 0:45 [PATCH 0/4] Bringup of SM7150 SoC Jens Reidel
2025-08-31 0:45 ` [PATCH 1/4] clk/qcom: add driver for SM7150 GCC Jens Reidel
2025-08-31 0:46 ` [PATCH 2/4] pinctrl: qcom: add SM7150 pinctrl driver Jens Reidel
@ 2025-08-31 0:46 ` Jens Reidel
2025-09-01 7:56 ` Neil Armstrong
2025-08-31 0:46 ` [PATCH 4/4] configs: qcom_defconfig: Enable SM7150 GCC and Pinctrl Jens Reidel
3 siblings, 1 reply; 6+ messages in thread
From: Jens Reidel @ 2025-08-31 0:46 UTC (permalink / raw)
To: Casey Connolly, Neil Armstrong, Sumit Garg, Tom Rini,
Lukasz Majewski, Sean Anderson, Ilias Apalodimas, Sam Day,
Varadarajan Narayanan, Marek Vasut, Sughosh Ganu,
Balaji Selvanathan, Julius Lehmann, Aswin Murugan, Bhupesh Sharma,
Alexey Minnekhanov
Cc: Danila Tikhonov, Luca Weiss, u-boot-qcom, u-boot, Jens Reidel
From: Danila Tikhonov <danila@jiaxyga.com>
Import the init sequence for the UFS on SM7150.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Signed-off-by: Jens Reidel <adrian@mainlining.org>
---
drivers/phy/qcom/phy-qcom-qmp-ufs.c | 61 +++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
index f3c606847fb..a2a0e226f0c 100644
--- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
@@ -221,6 +221,36 @@ static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
};
+static const struct qmp_ufs_init_tbl sm7150_ufsphy_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
+};
+
+static const struct qmp_ufs_init_tbl sm7150_ufsphy_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+};
+
static const struct qmp_ufs_init_tbl sm8150_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
@@ -1018,6 +1048,36 @@ static const struct qmp_ufs_cfg sm8150_ufsphy_cfg = {
.no_pcs_sw_reset = false,
};
+static const struct qmp_ufs_cfg sm7150_ufsphy_cfg = {
+ .lanes = 1,
+
+ .offsets = &qmp_ufs_offsets,
+
+ .tbls = {
+ .serdes = sdm845_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
+ .tx = sdm845_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
+ .rx = sm7150_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm7150_ufsphy_rx),
+ .pcs = sm7150_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm7150_ufsphy_pcs),
+ },
+ .tbls_hs_b = {
+ .serdes = sdm845_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
+ },
+ .clk_list = sdm845_ufs_phy_clk_l,
+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+ .vreg_list = qmp_ufs_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l),
+ .reset_list = qmp_ufs_reset_l,
+ .num_resets = ARRAY_SIZE(qmp_ufs_reset_l),
+ .regs = ufsphy_v3_regs_layout,
+
+ .no_pcs_sw_reset = true,
+};
+
static const struct qmp_ufs_cfg sm8250_ufsphy_cfg = {
.lanes = 2,
@@ -1593,6 +1653,7 @@ static struct phy_ops qmp_ufs_ops = {
static const struct udevice_id qmp_ufs_ids[] = {
{ .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, },
{ .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
+ { .compatible = "qcom,sm7150-qmp-ufs-phy", .data = (ulong)&sm7150_ufsphy_cfg },
{ .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg },
{ .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg },
{ .compatible = "qcom,qcs8300-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg },
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] configs: qcom_defconfig: Enable SM7150 GCC and Pinctrl
2025-08-31 0:45 [PATCH 0/4] Bringup of SM7150 SoC Jens Reidel
` (2 preceding siblings ...)
2025-08-31 0:46 ` [PATCH 3/4] phy: qcom-qmp-ufs: Import SM7150 tables from Linux Jens Reidel
@ 2025-08-31 0:46 ` Jens Reidel
3 siblings, 0 replies; 6+ messages in thread
From: Jens Reidel @ 2025-08-31 0:46 UTC (permalink / raw)
To: Casey Connolly, Neil Armstrong, Sumit Garg, Tom Rini,
Lukasz Majewski, Sean Anderson, Ilias Apalodimas, Sam Day,
Varadarajan Narayanan, Marek Vasut, Sughosh Ganu,
Balaji Selvanathan, Julius Lehmann, Aswin Murugan, Bhupesh Sharma,
Alexey Minnekhanov
Cc: Danila Tikhonov, Luca Weiss, u-boot-qcom, u-boot, Jens Reidel
From: Danila Tikhonov <danila@jiaxyga.com>
Enable the necessary drivers so that SM7150 devices can boot with
qcom_defconfig.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Signed-off-by: Jens Reidel <adrian@mainlining.org>
---
configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 86d7de89e77..42a25b4a18a 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -60,6 +60,7 @@ CONFIG_CLK_QCOM_QCS8300=y
CONFIG_CLK_QCOM_SA8775P=y
CONFIG_CLK_QCOM_SDM845=y
CONFIG_CLK_QCOM_SM6115=y
+CONFIG_CLK_QCOM_SM7150=y
CONFIG_CLK_QCOM_SM8150=y
CONFIG_CLK_QCOM_SM8250=y
CONFIG_CLK_QCOM_SM8550=y
@@ -112,6 +113,7 @@ CONFIG_PINCTRL_QCOM_SA8775P=y
CONFIG_PINCTRL_QCOM_SC7280=y
CONFIG_PINCTRL_QCOM_SDM845=y
CONFIG_PINCTRL_QCOM_SM6115=y
+CONFIG_PINCTRL_QCOM_SM7150=y
CONFIG_PINCTRL_QCOM_SM8150=y
CONFIG_PINCTRL_QCOM_SM8250=y
CONFIG_PINCTRL_QCOM_SM8550=y
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/4] phy: qcom-qmp-ufs: Import SM7150 tables from Linux
2025-08-31 0:46 ` [PATCH 3/4] phy: qcom-qmp-ufs: Import SM7150 tables from Linux Jens Reidel
@ 2025-09-01 7:56 ` Neil Armstrong
0 siblings, 0 replies; 6+ messages in thread
From: Neil Armstrong @ 2025-09-01 7:56 UTC (permalink / raw)
To: Jens Reidel, Casey Connolly, Sumit Garg, Tom Rini,
Lukasz Majewski, Sean Anderson, Ilias Apalodimas, Sam Day,
Varadarajan Narayanan, Marek Vasut, Sughosh Ganu,
Balaji Selvanathan, Julius Lehmann, Aswin Murugan, Bhupesh Sharma,
Alexey Minnekhanov
Cc: Danila Tikhonov, Luca Weiss, u-boot-qcom, u-boot
On 31/08/2025 02:46, Jens Reidel wrote:
> From: Danila Tikhonov <danila@jiaxyga.com>
>
> Import the init sequence for the UFS on SM7150.
>
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> Signed-off-by: Jens Reidel <adrian@mainlining.org>
> ---
> drivers/phy/qcom/phy-qcom-qmp-ufs.c | 61 +++++++++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
> index f3c606847fb..a2a0e226f0c 100644
> --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c
> @@ -221,6 +221,36 @@ static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
> };
>
> +static const struct qmp_ufs_init_tbl sm7150_ufsphy_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
> +};
> +
> +static const struct qmp_ufs_init_tbl sm7150_ufsphy_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> static const struct qmp_ufs_init_tbl sm8150_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
> QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
> @@ -1018,6 +1048,36 @@ static const struct qmp_ufs_cfg sm8150_ufsphy_cfg = {
> .no_pcs_sw_reset = false,
> };
>
> +static const struct qmp_ufs_cfg sm7150_ufsphy_cfg = {
> + .lanes = 1,
> +
> + .offsets = &qmp_ufs_offsets,
> +
> + .tbls = {
> + .serdes = sdm845_ufsphy_serdes,
> + .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
> + .tx = sdm845_ufsphy_tx,
> + .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
> + .rx = sm7150_ufsphy_rx,
> + .rx_num = ARRAY_SIZE(sm7150_ufsphy_rx),
> + .pcs = sm7150_ufsphy_pcs,
> + .pcs_num = ARRAY_SIZE(sm7150_ufsphy_pcs),
> + },
> + .tbls_hs_b = {
> + .serdes = sdm845_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
> + },
> + .clk_list = sdm845_ufs_phy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> + .vreg_list = qmp_ufs_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l),
> + .reset_list = qmp_ufs_reset_l,
> + .num_resets = ARRAY_SIZE(qmp_ufs_reset_l),
> + .regs = ufsphy_v3_regs_layout,
> +
> + .no_pcs_sw_reset = true,
> +};
> +
> static const struct qmp_ufs_cfg sm8250_ufsphy_cfg = {
> .lanes = 2,
>
> @@ -1593,6 +1653,7 @@ static struct phy_ops qmp_ufs_ops = {
> static const struct udevice_id qmp_ufs_ids[] = {
> { .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, },
> { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg },
> + { .compatible = "qcom,sm7150-qmp-ufs-phy", .data = (ulong)&sm7150_ufsphy_cfg },
> { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg },
> { .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg },
> { .compatible = "qcom,qcs8300-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg },
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-09-01 7:56 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-31 0:45 [PATCH 0/4] Bringup of SM7150 SoC Jens Reidel
2025-08-31 0:45 ` [PATCH 1/4] clk/qcom: add driver for SM7150 GCC Jens Reidel
2025-08-31 0:46 ` [PATCH 2/4] pinctrl: qcom: add SM7150 pinctrl driver Jens Reidel
2025-08-31 0:46 ` [PATCH 3/4] phy: qcom-qmp-ufs: Import SM7150 tables from Linux Jens Reidel
2025-09-01 7:56 ` Neil Armstrong
2025-08-31 0:46 ` [PATCH 4/4] configs: qcom_defconfig: Enable SM7150 GCC and Pinctrl Jens Reidel
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