Re: [PATCH v1 25/26] imx8mq: synchronise device tree with linux

Heiko Thiery
2022-09-06T12:36:36Z

Hi Marcel and all,

Am Do., 21. Juli 2022 um 15:48 Uhr schrieb Marcel Ziswiler
<marcel@ziswiler.com>:
>
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Synchronise device tree with linux v5.19-rc5.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
>
> arch/arm/dts/imx8mq-evk.dts | 65 ++++++-

I just tried the current master on imx8mq-evk and figured out that it
doesn't start. I did a git bisect and saw that the dtb sync seems to
be responsible for that. Can anyone else confirm that?

> arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts | 3 +-
> arch/arm/dts/imx8mq-mnt-reform2.dts | 144 ++++++++++++++-
> arch/arm/dts/imx8mq-nitrogen-som.dtsi | 15 +-
> arch/arm/dts/imx8mq-phanbell.dts | 86 +++++++--
> arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi | 2 +
> arch/arm/dts/imx8mq-pico-pi.dts | 67 ++++---
> arch/arm/dts/imx8mq.dtsi | 204 +++++++++++++--------
> include/dt-bindings/clock/imx8mq-clock.h | 19 --
> include/dt-bindings/power/imx8mq-power.h | 3 +
> 10 files changed, 452 insertions(+), 156 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
> index 85b045253a0..99fed35168e 100644
> --- a/arch/arm/dts/imx8mq-evk.dts
> +++ b/arch/arm/dts/imx8mq-evk.dts
> @@ -27,6 +27,17 @@
> clock-frequency = <100000000>;
> };
>
> + reg_pcie1: regulator-pcie {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie1_reg>;
> + regulator-name = "MPCIE_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> reg_usdhc2_vmmc: regulator-vsd-3v3 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_reg_usdhc2>;
> @@ -123,6 +134,7 @@
>
> &ddrc {
> operating-points-v2 = <&ddrc_opp_table>;
> + status = "okay";
>
> ddrc_opp_table: opp-table {
> compatible = "operating-points-v2";
> @@ -169,6 +181,11 @@
> reg = <0>;
> reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> reset-assert-us = <10000>;
> + qca,disable-smarteee;
> + vddio-supply = <&vddh>;
> +
> + vddh: vddh-regulator {
> + };
> };
> };
> };
> @@ -318,6 +335,21 @@
> <&clk IMX8MQ_CLK_PCIE1_PHY>,
> <&pcie0_refclk>;
> clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> + vph-supply = <&vgen5_reg>;
> + status = "okay";
> +};
> +
> +&pcie1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie1>;
> + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
> + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> + <&clk IMX8MQ_CLK_PCIE2_AUX>,
> + <&clk IMX8MQ_CLK_PCIE2_PHY>,
> + <&pcie0_refclk>;
> + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> + vpcie-supply = <&reg_pcie1>;
> + vph-supply = <&vgen5_reg>;
> status = "okay";
> };
>
> @@ -325,6 +357,10 @@
> power-supply = <&sw1a_reg>;
> };
>
> +&pgc_vpu {
> + power-supply = <&sw1c_reg>;
> +};
> +
> &qspi0 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_qspi>;
> @@ -336,6 +372,8 @@
> #size-cells = <1>;
> compatible = "micron,n25q256a", "jedec,spi-nor";
> spi-max-frequency = <29000000>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>;
> };
> };
>
> @@ -402,9 +440,9 @@
> assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
> assigned-clock-rates = <200000000>;
> pinctrl-names = "default", "state_100mhz", "state_200mhz";
> - pinctrl-0 = <&pinctrl_usdhc2>;
> - pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
> - pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> vmmc-supply = <&reg_usdhc2_vmmc>;
> status = "okay";
> @@ -422,7 +460,6 @@
> fsl,pins = <
> MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
> >;
> -
> };
>
> pinctrl_fec1: fec1grp {
> @@ -471,6 +508,19 @@
> >;
> };
>
> + pinctrl_pcie1: pcie1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
> + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
> + >;
> + };
> +
> + pinctrl_pcie1_reg: pcie1reggrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
> + >;
> + };
> +
> pinctrl_qspi: qspigrp {
> fsl,pins = <
> MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
> @@ -479,7 +529,6 @@
> MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
> MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
> MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
> -
> >;
> };
>
> @@ -564,6 +613,12 @@
> >;
> };
>
> + pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
> + >;
> + };
> +
> pinctrl_usdhc2: usdhc2grp {
> fsl,pins = <
> MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83

[SNIP]

--
Heiko