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[213.161.4.249]) by smtp.gmail.com with ESMTPSA id h15sm9229125wrq.88.2021.06.11.23.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jun 2021 23:08:51 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: andre.przywara@arm.com Cc: jagan@amarulasolutions.com, u-boot@lists.denx.de, linux-sunxi@lists.linux.dev Subject: Re: Re: [PATCH] configs: OrangePi PC2: Update defaults Date: Sat, 12 Jun 2021 08:08:51 +0200 Message-ID: <9487261.lNKWQbxSyI@kista> In-Reply-To: <2418795.6bcLzA2rA2@kista> References: <20210607174245.480188-1-jernej.skrabec@gmail.com> <2418795.6bcLzA2rA2@kista> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Dne sobota, 12. junij 2021 ob 07:50:27 CEST je Jernej =C5=A0krabec napisal(= a): > Dne ponedeljek, 07. junij 2021 ob 19:42:45 CEST je Jernej Skrabec=20 napisal(a): > > OrangePi PC2 board has DRAM with ODT, so enable it. ZQ value is also > > slightly different in vendor images, so update it as well. H5 SoC is > > also connected to voltage regulator. It's default value is pretty low, > > so in order to avoid instability, enable driver for it and set it to > > appropriate voltage. > >=20 > > Signed-off-by: Jernej Skrabec > > --- > > configs/orangepi_pc2_defconfig | 6 ++++-- > > 1 file changed, 4 insertions(+), 2 deletions(-) > >=20 > > diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defc= onfig > > index f72ffe27b26c..5e4cca793f53 100644 > > --- a/configs/orangepi_pc2_defconfig > > +++ b/configs/orangepi_pc2_defconfig > > @@ -3,13 +3,15 @@ CONFIG_ARCH_SUNXI=3Dy > > CONFIG_SPL=3Dy > > CONFIG_MACH_SUN50I_H5=3Dy > > CONFIG_DRAM_CLK=3D672 > > -CONFIG_DRAM_ZQ=3D3881977 > > -# CONFIG_DRAM_ODT_EN is not set > > +CONFIG_DRAM_ZQ=3D4145117 I re-checked BSP DT and original ZQ value is correct. So this patch should= =20 only enable ODT, which is really enabled in BSP and DRAM ICs support it. Best regards, Jernej > > CONFIG_MACPWR=3D"PD6" > > CONFIG_SPL_SPI_SUNXI=3Dy > > +CONFIG_SPL_I2C_SUPPORT=3Dy > > CONFIG_DEFAULT_DEVICE_TREE=3D"sun50i-h5-orangepi-pc2" > > # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set > > CONFIG_SUN8I_EMAC=3Dy > > +CONFIG_SY8106A_POWER=3Dy > > +CONFIG_SY8106A_VOUT1_VOLT=3D1100 >=20 > I'm not sure if voltage regulator adjustment needs to be enabled. By=20 default,=20 > it's set to 1.1 V using resistor divider. However, it can be still needed= if=20 > board is rebooted and OS set it to lower value before reboot. >=20 > Best regards, > Jernej >=20 > > CONFIG_USB_EHCI_HCD=3Dy > > CONFIG_USB_OHCI_HCD=3Dy > > CONFIG_USB_MUSB_GADGET=3Dy > > --=20 > > 2.31.1 > >=20 > >=20 >=20 >=20 >=20