[PATCH 2/2] [RFC] clk: stm32mp1: Handle SoC speed grade configs

Marek Vasut
2020-06-14T15:23:38Z

On 5/13/20 11:12 AM, Patrick DELAUNAY wrote:
> Dear Marek,

Hi,

[...]

>> @@ -1783,6 +1800,11 @@ static int stm32mp1_clktree(struct udevice *dev)
>> continue;
>>
>> fracv = ofnode_read_u32_default(plloff[i], "frac", 0);
>> + if (!fracv) {
>> + fracv = ofnode_read_u32_default(plloff[i],
>> + stm32mp1_is_df() ? "frac-df" : "frac-ac",
>> + 0);
>> + }
>> pll_config(priv, i, pllcfg[i], fracv);
>> ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB);
>> if (!ret) {
>> --
>> 2.25.1
>
> The 2 speed grade will be supported with OPP information and HW support,present in kernel device tree (upstream in progress)

Great, thanks!