[U-Boot-Users] IBM/AMCC 440EP ethernet question

[U-Boot-Users] IBM/AMCC 440EP ethernet question

[Miles Gazic]

I found one part of the problem.  The 0x8100 I was writing included the
reset bit.  When I take that out I can set the command register and read
it back.  We can now get a link 10Mbps, 100Mbps doesn't work.
Auto-negotiate sometimes doesn't work, and sometimes ends up at 10Mbps
speed even though both sides should do 100Mbps.  We are making progress
now at least.

I went through the register definitions and bit field definitions again
to see if any I am using aren't right for the 440ep, and I noticed that
EMAC_TRTR_128 is 0x01000000 for both 440gx_enet.h and 405gp_enet.h in
U-Boot.  For the EP, only the 5 most significant bits aren't reserved,
and the value in my user manual for EMAC_TRTR_128 is binary 00001.
Seems likely that it's the same for other 440s and 405s, and someone
made a typo.  From the most significant end of the register, 00001... =
0000 1000 = 0x08 != 0x01.  It's page 897 of ppc440ep_um.pdf, and that's the only
user manual I've got.  If anyone has another 440 or 405 user manual
handy and would like to check this out I'd appreciate it.  Otherwise
I'll download a couple other user manuals and if they match mine I'll
figure out how to submit a bug report.

Thanks,
Miles


On Tue, 2005-02-15 at 21:09 -0800, Miles Gazic wrote:
> I'm using a 440EP with MII mode selected, and a Broadcom AC101L phy.
> Autonegotiation was failing, so as an experiment, I tried replacing the
> start of autonegotiation in 440gx_enet.c, with setting the speed
> manually.  I did a miiphy_write to PHY_BMCR (the control register) with
> 0x8100 (which should specify 10mbps, full duplex).  The miiphy_write
> returns  0 which means it doesn't think it failed, but when I look at
> the value in the control register as spit out by miiphy_dump, it is
> still 0x3000 (which is 100mbps and half-duplex), which is the same value
> I always see there.
> 
> I don't think this is just a U-boot problem because I can duplicate
> what's happening using just a Abatron BDI2000.  When I write a
> 0x81002400 into the EMAC_STACR register (which should set the control
> register of the phy to 0x8100), and then write a 0x00001400 into
> EMAC_STACR (which should request a read of the same register), and then
> look at the EMAC_STACR register in the debugger, it has the same 0x3000
> as I see in U-Boot.  It seems likely to me though that if anyone has
> gotten the 440EP to work with MII in U-Boot, then they might be able to
> shed some light on what is going wrong for me.
> 
> Any advice is appreciated,
> Miles

[U-Boot-Users] IBM/AMCC 440EP ethernet question

[Bradley Remedios]

On Fri, 18 Feb 2005 05:20:59 -0800 (GMT-08:00), Miles Gazic
<mgazic@earthlink.net> wrote:
> I went through the register definitions and bit field definitions again
> to see if any I am using aren't right for the 440ep, and I noticed that
> EMAC_TRTR_128 is 0x01000000 for both 440gx_enet.h and 405gp_enet.h in
> U-Boot.  For the EP, only the 5 most significant bits aren't reserved,
> and the value in my user manual for EMAC_TRTR_128 is binary 00001.
> Seems likely that it's the same for other 440s and 405s, and someone
> made a typo.  From the most significant end of the register, 00001... =
> 0000 1000 = 0x08 != 0x01.

My user manual says the same, and I believe that this is just a typo
in 405gp_enet.h (as the other definitions match the user manual.) 
That said, I've found many errors in multiple versions of the 440EP
User Manual so I've been going with more what works than what the User
Manual says (in fact when trying to use the Nand Flash Controller we
had to set some reserved bits.)

>  It's page 897 of ppc440ep_um.pdf, and that's the only
> user manual I've got.  If anyone has another 440 or 405 user manual
> handy and would like to check this out I'd appreciate it.  Otherwise
> I'll download a couple other user manuals and if they match mine I'll
> figure out how to submit a bug report.

My most current user manual is Version 1.1 Dated December 3, 2004.

Regards,
-- 
Bradley Remedios
bremedios at gmail.com

[U-Boot-Users] IBM/AMCC 440EP ethernet question

[Miles Gazic]

Bradley,

Apart from the typo I posted about in my previous message, there is one bit field that looks different between the 405GP header file and what the 440EP has.  There is a #define for EMAC_ISR_SYE in the 405 header file, and it's at the same place that something called ALE (alignment error) is at in the 440EP user manual I have.  That bit is set high in the 405 code when the speed is supposed to be 100Mbps.  I don't know what the reprecussions of setting it high are if it really is ALE and not SYE.  But it can't be too important if it's worked like that so far for you.

Do you happen to know what PHY you are using?  Our Broadcom AC101L can do both RMII and MII, the hardware guy thinks all he might have to do is pop in a 50MHz crystal instead of the 25MHz one we have now.  I think it might be worthwhile for me to try that, at least I'll be travelling down the road more well travelled.

Thanks,
Miles

[U-Boot-Users] IBM/AMCC 440EP ethernet question

[Bradley Remedios]

On Fri, 18 Feb 2005 05:31:23 -0800 (GMT-08:00), Miles Gazic
<mgazic@earthlink.net> wrote:
> Do you happen to know what PHY you are using?  Our Broadcom AC101L can do
> both RMII and MII, the hardware guy thinks all he might have to do is pop in a
> 50MHz crystal instead of the 25MHz one we have now.  I think it might be worthwhile
> for me to try that, at least I'll be travelling down the road more well travelled.

We are using a Micrel KS8721B.

In terms of Ethernet I have recently broken it.  We are booting our
board from NAND.  When a Debugger loads U-Boot into SDRAM everything
works great.  When our NAND Bootloader loads U-Boot into SDRAM both
Ethernet and I2C have become broken.  (Auto-Negotiation works but
Transmit is broken, possibly Recieve Also.)
-- 
Bradley Remedios
bremedios at gmail.com

[U-Boot-Users] IBM/AMCC 440EP ethernet question

[Bradley Remedios]

On Fri, 18 Feb 2005 05:31:23 -0800 (GMT-08:00), Miles Gazic
<mgazic@earthlink.net> wrote:
> Do you happen to know what PHY you are using?  Our Broadcom AC101L can do
> both RMII and MII, the hardware guy thinks all he might have to do is pop in a
> 50MHz crystal instead of the 25MHz one we have now.

Before you do any major changes you may want to take a look at what
the SDR0_MFR register is set to on your board.  It also has a portion
that makes note of the ZMII mode.  I was just looking at some stuff
trying to pin-point my problem when I noticed that.

Regards.
-- 
Bradley Remedios
bremedios at gmail.com

[U-Boot-Users] IBM/AMCC 440EP ethernet question

[Miles Gazic]

I'm using a 440EP with MII mode selected, and a Broadcom AC101L phy.
Autonegotiation was failing, so as an experiment, I tried replacing the
start of autonegotiation in 440gx_enet.c, with setting the speed
manually.  I did a miiphy_write to PHY_BMCR (the control register) with
0x8100 (which should specify 10mbps, full duplex).  The miiphy_write
returns  0 which means it doesn't think it failed, but when I look at
the value in the control register as spit out by miiphy_dump, it is
still 0x3000 (which is 100mbps and half-duplex), which is the same value
I always see there.

I don't think this is just a U-boot problem because I can duplicate
what's happening using just a Abatron BDI2000.  When I write a
0x81002400 into the EMAC_STACR register (which should set the control
register of the phy to 0x8100), and then write a 0x00001400 into
EMAC_STACR (which should request a read of the same register), and then
look at the EMAC_STACR register in the debugger, it has the same 0x3000
as I see in U-Boot.  It seems likely to me though that if anyone has
gotten the 440EP to work with MII in U-Boot, then they might be able to
shed some light on what is going wrong for me.

Any advice is appreciated,
Miles

[U-Boot-Users] IBM/AMCC 440EP ethernet question

[Bradley Remedios]

On Tue, 15 Feb 2005 21:09:52 -0800, Miles Gazic <mgazic@earthlink.net> wrote:
> I'm using a 440EP with MII mode selected, and a Broadcom AC101L phy.
> Autonegotiation was failing, so as an experiment, I tried replacing the
> start of autonegotiation in 440gx_enet.c, with setting the speed
> manually.

I'm not sure if I can help much, but I've managed to get the Ethernet
on the 440EP working.  We have an RMII PHY and use the file
405gp_enet.c.

If you use that file, there are no major changes (for RMII) to be
completed.  There was a small bug in the code that occurs for 440
Processors.  I have yet to finnish my port so there are no completed
patches yet.  The bug is simple and simple to fix (a missing else
condition).  Just look for "if( get_pvr() == PVR_440GP_RB)" if you are
interested.

With the 405gp_enet.c code (I am not sure about the 440gx_enet.c code)
the default operation of the ZMII is RMII so you might want to check
that something similar has not been set in the 440gx_enet.c code.

Good Luck,
-- 
Bradley Remedios
bremedios at gmail.com