From: Icenowy Zheng <icenowy@aosc.xyz>
To: u-boot@lists.denx.de
Subject: [U-Boot] [linux-sunxi] Re: [RFC PATCH 1/4] sunxi: add DDR2 support to H3-like DRAM controller
Date: Tue, 10 Jan 2017 17:27:21 +0800 [thread overview]
Message-ID: <969361484040441@web7g.yandex.ru> (raw)
In-Reply-To: <20170109100100.3y5ndqqkt4xgaut3@lukather>
09.01.2017, 18:01, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> On Fri, Jan 06, 2017 at 06:55:05AM +0800, Icenowy Zheng wrote:
>> ?> > + ?????? MCTL_CR_32BIT /* fixme, thats wrong but what boot0 does */ |
>> ?>
>> ?> What's wrong about it?
>>
>> ?V3s DRAM seems to be 16-bit.
>>
>> ?However, boot0 has this bit set, and without this bit, it cannot work.
>>
>> ?According to Jens' guess (only guess), this may be something more
>> ?like full-width and half-width.
>
> Ok. Please put that in the comments then.
Now I think it's not only guess.
See dram_sun8i_a33.h, which has MCTL_CR_BUSW8 = 0 << 12 and MCTL_CR_BUSW16 = 1 << 12.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
next prev parent reply other threads:[~2017-01-10 9:27 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-05 22:55 [U-Boot] [linux-sunxi] Re: [RFC PATCH 1/4] sunxi: add DDR2 support to H3-like DRAM controller Icenowy Zheng
2017-01-09 10:01 ` Maxime Ripard
2017-01-10 9:27 ` Icenowy Zheng [this message]
2017-01-09 10:30 ` Andre Przywara
-- strict thread matches above, loose matches on Subject: below --
2017-01-09 13:06 Icenowy Zheng
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