From mboxrd@z Thu Jan 1 00:00:00 1970 From: Icenowy Zheng Date: Tue, 10 Jan 2017 17:27:21 +0800 Subject: [U-Boot] [linux-sunxi] Re: [RFC PATCH 1/4] sunxi: add DDR2 support to H3-like DRAM controller In-Reply-To: <20170109100100.3y5ndqqkt4xgaut3@lukather> References: <20170106015514.t9B4PJoH@smtp1h.mail.yandex.net> <20170109100100.3y5ndqqkt4xgaut3@lukather> Message-ID: <969361484040441@web7g.yandex.ru> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de 09.01.2017, 18:01, "Maxime Ripard" : > On Fri, Jan 06, 2017 at 06:55:05AM +0800, Icenowy Zheng wrote: >> ?> > + ?????? MCTL_CR_32BIT /* fixme, thats wrong but what boot0 does */ | >> ?> >> ?> What's wrong about it? >> >> ?V3s DRAM seems to be 16-bit. >> >> ?However, boot0 has this bit set, and without this bit, it cannot work. >> >> ?According to Jens' guess (only guess), this may be something more >> ?like full-width and half-width. > > Ok. Please put that in the comments then. Now I think it's not only guess. See dram_sun8i_a33.h, which has MCTL_CR_BUSW8 = 0 << 12 and MCTL_CR_BUSW16 = 1 << 12. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com