From: akshay ts <takshays@yahoo.co.in>
To: u-boot@lists.denx.de
Subject: [U-Boot] Why Cache flush required in some ARM Cortex boards to enable D cache?
Date: Wed, 9 Sep 2009 08:53:53 +0530 (IST) [thread overview]
Message-ID: <977362.71864.qm@web94308.mail.in2.yahoo.com> (raw)
Hi,
I ran into problems when i enabled D cache. But later i found out that cache flush was required before enabling D Cache. What i dont understand is why is it required?. Since earlier D cache is never enabled and so nothing should be present in the cache.
Flushing is only required during context switch/may be interrupts?.
I tried with omap3 board with Arm cortex A8 on it, it worked without a cache flush. I tried with C110 with Arm cortex A8 on it, i had to do a cache flush to make D cache work.
Also if possible please tell me what is a GP device, OMAP3 (CONTROL_STATUS register) seems to be a GP device and hence they are skipping cache flush. I dont know what is this.
Warm Regards,
Akshay
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next reply other threads:[~2009-09-09 3:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-09-09 3:23 akshay ts [this message]
2009-09-09 18:44 ` [U-Boot] Why Cache flush required in some ARM Cortex boards to enable D cache? Dirk Behme
2009-09-11 4:29 ` akshay ts
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