From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= Date: Thu, 27 Sep 2012 22:27:28 +0200 (CEST) Subject: [U-Boot] [PATCH 3/7] mx25: Define more standard clocks In-Reply-To: <354965566.5372561.1348777614543.JavaMail.root@advansee.com> Message-ID: <978272969.5372569.1348777648577.JavaMail.root@advansee.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Define AHB, IPG and CSPI clocks. Signed-off-by: Beno?t Th?baudeau Cc: Stefano Babic --- .../arch/arm/cpu/arm926ejs/mx25/generic.c | 10 ++++++++++ .../arch/arm/include/asm/arch-mx25/clock.h | 5 +++++ 2 files changed, 15 insertions(+) diff --git u-boot-imx-e1eb75b.orig/arch/arm/cpu/arm926ejs/mx25/generic.c u-boot-imx-e1eb75b/arch/arm/cpu/arm926ejs/mx25/generic.c index 5503522..219c9eb 100644 --- u-boot-imx-e1eb75b.orig/arch/arm/cpu/arm926ejs/mx25/generic.c +++ u-boot-imx-e1eb75b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -101,6 +101,11 @@ ulong imx_get_ahbclk(void) return fref / div; } +static ulong imx_get_ipgclk(void) +{ + return imx_get_ahbclk() / 2; +} + ulong imx_get_perclk(int clk) { struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; @@ -120,6 +125,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_ARM_CLK: return imx_get_armclk(); + case MXC_AHB_CLK: + return imx_get_ahbclk(); + case MXC_IPG_CLK: + case MXC_CSPI_CLK: + return imx_get_ipgclk(); case MXC_FEC_CLK: return imx_get_ahbclk(); default: diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx25/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx25/clock.h index a313b80..9823f46 100644 --- u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx25/clock.h +++ u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx25/clock.h @@ -41,6 +41,7 @@ #endif enum mxc_clock { + /* PER clocks (do not change order) */ MXC_CSI_CLK, MXC_EPIT_CLK, MXC_ESAI_CLK, @@ -57,7 +58,11 @@ enum mxc_clock { MXC_SSI1_CLK, MXC_SSI2_CLK, MXC_UART_CLK, + /* Other clocks */ MXC_ARM_CLK, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_CSPI_CLK, MXC_FEC_CLK, MXC_CLK_NUM };